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File indexing completed on 2025-05-11 08:23:10 

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_ll_tim.c
0004   * @author  MCD Application Team
0005   * @brief   TIM LL module driver.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
0019 
0020 /* Includes ------------------------------------------------------------------*/
0021 #include "stm32h7xx_ll_tim.h"
0022 #include "stm32h7xx_ll_bus.h"
0023 
0024 #ifdef  USE_FULL_ASSERT
0025 #include "stm32_assert.h"
0026 #else
0027 #define assert_param(expr) ((void)0U)
0028 #endif /* USE_FULL_ASSERT */
0029 
0030 /** @addtogroup STM32H7xx_LL_Driver
0031   * @{
0032   */
0033 
0034 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24)
0035 
0036 /** @addtogroup TIM_LL
0037   * @{
0038   */
0039 
0040 /* Private types -------------------------------------------------------------*/
0041 /* Private variables ---------------------------------------------------------*/
0042 /* Private constants ---------------------------------------------------------*/
0043 /* Private macros ------------------------------------------------------------*/
0044 /** @addtogroup TIM_LL_Private_Macros
0045   * @{
0046   */
0047 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
0048                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
0049                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
0050                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
0051                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
0052 
0053 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
0054                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
0055                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
0056 
0057 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
0058                                      || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
0059                                      || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
0060                                      || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
0061                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
0062                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
0063                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
0064                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
0065                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
0066                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
0067                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
0068                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
0069                                      || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
0070                                      || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
0071 
0072 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
0073                                       || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
0074 
0075 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
0076                                          || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
0077 
0078 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
0079                                           || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
0080 
0081 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
0082                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
0083                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
0084 
0085 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
0086                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
0087                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
0088                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
0089 
0090 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
0091                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
0092                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
0093                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
0094                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
0095                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
0096                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
0097                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
0098                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
0099                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
0100                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
0101                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
0102                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
0103                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
0104                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
0105                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
0106 
0107 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
0108                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
0109                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
0110 
0111 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
0112                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
0113                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
0114 
0115 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
0116                                                   || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
0117 
0118 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
0119                                          || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
0120 
0121 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
0122                                          || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
0123 
0124 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
0125                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
0126                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
0127                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
0128 
0129 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
0130                                           || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
0131 
0132 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
0133                                              || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
0134 
0135 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
0136                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
0137                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
0138                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
0139                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
0140                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
0141                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
0142                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
0143                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
0144                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
0145                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
0146                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
0147                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
0148                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
0149                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
0150                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
0151 #if defined(TIM_BDTR_BKBID)
0152 
0153 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT)          \
0154                                            || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
0155 #endif /* TIM_BDTR_BKBID */
0156 
0157 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
0158                                            || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
0159 
0160 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
0161                                               || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
0162 
0163 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
0164                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
0165                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
0166                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
0167                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
0168                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
0169                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
0170                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
0171                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
0172                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
0173                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
0174                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
0175                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
0176                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
0177                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
0178                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
0179 #if   defined(TIM_BDTR_BKBID)
0180 
0181 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT)       \
0182                                             || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
0183 #endif /*TIM_BDTR_BKBID */
0184 
0185 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
0186                                                      || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
0187 /**
0188   * @}
0189   */
0190 
0191 
0192 /* Private function prototypes -----------------------------------------------*/
0193 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
0194   * @ingroup RTEMSBSPsARMSTM32H7
0195   * @{
0196   */
0197 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
0198 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
0199 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
0200 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
0201 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
0202 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
0203 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
0204 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
0205 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
0206 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
0207 /**
0208   * @}
0209   */
0210 
0211 /* Exported functions --------------------------------------------------------*/
0212 /** @addtogroup TIM_LL_Exported_Functions
0213   * @{
0214   */
0215 
0216 /** @addtogroup TIM_LL_EF_Init
0217   * @{
0218   */
0219 
0220 /**
0221   * @brief  Set TIMx registers to their reset values.
0222   * @param  TIMx Timer instance
0223   * @retval An ErrorStatus enumeration value:
0224   *          - SUCCESS: TIMx registers are de-initialized
0225   *          - ERROR: invalid TIMx instance
0226   */
0227 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
0228 {
0229   ErrorStatus result = SUCCESS;
0230 
0231   /* Check the parameters */
0232   assert_param(IS_TIM_INSTANCE(TIMx));
0233 
0234   if (TIMx == TIM1)
0235   {
0236     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
0237     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
0238   }
0239 #if defined(TIM2)
0240   else if (TIMx == TIM2)
0241   {
0242     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
0243     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
0244   }
0245 #endif /* TIM2 */
0246 #if defined(TIM3)
0247   else if (TIMx == TIM3)
0248   {
0249     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
0250     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
0251   }
0252 #endif /* TIM3 */
0253 #if defined(TIM4)
0254   else if (TIMx == TIM4)
0255   {
0256     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
0257     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
0258   }
0259 #endif /* TIM4 */
0260 #if defined(TIM5)
0261   else if (TIMx == TIM5)
0262   {
0263     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
0264     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
0265   }
0266 #endif /* TIM5 */
0267 #if defined(TIM6)
0268   else if (TIMx == TIM6)
0269   {
0270     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
0271     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
0272   }
0273 #endif /* TIM6 */
0274 #if defined (TIM7)
0275   else if (TIMx == TIM7)
0276   {
0277     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
0278     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
0279   }
0280 #endif /* TIM7 */
0281 #if defined(TIM8)
0282   else if (TIMx == TIM8)
0283   {
0284     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
0285     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
0286   }
0287 #endif /* TIM8 */
0288 #if defined(TIM12)
0289   else if (TIMx == TIM12)
0290   {
0291     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
0292     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
0293   }
0294 #endif /* TIM12 */
0295 #if defined(TIM13)
0296   else if (TIMx == TIM13)
0297   {
0298     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
0299     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
0300   }
0301 #endif /* TIM13 */
0302 #if defined(TIM14)
0303   else if (TIMx == TIM14)
0304   {
0305     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
0306     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
0307   }
0308 #endif /* TIM14 */
0309 #if defined(TIM15)
0310   else if (TIMx == TIM15)
0311   {
0312     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
0313     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
0314   }
0315 #endif /* TIM15 */
0316 #if defined(TIM16)
0317   else if (TIMx == TIM16)
0318   {
0319     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
0320     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
0321   }
0322 #endif /* TIM16 */
0323 #if defined(TIM17)
0324   else if (TIMx == TIM17)
0325   {
0326     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
0327     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
0328   }
0329 #endif /* TIM17 */
0330   else
0331   {
0332     result = ERROR;
0333   }
0334 
0335   return result;
0336 }
0337 
0338 /**
0339   * @brief  Set the fields of the time base unit configuration data structure
0340   *         to their default values.
0341   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
0342   * @retval None
0343   */
0344 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
0345 {
0346   /* Set the default configuration */
0347   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
0348   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
0349   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
0350   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
0351   TIM_InitStruct->RepetitionCounter = 0x00000000U;
0352 }
0353 
0354 /**
0355   * @brief  Configure the TIMx time base unit.
0356   * @param  TIMx Timer Instance
0357   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
0358   *         (TIMx time base unit configuration data structure)
0359   * @retval An ErrorStatus enumeration value:
0360   *          - SUCCESS: TIMx registers are de-initialized
0361   *          - ERROR: not applicable
0362   */
0363 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
0364 {
0365   uint32_t tmpcr1;
0366 
0367   /* Check the parameters */
0368   assert_param(IS_TIM_INSTANCE(TIMx));
0369   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
0370   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
0371 
0372   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
0373 
0374   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
0375   {
0376     /* Select the Counter Mode */
0377     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
0378   }
0379 
0380   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
0381   {
0382     /* Set the clock division */
0383     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
0384   }
0385 
0386   /* Write to TIMx CR1 */
0387   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
0388 
0389   /* Set the Autoreload value */
0390   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
0391 
0392   /* Set the Prescaler value */
0393   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
0394 
0395   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
0396   {
0397     /* Set the Repetition Counter value */
0398     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
0399   }
0400 
0401   /* Generate an update event to reload the Prescaler
0402      and the repetition counter value (if applicable) immediately */
0403   LL_TIM_GenerateEvent_UPDATE(TIMx);
0404 
0405   return SUCCESS;
0406 }
0407 
0408 /**
0409   * @brief  Set the fields of the TIMx output channel configuration data
0410   *         structure to their default values.
0411   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
0412   *         (the output channel configuration data structure)
0413   * @retval None
0414   */
0415 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
0416 {
0417   /* Set the default configuration */
0418   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
0419   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
0420   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
0421   TIM_OC_InitStruct->CompareValue = 0x00000000U;
0422   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
0423   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
0424   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
0425   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
0426 }
0427 
0428 /**
0429   * @brief  Configure the TIMx output channel.
0430   * @param  TIMx Timer Instance
0431   * @param  Channel This parameter can be one of the following values:
0432   *         @arg @ref LL_TIM_CHANNEL_CH1
0433   *         @arg @ref LL_TIM_CHANNEL_CH2
0434   *         @arg @ref LL_TIM_CHANNEL_CH3
0435   *         @arg @ref LL_TIM_CHANNEL_CH4
0436   *         @arg @ref LL_TIM_CHANNEL_CH5
0437   *         @arg @ref LL_TIM_CHANNEL_CH6
0438   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
0439   *         data structure)
0440   * @retval An ErrorStatus enumeration value:
0441   *          - SUCCESS: TIMx output channel is initialized
0442   *          - ERROR: TIMx output channel is not initialized
0443   */
0444 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
0445 {
0446   ErrorStatus result = ERROR;
0447 
0448   switch (Channel)
0449   {
0450     case LL_TIM_CHANNEL_CH1:
0451       result = OC1Config(TIMx, TIM_OC_InitStruct);
0452       break;
0453     case LL_TIM_CHANNEL_CH2:
0454       result = OC2Config(TIMx, TIM_OC_InitStruct);
0455       break;
0456     case LL_TIM_CHANNEL_CH3:
0457       result = OC3Config(TIMx, TIM_OC_InitStruct);
0458       break;
0459     case LL_TIM_CHANNEL_CH4:
0460       result = OC4Config(TIMx, TIM_OC_InitStruct);
0461       break;
0462     case LL_TIM_CHANNEL_CH5:
0463       result = OC5Config(TIMx, TIM_OC_InitStruct);
0464       break;
0465     case LL_TIM_CHANNEL_CH6:
0466       result = OC6Config(TIMx, TIM_OC_InitStruct);
0467       break;
0468     default:
0469       break;
0470   }
0471 
0472   return result;
0473 }
0474 
0475 /**
0476   * @brief  Set the fields of the TIMx input channel configuration data
0477   *         structure to their default values.
0478   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
0479   *         data structure)
0480   * @retval None
0481   */
0482 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
0483 {
0484   /* Set the default configuration */
0485   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
0486   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
0487   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
0488   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
0489 }
0490 
0491 /**
0492   * @brief  Configure the TIMx input channel.
0493   * @param  TIMx Timer Instance
0494   * @param  Channel This parameter can be one of the following values:
0495   *         @arg @ref LL_TIM_CHANNEL_CH1
0496   *         @arg @ref LL_TIM_CHANNEL_CH2
0497   *         @arg @ref LL_TIM_CHANNEL_CH3
0498   *         @arg @ref LL_TIM_CHANNEL_CH4
0499   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
0500   *         structure)
0501   * @retval An ErrorStatus enumeration value:
0502   *          - SUCCESS: TIMx output channel is initialized
0503   *          - ERROR: TIMx output channel is not initialized
0504   */
0505 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
0506 {
0507   ErrorStatus result = ERROR;
0508 
0509   switch (Channel)
0510   {
0511     case LL_TIM_CHANNEL_CH1:
0512       result = IC1Config(TIMx, TIM_IC_InitStruct);
0513       break;
0514     case LL_TIM_CHANNEL_CH2:
0515       result = IC2Config(TIMx, TIM_IC_InitStruct);
0516       break;
0517     case LL_TIM_CHANNEL_CH3:
0518       result = IC3Config(TIMx, TIM_IC_InitStruct);
0519       break;
0520     case LL_TIM_CHANNEL_CH4:
0521       result = IC4Config(TIMx, TIM_IC_InitStruct);
0522       break;
0523     default:
0524       break;
0525   }
0526 
0527   return result;
0528 }
0529 
0530 /**
0531   * @brief  Fills each TIM_EncoderInitStruct field with its default value
0532   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
0533   *         configuration data structure)
0534   * @retval None
0535   */
0536 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
0537 {
0538   /* Set the default configuration */
0539   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
0540   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
0541   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
0542   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
0543   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
0544   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
0545   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
0546   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
0547   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
0548 }
0549 
0550 /**
0551   * @brief  Configure the encoder interface of the timer instance.
0552   * @param  TIMx Timer Instance
0553   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
0554   *         configuration data structure)
0555   * @retval An ErrorStatus enumeration value:
0556   *          - SUCCESS: TIMx registers are de-initialized
0557   *          - ERROR: not applicable
0558   */
0559 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
0560 {
0561   uint32_t tmpccmr1;
0562   uint32_t tmpccer;
0563 
0564   /* Check the parameters */
0565   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
0566   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
0567   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
0568   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
0569   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
0570   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
0571   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
0572   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
0573   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
0574   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
0575 
0576   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
0577   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
0578 
0579   /* Get the TIMx CCMR1 register value */
0580   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
0581 
0582   /* Get the TIMx CCER register value */
0583   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
0584 
0585   /* Configure TI1 */
0586   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
0587   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
0588   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
0589   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
0590 
0591   /* Configure TI2 */
0592   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
0593   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
0594   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
0595   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
0596 
0597   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
0598   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
0599   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
0600   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
0601   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
0602 
0603   /* Set encoder mode */
0604   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
0605 
0606   /* Write to TIMx CCMR1 */
0607   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
0608 
0609   /* Write to TIMx CCER */
0610   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
0611 
0612   return SUCCESS;
0613 }
0614 
0615 /**
0616   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
0617   *         structure to their default values.
0618   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
0619   *         configuration data structure)
0620   * @retval None
0621   */
0622 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
0623 {
0624   /* Set the default configuration */
0625   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
0626   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
0627   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
0628   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
0629 }
0630 
0631 /**
0632   * @brief  Configure the Hall sensor interface of the timer instance.
0633   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
0634   *       to the TI1 input channel
0635   * @note TIMx slave mode controller is configured in reset mode.
0636           Selected internal trigger is TI1F_ED.
0637   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
0638   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
0639   *       between 2 changes on the inputs. It gives information about motor speed.
0640   * @note Channel 2 is configured in output PWM 2 mode.
0641   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
0642   * @note OC2REF is selected as trigger output on TRGO.
0643   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
0644   *       when TIMx operates in Hall sensor interface mode.
0645   * @param  TIMx Timer Instance
0646   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
0647   *         interface configuration data structure)
0648   * @retval An ErrorStatus enumeration value:
0649   *          - SUCCESS: TIMx registers are de-initialized
0650   *          - ERROR: not applicable
0651   */
0652 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
0653 {
0654   uint32_t tmpcr2;
0655   uint32_t tmpccmr1;
0656   uint32_t tmpccer;
0657   uint32_t tmpsmcr;
0658 
0659   /* Check the parameters */
0660   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
0661   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
0662   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
0663   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
0664 
0665   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
0666   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
0667 
0668   /* Get the TIMx CR2 register value */
0669   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
0670 
0671   /* Get the TIMx CCMR1 register value */
0672   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
0673 
0674   /* Get the TIMx CCER register value */
0675   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
0676 
0677   /* Get the TIMx SMCR register value */
0678   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
0679 
0680   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
0681   tmpcr2 |= TIM_CR2_TI1S;
0682 
0683   /* OC2REF signal is used as trigger output (TRGO) */
0684   tmpcr2 |= LL_TIM_TRGO_OC2REF;
0685 
0686   /* Configure the slave mode controller */
0687   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
0688   tmpsmcr |= LL_TIM_TS_TI1F_ED;
0689   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
0690 
0691   /* Configure input channel 1 */
0692   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
0693   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
0694   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
0695   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
0696 
0697   /* Configure input channel 2 */
0698   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
0699   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
0700 
0701   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
0702   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
0703   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
0704   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
0705 
0706   /* Write to TIMx CR2 */
0707   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
0708 
0709   /* Write to TIMx SMCR */
0710   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
0711 
0712   /* Write to TIMx CCMR1 */
0713   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
0714 
0715   /* Write to TIMx CCER */
0716   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
0717 
0718   /* Write to TIMx CCR2 */
0719   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
0720 
0721   return SUCCESS;
0722 }
0723 
0724 /**
0725   * @brief  Set the fields of the Break and Dead Time configuration data structure
0726   *         to their default values.
0727   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
0728   *         data structure)
0729   * @retval None
0730   */
0731 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
0732 {
0733   /* Set the default configuration */
0734   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
0735   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
0736   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
0737   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
0738   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
0739   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
0740   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
0741 #if defined(TIM_BDTR_BKBID)
0742   TIM_BDTRInitStruct->BreakAFMode     = LL_TIM_BREAK_AFMODE_INPUT;
0743 #endif /* TIM_BDTR_BKBID */
0744   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
0745   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
0746   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
0747 #if defined(TIM_BDTR_BKBID)
0748   TIM_BDTRInitStruct->Break2AFMode    = LL_TIM_BREAK2_AFMODE_INPUT;
0749 #endif /*TIM_BDTR_BKBID */
0750   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
0751 }
0752 
0753 /**
0754   * @brief  Configure the Break and Dead Time feature of the timer instance.
0755   * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
0756   *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
0757   *  can be necessary to configure all of them during the first write access to
0758   *  the TIMx_BDTR register.
0759   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
0760   *       a timer instance provides a break input.
0761   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
0762   *       a timer instance provides a second break input.
0763   * @param  TIMx Timer Instance
0764   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
0765   *         data structure)
0766   * @retval An ErrorStatus enumeration value:
0767   *          - SUCCESS: Break and Dead Time is initialized
0768   *          - ERROR: not applicable
0769   */
0770 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
0771 {
0772   uint32_t tmpbdtr = 0;
0773 
0774   /* Check the parameters */
0775   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
0776   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
0777   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
0778   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
0779   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
0780   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
0781   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
0782   assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
0783 #if defined(TIM_BDTR_BKBID)
0784   assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
0785 #endif /*TIM_BDTR_BKBID */
0786 
0787   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
0788   the OSSI State, the dead time value and the Automatic Output Enable Bit */
0789 
0790   /* Set the BDTR bits */
0791   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
0792   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
0793   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
0794   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
0795   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
0796   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
0797   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
0798   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
0799 #if defined(TIM_BDTR_BKBID)
0800   MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
0801 #endif /*TIM_BDTR_BKBID */
0802 
0803   if (IS_TIM_BKIN2_INSTANCE(TIMx))
0804   {
0805     assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
0806     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
0807     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
0808 #if defined(TIM_BDTR_BKBID)
0809     assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
0810 #endif /*TIM_BDTR_BKBID */
0811 
0812     /* Set the BREAK2 input related BDTR bit-fields */
0813     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
0814     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
0815     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
0816 #if defined(TIM_BDTR_BKBID)
0817     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
0818 #endif /*TIM_BDTR_BKBID */
0819   }
0820 
0821   /* Set TIMx_BDTR */
0822   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
0823 
0824   return SUCCESS;
0825 }
0826 /**
0827   * @}
0828   */
0829 
0830 /**
0831   * @}
0832   */
0833 
0834 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
0835   *  @brief   Private functions
0836   * @{
0837   */
0838 /**
0839   * @brief  Configure the TIMx output channel 1.
0840   * @param  TIMx Timer Instance
0841   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
0842   * @retval An ErrorStatus enumeration value:
0843   *          - SUCCESS: TIMx registers are de-initialized
0844   *          - ERROR: not applicable
0845   */
0846 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
0847 {
0848   uint32_t tmpccmr1;
0849   uint32_t tmpccer;
0850   uint32_t tmpcr2;
0851 
0852   /* Check the parameters */
0853   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
0854   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
0855   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
0856   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
0857 
0858   /* Disable the Channel 1: Reset the CC1E Bit */
0859   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
0860 
0861   /* Get the TIMx CCER register value */
0862   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
0863 
0864   /* Get the TIMx CR2 register value */
0865   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
0866 
0867   /* Get the TIMx CCMR1 register value */
0868   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
0869 
0870   /* Reset Capture/Compare selection Bits */
0871   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
0872 
0873   /* Set the Output Compare Mode */
0874   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
0875 
0876   /* Set the Output Compare Polarity */
0877   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
0878 
0879   /* Set the Output State */
0880   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
0881 
0882   if (IS_TIM_BREAK_INSTANCE(TIMx))
0883   {
0884     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
0885     assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
0886     assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
0887     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
0888 
0889     /* Set the complementary output Polarity */
0890     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
0891 
0892     /* Set the complementary output State */
0893     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
0894 
0895     /* Set the Output Idle state */
0896     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
0897 
0898     /* Set the complementary output Idle state */
0899     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
0900   }
0901 
0902   /* Write to TIMx CR2 */
0903   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
0904 
0905   /* Write to TIMx CCMR1 */
0906   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
0907 
0908   /* Set the Capture Compare Register value */
0909   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
0910 
0911   /* Write to TIMx CCER */
0912   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
0913 
0914   return SUCCESS;
0915 }
0916 
0917 /**
0918   * @brief  Configure the TIMx output channel 2.
0919   * @param  TIMx Timer Instance
0920   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
0921   * @retval An ErrorStatus enumeration value:
0922   *          - SUCCESS: TIMx registers are de-initialized
0923   *          - ERROR: not applicable
0924   */
0925 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
0926 {
0927   uint32_t tmpccmr1;
0928   uint32_t tmpccer;
0929   uint32_t tmpcr2;
0930 
0931   /* Check the parameters */
0932   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
0933   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
0934   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
0935   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
0936 
0937   /* Disable the Channel 2: Reset the CC2E Bit */
0938   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
0939 
0940   /* Get the TIMx CCER register value */
0941   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
0942 
0943   /* Get the TIMx CR2 register value */
0944   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
0945 
0946   /* Get the TIMx CCMR1 register value */
0947   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
0948 
0949   /* Reset Capture/Compare selection Bits */
0950   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
0951 
0952   /* Select the Output Compare Mode */
0953   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
0954 
0955   /* Set the Output Compare Polarity */
0956   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
0957 
0958   /* Set the Output State */
0959   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
0960 
0961   if (IS_TIM_BREAK_INSTANCE(TIMx))
0962   {
0963     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
0964     assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
0965     assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
0966     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
0967 
0968     /* Set the complementary output Polarity */
0969     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
0970 
0971     /* Set the complementary output State */
0972     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
0973 
0974     /* Set the Output Idle state */
0975     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
0976 
0977     /* Set the complementary output Idle state */
0978     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
0979   }
0980 
0981   /* Write to TIMx CR2 */
0982   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
0983 
0984   /* Write to TIMx CCMR1 */
0985   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
0986 
0987   /* Set the Capture Compare Register value */
0988   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
0989 
0990   /* Write to TIMx CCER */
0991   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
0992 
0993   return SUCCESS;
0994 }
0995 
0996 /**
0997   * @brief  Configure the TIMx output channel 3.
0998   * @param  TIMx Timer Instance
0999   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
1000   * @retval An ErrorStatus enumeration value:
1001   *          - SUCCESS: TIMx registers are de-initialized
1002   *          - ERROR: not applicable
1003   */
1004 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1005 {
1006   uint32_t tmpccmr2;
1007   uint32_t tmpccer;
1008   uint32_t tmpcr2;
1009 
1010   /* Check the parameters */
1011   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1012   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1013   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1014   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1015 
1016   /* Disable the Channel 3: Reset the CC3E Bit */
1017   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
1018 
1019   /* Get the TIMx CCER register value */
1020   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
1021 
1022   /* Get the TIMx CR2 register value */
1023   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1024 
1025   /* Get the TIMx CCMR2 register value */
1026   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1027 
1028   /* Reset Capture/Compare selection Bits */
1029   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
1030 
1031   /* Select the Output Compare Mode */
1032   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
1033 
1034   /* Set the Output Compare Polarity */
1035   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
1036 
1037   /* Set the Output State */
1038   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1039 
1040   if (IS_TIM_BREAK_INSTANCE(TIMx))
1041   {
1042     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1043     assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1044     assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1045     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1046 
1047     /* Set the complementary output Polarity */
1048     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1049 
1050     /* Set the complementary output State */
1051     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1052 
1053     /* Set the Output Idle state */
1054     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1055 
1056     /* Set the complementary output Idle state */
1057     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1058   }
1059 
1060   /* Write to TIMx CR2 */
1061   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1062 
1063   /* Write to TIMx CCMR2 */
1064   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1065 
1066   /* Set the Capture Compare Register value */
1067   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1068 
1069   /* Write to TIMx CCER */
1070   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1071 
1072   return SUCCESS;
1073 }
1074 
1075 /**
1076   * @brief  Configure the TIMx output channel 4.
1077   * @param  TIMx Timer Instance
1078   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1079   * @retval An ErrorStatus enumeration value:
1080   *          - SUCCESS: TIMx registers are de-initialized
1081   *          - ERROR: not applicable
1082   */
1083 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1084 {
1085   uint32_t tmpccmr2;
1086   uint32_t tmpccer;
1087   uint32_t tmpcr2;
1088 
1089   /* Check the parameters */
1090   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1091   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1092   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1093   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1094 
1095   /* Disable the Channel 4: Reset the CC4E Bit */
1096   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1097 
1098   /* Get the TIMx CCER register value */
1099   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1100 
1101   /* Get the TIMx CR2 register value */
1102   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
1103 
1104   /* Get the TIMx CCMR2 register value */
1105   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1106 
1107   /* Reset Capture/Compare selection Bits */
1108   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1109 
1110   /* Select the Output Compare Mode */
1111   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1112 
1113   /* Set the Output Compare Polarity */
1114   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1115 
1116   /* Set the Output State */
1117   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1118 
1119   if (IS_TIM_BREAK_INSTANCE(TIMx))
1120   {
1121     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1122 
1123     /* Set the Output Idle state */
1124     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1125   }
1126 
1127   /* Write to TIMx CR2 */
1128   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1129 
1130   /* Write to TIMx CCMR2 */
1131   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1132 
1133   /* Set the Capture Compare Register value */
1134   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1135 
1136   /* Write to TIMx CCER */
1137   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1138 
1139   return SUCCESS;
1140 }
1141 
1142 /**
1143   * @brief  Configure the TIMx output channel 5.
1144   * @param  TIMx Timer Instance
1145   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1146   * @retval An ErrorStatus enumeration value:
1147   *          - SUCCESS: TIMx registers are de-initialized
1148   *          - ERROR: not applicable
1149   */
1150 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1151 {
1152   uint32_t tmpccmr3;
1153   uint32_t tmpccer;
1154 
1155   /* Check the parameters */
1156   assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1157   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1158   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1159   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1160   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1161   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1162 
1163   /* Disable the Channel 5: Reset the CC5E Bit */
1164   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1165 
1166   /* Get the TIMx CCER register value */
1167   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1168 
1169   /* Get the TIMx CCMR3 register value */
1170   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1171 
1172   /* Select the Output Compare Mode */
1173   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1174 
1175   /* Set the Output Compare Polarity */
1176   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1177 
1178   /* Set the Output State */
1179   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1180 
1181   if (IS_TIM_BREAK_INSTANCE(TIMx))
1182   {
1183     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1184     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1185 
1186     /* Set the Output Idle state */
1187     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1188 
1189   }
1190 
1191   /* Write to TIMx CCMR3 */
1192   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1193 
1194   /* Set the Capture Compare Register value */
1195   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1196 
1197   /* Write to TIMx CCER */
1198   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1199 
1200   return SUCCESS;
1201 }
1202 
1203 /**
1204   * @brief  Configure the TIMx output channel 6.
1205   * @param  TIMx Timer Instance
1206   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1207   * @retval An ErrorStatus enumeration value:
1208   *          - SUCCESS: TIMx registers are de-initialized
1209   *          - ERROR: not applicable
1210   */
1211 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1212 {
1213   uint32_t tmpccmr3;
1214   uint32_t tmpccer;
1215 
1216   /* Check the parameters */
1217   assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1218   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1219   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1220   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1221   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1222   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1223 
1224   /* Disable the Channel 5: Reset the CC6E Bit */
1225   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1226 
1227   /* Get the TIMx CCER register value */
1228   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1229 
1230   /* Get the TIMx CCMR3 register value */
1231   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1232 
1233   /* Select the Output Compare Mode */
1234   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1235 
1236   /* Set the Output Compare Polarity */
1237   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1238 
1239   /* Set the Output State */
1240   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1241 
1242   if (IS_TIM_BREAK_INSTANCE(TIMx))
1243   {
1244     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1245     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1246 
1247     /* Set the Output Idle state */
1248     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1249   }
1250 
1251   /* Write to TIMx CCMR3 */
1252   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1253 
1254   /* Set the Capture Compare Register value */
1255   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1256 
1257   /* Write to TIMx CCER */
1258   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1259 
1260   return SUCCESS;
1261 }
1262 
1263 /**
1264   * @brief  Configure the TIMx input channel 1.
1265   * @param  TIMx Timer Instance
1266   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1267   * @retval An ErrorStatus enumeration value:
1268   *          - SUCCESS: TIMx registers are de-initialized
1269   *          - ERROR: not applicable
1270   */
1271 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1272 {
1273   /* Check the parameters */
1274   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1275   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1276   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1277   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1278   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1279 
1280   /* Disable the Channel 1: Reset the CC1E Bit */
1281   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1282 
1283   /* Select the Input and set the filter and the prescaler value */
1284   MODIFY_REG(TIMx->CCMR1,
1285              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1286              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1287 
1288   /* Select the Polarity and set the CC1E Bit */
1289   MODIFY_REG(TIMx->CCER,
1290              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1291              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1292 
1293   return SUCCESS;
1294 }
1295 
1296 /**
1297   * @brief  Configure the TIMx input channel 2.
1298   * @param  TIMx Timer Instance
1299   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1300   * @retval An ErrorStatus enumeration value:
1301   *          - SUCCESS: TIMx registers are de-initialized
1302   *          - ERROR: not applicable
1303   */
1304 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1305 {
1306   /* Check the parameters */
1307   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1308   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1309   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1310   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1311   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1312 
1313   /* Disable the Channel 2: Reset the CC2E Bit */
1314   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1315 
1316   /* Select the Input and set the filter and the prescaler value */
1317   MODIFY_REG(TIMx->CCMR1,
1318              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1319              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1320 
1321   /* Select the Polarity and set the CC2E Bit */
1322   MODIFY_REG(TIMx->CCER,
1323              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1324              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1325 
1326   return SUCCESS;
1327 }
1328 
1329 /**
1330   * @brief  Configure the TIMx input channel 3.
1331   * @param  TIMx Timer Instance
1332   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1333   * @retval An ErrorStatus enumeration value:
1334   *          - SUCCESS: TIMx registers are de-initialized
1335   *          - ERROR: not applicable
1336   */
1337 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1338 {
1339   /* Check the parameters */
1340   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1341   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1342   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1343   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1344   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1345 
1346   /* Disable the Channel 3: Reset the CC3E Bit */
1347   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1348 
1349   /* Select the Input and set the filter and the prescaler value */
1350   MODIFY_REG(TIMx->CCMR2,
1351              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1352              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1353 
1354   /* Select the Polarity and set the CC3E Bit */
1355   MODIFY_REG(TIMx->CCER,
1356              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1357              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1358 
1359   return SUCCESS;
1360 }
1361 
1362 /**
1363   * @brief  Configure the TIMx input channel 4.
1364   * @param  TIMx Timer Instance
1365   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1366   * @retval An ErrorStatus enumeration value:
1367   *          - SUCCESS: TIMx registers are de-initialized
1368   *          - ERROR: not applicable
1369   */
1370 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1371 {
1372   /* Check the parameters */
1373   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1374   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1375   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1376   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1377   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1378 
1379   /* Disable the Channel 4: Reset the CC4E Bit */
1380   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1381 
1382   /* Select the Input and set the filter and the prescaler value */
1383   MODIFY_REG(TIMx->CCMR2,
1384              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1385              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1386 
1387   /* Select the Polarity and set the CC4E Bit */
1388   MODIFY_REG(TIMx->CCER,
1389              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1390              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1391 
1392   return SUCCESS;
1393 }
1394 
1395 
1396 /**
1397   * @}
1398   */
1399 
1400 /**
1401   * @}
1402   */
1403 
1404 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17  || TIM23  || TIM24 */
1405 
1406 /**
1407   * @}
1408   */
1409 
1410 #endif /* USE_FULL_LL_DRIVER */
1411
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