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File indexing completed on 2025-05-11 08:23:10 

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_ll_rcc.c
0004   * @author  MCD Application Team
0005   * @brief   RCC LL module driver.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file in
0013   * the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   ******************************************************************************
0016   */
0017 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
0018 
0019 /* Includes ------------------------------------------------------------------*/
0020 #include "stm32h7xx_ll_rcc.h"
0021 #include "stm32h7xx_ll_bus.h"
0022 #ifdef  USE_FULL_ASSERT
0023 #include "stm32_assert.h"
0024 #else
0025 #define assert_param(expr) ((void)0U)
0026 #endif
0027 
0028 /** @addtogroup STM32H7xx_LL_Driver
0029   * @{
0030   */
0031 
0032 #if defined(RCC)
0033 
0034 /** @addtogroup RCC_LL
0035   * @{
0036   */
0037 
0038 /* Private types -------------------------------------------------------------*/
0039 /* Private variables ---------------------------------------------------------*/
0040 /** @addtogroup RCC_LL_Private_Variables
0041   * @{
0042   */
0043 const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
0044 
0045 /**
0046   * @}
0047   */
0048 /* Private constants ---------------------------------------------------------*/
0049 /* Private macros ------------------------------------------------------------*/
0050 /** @addtogroup RCC_LL_Private_Macros
0051   * @{
0052   */
0053 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART16_CLKSOURCE) \
0054                                             || ((__VALUE__) == LL_RCC_USART234578_CLKSOURCE))
0055 
0056 
0057 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C123_CLKSOURCE) \
0058                                             || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
0059 
0060 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)  \
0061                                             || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)  \
0062                                             || ((__VALUE__) == LL_RCC_LPTIM345_CLKSOURCE))
0063 
0064 #if defined(SAI3)
0065 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
0066                                             || ((__VALUE__) == LL_RCC_SAI23_CLKSOURCE) \
0067                                             || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
0068                                             || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
0069 #elif defined(SAI4)
0070 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
0071                                             || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
0072                                             || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
0073 #else
0074 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
0075                                             || ((__VALUE__) == LL_RCC_SAI2A_CLKSOURCE) \
0076                                             || ((__VALUE__) == LL_RCC_SAI2B_CLKSOURCE))
0077 #endif /* SAI3 */
0078 
0079 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SPI123_CLKSOURCE) \
0080                                             || ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \
0081                                             || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
0082 
0083 /**
0084   * @}
0085   */
0086 
0087 /* Private function prototypes -----------------------------------------------*/
0088 /** @defgroup RCC_LL_Private_Functions RCC Private functions
0089   * @ingroup RTEMSBSPsARMSTM32H7
0090   * @{
0091   */
0092 static uint32_t RCC_GetSystemClockFreq(void);
0093 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
0094 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
0095 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
0096 static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
0097 static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
0098 
0099 /**
0100   * @}
0101   */
0102 
0103 
0104 /* Exported functions --------------------------------------------------------*/
0105 /** @addtogroup RCC_LL_Exported_Functions
0106   * @{
0107   */
0108 
0109 /** @addtogroup RCC_LL_EF_Init
0110   * @{
0111   */
0112 
0113 /**
0114   * @brief  Resets the RCC clock configuration to the default reset state.
0115   * @note   The default reset state of the clock configuration is given below:
0116   *            - HSI ON and used as system clock source
0117   *            - HSE, PLL1, PLL2 and PLL3 OFF
0118   *            - AHB, APB Bus pre-scaler set to 1.
0119   *            - CSS, MCO1 and MCO2 OFF
0120   *            - All interrupts disabled
0121   * @note   This function doesn't modify the configuration of the
0122   *            - Peripheral clocks
0123   *            - LSI, LSE and RTC clocks
0124   * @retval None
0125   */
0126 void LL_RCC_DeInit(void)
0127 {
0128   /* Increasing the CPU frequency */
0129   if (FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
0130   {
0131     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
0132     MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
0133   }
0134 
0135   /* Set HSION bit */
0136   SET_BIT(RCC->CR, RCC_CR_HSION);
0137 
0138   /* Wait for HSI READY bit */
0139   while (LL_RCC_HSI_IsReady() == 0U)
0140   {}
0141 
0142   /* Reset CFGR register */
0143   CLEAR_REG(RCC->CFGR);
0144 
0145   /* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */
0146   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON |  RCC_CR_HSI48ON  \
0147             | RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
0148 
0149   /* Wait for PLL1 READY bit to be reset */
0150   while (LL_RCC_PLL1_IsReady() != 0U)
0151   {}
0152 
0153   /* Wait for PLL2 READY bit to be reset */
0154   while (LL_RCC_PLL2_IsReady() != 0U)
0155   {}
0156 
0157   /* Wait for PLL3 READY bit to be reset */
0158   while (LL_RCC_PLL3_IsReady() != 0U)
0159   {}
0160 
0161 #if defined(RCC_D1CFGR_HPRE)
0162   /* Reset D1CFGR register */
0163   CLEAR_REG(RCC->D1CFGR);
0164 
0165   /* Reset D2CFGR register */
0166   CLEAR_REG(RCC->D2CFGR);
0167 
0168   /* Reset D3CFGR register */
0169   CLEAR_REG(RCC->D3CFGR);
0170 #else
0171   /* Reset CDCFGR1 register */
0172   CLEAR_REG(RCC->CDCFGR1);
0173 
0174   /* Reset CDCFGR2 register */
0175   CLEAR_REG(RCC->CDCFGR2);
0176 
0177   /* Reset SRDCFGR register */
0178   CLEAR_REG(RCC->SRDCFGR);
0179 
0180 #endif /* RCC_D1CFGR_HPRE */
0181 
0182   /* Reset PLLCKSELR register to default value */
0183   RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM1_5 | RCC_PLLCKSELR_DIVM2_5 | RCC_PLLCKSELR_DIVM3_5;
0184 
0185   /* Reset PLLCFGR register to default value */
0186   LL_RCC_WriteReg(PLLCFGR, 0x01FF0000U);
0187 
0188   /* Reset PLL1DIVR register to default value */
0189   LL_RCC_WriteReg(PLL1DIVR, 0x01010280U);
0190 
0191   /* Reset PLL1FRACR register */
0192   CLEAR_REG(RCC->PLL1FRACR);
0193 
0194   /* Reset PLL2DIVR register to default value */
0195   LL_RCC_WriteReg(PLL2DIVR, 0x01010280U);
0196 
0197   /* Reset PLL2FRACR register */
0198   CLEAR_REG(RCC->PLL2FRACR);
0199 
0200   /* Reset PLL3DIVR register to default value */
0201   LL_RCC_WriteReg(PLL3DIVR, 0x01010280U);
0202 
0203   /* Reset PLL3FRACR register */
0204   CLEAR_REG(RCC->PLL3FRACR);
0205 
0206   /* Reset HSEBYP bit */
0207   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
0208 
0209   /* Disable all interrupts */
0210   CLEAR_REG(RCC->CIER);
0211 
0212   /* Clear all interrupts */
0213   SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC
0214           | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC
0215           | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC);
0216 
0217   /* Clear reset source flags */
0218   SET_BIT(RCC->RSR, RCC_RSR_RMVF);
0219 
0220   /* Decreasing the number of wait states because of lower CPU frequency */
0221   if (FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
0222   {
0223     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
0224     MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
0225   }
0226 
0227 }
0228 
0229 /**
0230   * @}
0231   */
0232 
0233 /** @addtogroup RCC_LL_EF_Get_Freq
0234   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
0235   *         and different peripheral clocks available on the device.
0236   * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
0237   * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
0238   * @note   If SYSCLK source is CSI, function returns values based on CSI_VALUE(***)
0239   * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
0240   *         or HSI_VALUE(*) multiplied/divided by the PLL factors.
0241   * @note   (*) HSI_VALUE is a constant defined in header file (default value
0242   *             64 MHz) divider by HSIDIV, but the real value may vary depending on
0243   *             on the variations in voltage and temperature.
0244   * @note   (**) HSE_VALUE is a constant defined in header file (default value
0245   *              25 MHz), user has to ensure that HSE_VALUE is same as the real
0246   *              frequency of the crystal used. Otherwise, this function may
0247   *              have wrong result.
0248   * @note   (***) CSI_VALUE is a constant defined in header file (default value
0249   *               4 MHz) but the real value may vary depending on the variations
0250   *               in voltage and temperature.
0251   * @note   The result of this function could be incorrect when using fractional
0252   *         value for HSE crystal.
0253   * @note   This function can be used by the user application to compute the
0254   *         baud-rate for the communication peripherals or configure other parameters.
0255   * @{
0256   */
0257 
0258 /**
0259   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
0260   * @note   Each time SYSCLK, HCLK, PCLK1, PCLK2, PCLK3 and/or PCLK4 clock changes, this function
0261   *         must be called to update structure fields. Otherwise, any
0262   *         configuration based on this function will be incorrect.
0263   * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
0264   * @retval None
0265   */
0266 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
0267 {
0268   /* Get SYSCLK frequency */
0269   RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
0270 
0271   /* HCLK clock frequency */
0272   RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
0273 
0274   /* PCLK1 clock frequency */
0275   RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
0276 
0277   /* PCLK2 clock frequency */
0278   RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
0279 
0280   /* PCLK3 clock frequency */
0281   RCC_Clocks->PCLK3_Frequency  = RCC_GetPCLK3ClockFreq(RCC_Clocks->HCLK_Frequency);
0282 
0283   /* PCLK4 clock frequency */
0284   RCC_Clocks->PCLK4_Frequency  = RCC_GetPCLK4ClockFreq(RCC_Clocks->HCLK_Frequency);
0285 }
0286 
0287 /**
0288   * @brief  Return PLL1 clocks frequencies
0289   * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
0290   * @retval None
0291   */
0292 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
0293 {
0294   uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
0295   uint32_t m, n, fracn = 0U;
0296 
0297   /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
0298      SYSCLK = PLL_VCO / PLLP
0299   */
0300   pllsource = LL_RCC_PLL_GetSource();
0301 
0302   switch (pllsource)
0303   {
0304     case LL_RCC_PLLSOURCE_HSI:
0305       if (LL_RCC_HSI_IsReady() != 0U)
0306       {
0307         pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
0308       }
0309       break;
0310 
0311     case LL_RCC_PLLSOURCE_CSI:
0312       if (LL_RCC_CSI_IsReady() != 0U)
0313       {
0314         pllinputfreq = CSI_VALUE;
0315       }
0316       break;
0317 
0318     case LL_RCC_PLLSOURCE_HSE:
0319       if (LL_RCC_HSE_IsReady() != 0U)
0320       {
0321         pllinputfreq = HSE_VALUE;
0322       }
0323       break;
0324 
0325     case LL_RCC_PLLSOURCE_NONE:
0326     default:
0327       /* PLL clock disabled */
0328       break;
0329   }
0330 
0331   PLL_Clocks->PLL_P_Frequency = 0U;
0332   PLL_Clocks->PLL_Q_Frequency = 0U;
0333   PLL_Clocks->PLL_R_Frequency = 0U;
0334 
0335   m = LL_RCC_PLL1_GetM();
0336   n = LL_RCC_PLL1_GetN();
0337   if (LL_RCC_PLL1FRACN_IsEnabled() != 0U)
0338   {
0339     fracn = LL_RCC_PLL1_GetFRACN();
0340   }
0341 
0342   if (m != 0U)
0343   {
0344     if (LL_RCC_PLL1P_IsEnabled() != 0U)
0345     {
0346       PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetP());
0347     }
0348 
0349     if (LL_RCC_PLL1Q_IsEnabled() != 0U)
0350     {
0351       PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetQ());
0352     }
0353 
0354     if (LL_RCC_PLL1R_IsEnabled() != 0U)
0355     {
0356       PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetR());
0357     }
0358   }
0359 }
0360 
0361 /**
0362   * @brief  Return PLL2 clocks frequencies
0363   * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
0364   * @retval None
0365   */
0366 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
0367 {
0368   uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
0369   uint32_t m, n, fracn = 0U;
0370 
0371   /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
0372      SYSCLK = PLL_VCO / PLLP
0373   */
0374   pllsource = LL_RCC_PLL_GetSource();
0375 
0376   switch (pllsource)
0377   {
0378     case LL_RCC_PLLSOURCE_HSI:
0379       if (LL_RCC_HSI_IsReady() != 0U)
0380       {
0381         pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
0382       }
0383       break;
0384 
0385     case LL_RCC_PLLSOURCE_CSI:
0386       if (LL_RCC_CSI_IsReady() != 0U)
0387       {
0388         pllinputfreq = CSI_VALUE;
0389       }
0390       break;
0391 
0392     case LL_RCC_PLLSOURCE_HSE:
0393       if (LL_RCC_HSE_IsReady() != 0U)
0394       {
0395         pllinputfreq = HSE_VALUE;
0396       }
0397       break;
0398 
0399     case LL_RCC_PLLSOURCE_NONE:
0400     default:
0401       /* PLL clock disabled */
0402       break;
0403   }
0404 
0405   PLL_Clocks->PLL_P_Frequency = 0U;
0406   PLL_Clocks->PLL_Q_Frequency = 0U;
0407   PLL_Clocks->PLL_R_Frequency = 0U;
0408 
0409   m = LL_RCC_PLL2_GetM();
0410   n = LL_RCC_PLL2_GetN();
0411   if (LL_RCC_PLL2FRACN_IsEnabled() != 0U)
0412   {
0413     fracn = LL_RCC_PLL2_GetFRACN();
0414   }
0415 
0416   if (m != 0U)
0417   {
0418     if (LL_RCC_PLL2P_IsEnabled() != 0U)
0419     {
0420       PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetP());
0421     }
0422 
0423     if (LL_RCC_PLL2Q_IsEnabled() != 0U)
0424     {
0425       PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetQ());
0426     }
0427 
0428     if (LL_RCC_PLL2R_IsEnabled() != 0U)
0429     {
0430       PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetR());
0431     }
0432   }
0433 }
0434 
0435 /**
0436   * @brief  Return PLL3 clocks frequencies
0437   * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
0438   * @retval None
0439   */
0440 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
0441 {
0442   uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
0443   uint32_t m, n, fracn = 0U;
0444 
0445   /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
0446      SYSCLK = PLL_VCO / PLLP
0447   */
0448   pllsource = LL_RCC_PLL_GetSource();
0449 
0450   switch (pllsource)
0451   {
0452     case LL_RCC_PLLSOURCE_HSI:
0453       if (LL_RCC_HSI_IsReady() != 0U)
0454       {
0455         pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
0456       }
0457       break;
0458 
0459     case LL_RCC_PLLSOURCE_CSI:
0460       if (LL_RCC_CSI_IsReady() != 0U)
0461       {
0462         pllinputfreq = CSI_VALUE;
0463       }
0464       break;
0465 
0466     case LL_RCC_PLLSOURCE_HSE:
0467       if (LL_RCC_HSE_IsReady() != 0U)
0468       {
0469         pllinputfreq = HSE_VALUE;
0470       }
0471       break;
0472 
0473     case LL_RCC_PLLSOURCE_NONE:
0474     default:
0475       /* PLL clock disabled */
0476       break;
0477   }
0478 
0479   PLL_Clocks->PLL_P_Frequency = 0U;
0480   PLL_Clocks->PLL_Q_Frequency = 0U;
0481   PLL_Clocks->PLL_R_Frequency = 0U;
0482 
0483   m = LL_RCC_PLL3_GetM();
0484   n = LL_RCC_PLL3_GetN();
0485   if (LL_RCC_PLL3FRACN_IsEnabled() != 0U)
0486   {
0487     fracn = LL_RCC_PLL3_GetFRACN();
0488   }
0489 
0490   if ((m != 0U) && (pllinputfreq != 0U))
0491   {
0492     if (LL_RCC_PLL3P_IsEnabled() != 0U)
0493     {
0494       PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetP());
0495     }
0496 
0497     if (LL_RCC_PLL3Q_IsEnabled() != 0U)
0498     {
0499       PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetQ());
0500     }
0501 
0502     if (LL_RCC_PLL3R_IsEnabled() != 0U)
0503     {
0504       PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetR());
0505     }
0506   }
0507 }
0508 
0509 /**
0510   * @brief  Helper function to calculate the PLL frequency output
0511   * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (),
0512   *             @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP ());
0513   * @param  PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
0514   * @param  M      Between 1 and 63
0515   * @param  N      Between 4 and 512
0516   * @param  FRACN  Between 0 and 0x1FFF
0517   * @param  PQR    VCO output divider (P, Q or R)
0518   *                Between 1 and 128, except for PLL1P Odd value not allowed
0519   * @retval PLL1 clock frequency (in Hz)
0520   */
0521 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
0522 {
0523   float_t freq;
0524 
0525   freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN / (float_t)0x2000));
0526 
0527   freq = freq / (float_t)PQR;
0528 
0529   return (uint32_t)freq;
0530 }
0531 
0532 /**
0533   * @brief  Return USARTx clock frequency
0534   * @param  USARTxSource This parameter can be one of the following values:
0535   *         @arg @ref LL_RCC_USART16_CLKSOURCE
0536   *         @arg @ref LL_RCC_USART234578_CLKSOURCE
0537   * @retval USART clock frequency (in Hz)
0538   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
0539   */
0540 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
0541 {
0542   uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
0543   LL_PLL_ClocksTypeDef PLL_Clocks;
0544 
0545   /* Check parameter */
0546   assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
0547 
0548   switch (LL_RCC_GetUSARTClockSource(USARTxSource))
0549   {
0550     case LL_RCC_USART16_CLKSOURCE_PCLK2:
0551       usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
0552       break;
0553 
0554     case LL_RCC_USART234578_CLKSOURCE_PCLK1:
0555       usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
0556       break;
0557 
0558     case LL_RCC_USART16_CLKSOURCE_PLL2Q:
0559     case LL_RCC_USART234578_CLKSOURCE_PLL2Q:
0560       if (LL_RCC_PLL2_IsReady() != 0U)
0561       {
0562         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
0563         usart_frequency = PLL_Clocks.PLL_Q_Frequency;
0564       }
0565       break;
0566 
0567     case LL_RCC_USART16_CLKSOURCE_PLL3Q:
0568     case LL_RCC_USART234578_CLKSOURCE_PLL3Q:
0569       if (LL_RCC_PLL3_IsReady() != 0U)
0570       {
0571         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
0572         usart_frequency = PLL_Clocks.PLL_Q_Frequency;
0573       }
0574       break;
0575 
0576     case LL_RCC_USART16_CLKSOURCE_HSI:
0577     case LL_RCC_USART234578_CLKSOURCE_HSI:
0578       if (LL_RCC_HSI_IsReady() != 0U)
0579       {
0580         usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
0581       }
0582       break;
0583 
0584     case LL_RCC_USART16_CLKSOURCE_CSI:
0585     case LL_RCC_USART234578_CLKSOURCE_CSI:
0586       if (LL_RCC_CSI_IsReady() != 0U)
0587       {
0588         usart_frequency = CSI_VALUE;
0589       }
0590       break;
0591 
0592     case LL_RCC_USART16_CLKSOURCE_LSE:
0593     case LL_RCC_USART234578_CLKSOURCE_LSE:
0594       if (LL_RCC_LSE_IsReady() != 0U)
0595       {
0596         usart_frequency = LSE_VALUE;
0597       }
0598       break;
0599 
0600     default:
0601       /* Kernel clock disabled */
0602       break;
0603   }
0604 
0605   return usart_frequency;
0606 }
0607 
0608 /**
0609   * @brief  Return LPUART clock frequency
0610   * @param  LPUARTxSource This parameter can be one of the following values:
0611   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
0612   * @retval LPUART clock frequency (in Hz)
0613   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
0614   */
0615 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
0616 {
0617   uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
0618   LL_PLL_ClocksTypeDef PLL_Clocks;
0619 
0620   switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
0621   {
0622     case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
0623       lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
0624       break;
0625 
0626     case LL_RCC_LPUART1_CLKSOURCE_PLL2Q:
0627       if (LL_RCC_PLL2_IsReady() != 0U)
0628       {
0629         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
0630         lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
0631       }
0632       break;
0633 
0634     case LL_RCC_LPUART1_CLKSOURCE_PLL3Q:
0635       if (LL_RCC_PLL3_IsReady() != 0U)
0636       {
0637         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
0638         lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
0639       }
0640       break;
0641 
0642     case LL_RCC_LPUART1_CLKSOURCE_HSI:
0643       if (LL_RCC_HSI_IsReady() != 0U)
0644       {
0645         lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
0646       }
0647       break;
0648 
0649     case LL_RCC_LPUART1_CLKSOURCE_CSI:
0650       if (LL_RCC_CSI_IsReady() != 0U)
0651       {
0652         lpuart_frequency = CSI_VALUE;
0653       }
0654       break;
0655 
0656     case LL_RCC_LPUART1_CLKSOURCE_LSE:
0657       if (LL_RCC_LSE_IsReady() != 0U)
0658       {
0659         lpuart_frequency = LSE_VALUE;
0660       }
0661       break;
0662 
0663     default:
0664       /* Kernel clock disabled */
0665       break;
0666   }
0667 
0668   return lpuart_frequency;
0669 }
0670 
0671 /**
0672   * @brief  Return I2Cx clock frequency
0673   * @param  I2CxSource This parameter can be one of the following values:
0674   *         @arg @ref LL_RCC_I2C123_CLKSOURCE
0675   *         @arg @ref LL_RCC_I2C4_CLKSOURCE
0676   * @retval I2C clock frequency (in Hz)
0677   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
0678   */
0679 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
0680 {
0681   uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
0682   LL_PLL_ClocksTypeDef PLL_Clocks;
0683 
0684   /* Check parameter */
0685   assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
0686 
0687   switch (LL_RCC_GetI2CClockSource(I2CxSource))
0688   {
0689     case LL_RCC_I2C123_CLKSOURCE_PCLK1:
0690       i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
0691       break;
0692 
0693     case LL_RCC_I2C4_CLKSOURCE_PCLK4:
0694       i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
0695       break;
0696 
0697     case LL_RCC_I2C123_CLKSOURCE_PLL3R:
0698     case LL_RCC_I2C4_CLKSOURCE_PLL3R:
0699       if (LL_RCC_PLL3_IsReady() != 0U)
0700       {
0701         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
0702         i2c_frequency = PLL_Clocks.PLL_R_Frequency;
0703       }
0704       break;
0705 
0706     case LL_RCC_I2C123_CLKSOURCE_HSI:
0707     case LL_RCC_I2C4_CLKSOURCE_HSI:
0708       if (LL_RCC_HSI_IsReady() != 0U)
0709       {
0710         i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
0711       }
0712       break;
0713 
0714     case LL_RCC_I2C123_CLKSOURCE_CSI:
0715     case LL_RCC_I2C4_CLKSOURCE_CSI:
0716       if (LL_RCC_CSI_IsReady() != 0U)
0717       {
0718         i2c_frequency = CSI_VALUE;
0719       }
0720       break;
0721 
0722     default:
0723       /* Nothing to do */
0724       break;
0725   }
0726 
0727   return i2c_frequency;
0728 }
0729 
0730 /**
0731   * @brief  Return LPTIMx clock frequency
0732   * @param  LPTIMxSource This parameter can be one of the following values:
0733   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
0734   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
0735   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
0736   * @retval LPTIM clock frequency (in Hz)
0737   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
0738   */
0739 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
0740 {
0741   uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
0742   LL_PLL_ClocksTypeDef PLL_Clocks;
0743 
0744   /* Check parameter */
0745   assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
0746 
0747   switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
0748   {
0749     case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
0750       lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
0751       break;
0752 
0753     case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
0754     case LL_RCC_LPTIM345_CLKSOURCE_PCLK4:
0755       lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
0756       break;
0757 
0758     case LL_RCC_LPTIM1_CLKSOURCE_PLL2P:
0759     case LL_RCC_LPTIM2_CLKSOURCE_PLL2P:
0760     case LL_RCC_LPTIM345_CLKSOURCE_PLL2P:
0761       if (LL_RCC_PLL2_IsReady() != 0U)
0762       {
0763         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
0764         lptim_frequency = PLL_Clocks.PLL_P_Frequency;
0765       }
0766       break;
0767 
0768     case LL_RCC_LPTIM1_CLKSOURCE_PLL3R:
0769     case LL_RCC_LPTIM2_CLKSOURCE_PLL3R:
0770     case LL_RCC_LPTIM345_CLKSOURCE_PLL3R:
0771       if (LL_RCC_PLL3_IsReady() != 0U)
0772       {
0773         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
0774         lptim_frequency = PLL_Clocks.PLL_R_Frequency;
0775       }
0776       break;
0777 
0778     case LL_RCC_LPTIM1_CLKSOURCE_LSE:
0779     case LL_RCC_LPTIM2_CLKSOURCE_LSE:
0780     case LL_RCC_LPTIM345_CLKSOURCE_LSE:
0781       if (LL_RCC_LSE_IsReady() != 0U)
0782       {
0783         lptim_frequency = LSE_VALUE;
0784       }
0785       break;
0786 
0787     case LL_RCC_LPTIM1_CLKSOURCE_LSI:
0788     case LL_RCC_LPTIM2_CLKSOURCE_LSI:
0789     case LL_RCC_LPTIM345_CLKSOURCE_LSI:
0790       if (LL_RCC_LSI_IsReady() != 0U)
0791       {
0792         lptim_frequency = LSI_VALUE;
0793       }
0794       break;
0795 
0796     case LL_RCC_LPTIM1_CLKSOURCE_CLKP:
0797     case LL_RCC_LPTIM2_CLKSOURCE_CLKP:
0798     case LL_RCC_LPTIM345_CLKSOURCE_CLKP:
0799       lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
0800       break;
0801 
0802     default:
0803       /* Kernel clock disabled */
0804       break;
0805   }
0806 
0807   return lptim_frequency;
0808 }
0809 
0810 /**
0811   * @brief  Return SAIx clock frequency
0812   * @param  SAIxSource This parameter can be one of the following values:
0813   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
0814   *         @arg @ref LL_RCC_SAI23_CLKSOURCE (*)
0815   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
0816   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
0817   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
0818   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
0819   * @retval SAI clock frequency (in Hz)
0820   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
0821   *
0822   * (*) : Available on some STM32H7 lines only.
0823   */
0824 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
0825 {
0826   uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
0827   LL_PLL_ClocksTypeDef PLL_Clocks;
0828 
0829   /* Check parameter */
0830   assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
0831 
0832   switch (LL_RCC_GetSAIClockSource(SAIxSource))
0833   {
0834     case LL_RCC_SAI1_CLKSOURCE_PLL1Q:
0835 #if defined(SAI3)
0836     case LL_RCC_SAI23_CLKSOURCE_PLL1Q:
0837 #endif /* SAI3 */
0838 #if defined(SAI4)
0839     case LL_RCC_SAI4A_CLKSOURCE_PLL1Q:
0840     case LL_RCC_SAI4B_CLKSOURCE_PLL1Q:
0841 #endif /* SAI4 */
0842 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
0843     case LL_RCC_SAI2A_CLKSOURCE_PLL1Q:
0844     case LL_RCC_SAI2B_CLKSOURCE_PLL1Q:
0845 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
0846       if (LL_RCC_PLL1_IsReady() != 0U)
0847       {
0848         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
0849         sai_frequency = PLL_Clocks.PLL_Q_Frequency;
0850       }
0851       break;
0852 
0853     case LL_RCC_SAI1_CLKSOURCE_PLL2P:
0854 #if defined(SAI3)
0855     case LL_RCC_SAI23_CLKSOURCE_PLL2P:
0856 #endif /* SAI3 */
0857 #if defined(SAI4)
0858     case LL_RCC_SAI4A_CLKSOURCE_PLL2P:
0859     case LL_RCC_SAI4B_CLKSOURCE_PLL2P:
0860 #endif /* SAI4 */
0861 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
0862     case LL_RCC_SAI2A_CLKSOURCE_PLL2P:
0863     case LL_RCC_SAI2B_CLKSOURCE_PLL2P:
0864 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
0865       if (LL_RCC_PLL2_IsReady() != 0U)
0866       {
0867         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
0868         sai_frequency = PLL_Clocks.PLL_P_Frequency;
0869       }
0870       break;
0871 
0872     case LL_RCC_SAI1_CLKSOURCE_PLL3P:
0873 #if defined(SAI3)
0874     case LL_RCC_SAI23_CLKSOURCE_PLL3P:
0875 #endif /* SAI3 */
0876 #if defined(SAI4)
0877     case LL_RCC_SAI4A_CLKSOURCE_PLL3P:
0878     case LL_RCC_SAI4B_CLKSOURCE_PLL3P:
0879 #endif /* SAI4 */
0880 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
0881     case LL_RCC_SAI2A_CLKSOURCE_PLL3P:
0882     case LL_RCC_SAI2B_CLKSOURCE_PLL3P:
0883 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
0884       if (LL_RCC_PLL3_IsReady() != 0U)
0885       {
0886         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
0887         sai_frequency = PLL_Clocks.PLL_P_Frequency;
0888       }
0889       break;
0890 
0891     case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN:
0892 #if defined(SAI3)
0893     case LL_RCC_SAI23_CLKSOURCE_I2S_CKIN:
0894 #endif /* SAI3 */
0895 #if defined(SAI4)
0896     case LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN:
0897     case LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN:
0898 #endif /* SAI4 */
0899 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
0900     case LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN:
0901     case LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN:
0902 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
0903       sai_frequency = EXTERNAL_CLOCK_VALUE;
0904       break;
0905 
0906     case LL_RCC_SAI1_CLKSOURCE_CLKP:
0907 #if defined(SAI3)
0908     case LL_RCC_SAI23_CLKSOURCE_CLKP:
0909 #endif /* SAI3 */
0910 #if defined(SAI4)
0911     case LL_RCC_SAI4A_CLKSOURCE_CLKP:
0912     case LL_RCC_SAI4B_CLKSOURCE_CLKP:
0913 #endif /* SAI4 */
0914 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
0915     case LL_RCC_SAI2A_CLKSOURCE_CLKP:
0916     case LL_RCC_SAI2B_CLKSOURCE_CLKP:
0917 #endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
0918       sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
0919       break;
0920 
0921     default:
0922       /* Kernel clock disabled */
0923       break;
0924   }
0925 
0926   return sai_frequency;
0927 }
0928 
0929 /**
0930   * @brief  Return ADC clock frequency
0931   * @param  ADCxSource This parameter can be one of the following values:
0932   *         @arg @ref LL_RCC_ADC_CLKSOURCE
0933   * @retval ADC clock frequency (in Hz)
0934   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
0935   */
0936 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
0937 {
0938   uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
0939   LL_PLL_ClocksTypeDef PLL_Clocks;
0940 
0941   switch (LL_RCC_GetADCClockSource(ADCxSource))
0942   {
0943     case LL_RCC_ADC_CLKSOURCE_PLL2P:
0944       if (LL_RCC_PLL2_IsReady() != 0U)
0945       {
0946         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
0947         adc_frequency = PLL_Clocks.PLL_P_Frequency;
0948       }
0949       break;
0950 
0951     case LL_RCC_ADC_CLKSOURCE_PLL3R:
0952       if (LL_RCC_PLL3_IsReady() != 0U)
0953       {
0954         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
0955         adc_frequency = PLL_Clocks.PLL_R_Frequency;
0956       }
0957       break;
0958 
0959     case LL_RCC_ADC_CLKSOURCE_CLKP:
0960       adc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
0961       break;
0962 
0963     default:
0964       /* Kernel clock disabled */
0965       break;
0966   }
0967 
0968   return adc_frequency;
0969 }
0970 
0971 /**
0972   * @brief  Return SDMMC clock frequency
0973   * @param  SDMMCxSource This parameter can be one of the following values:
0974   *         @arg @ref LL_RCC_SDMMC_CLKSOURCE
0975   * @retval SDMMC clock frequency (in Hz)
0976   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
0977   */
0978 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
0979 {
0980   uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
0981   LL_PLL_ClocksTypeDef PLL_Clocks;
0982 
0983   switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
0984   {
0985     case LL_RCC_SDMMC_CLKSOURCE_PLL1Q:
0986       if (LL_RCC_PLL1_IsReady() != 0U)
0987       {
0988         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
0989         sdmmc_frequency = PLL_Clocks.PLL_Q_Frequency;
0990       }
0991       break;
0992 
0993     case LL_RCC_SDMMC_CLKSOURCE_PLL2R:
0994       if (LL_RCC_PLL2_IsReady() != 0U)
0995       {
0996         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
0997         sdmmc_frequency = PLL_Clocks.PLL_R_Frequency;
0998       }
0999       break;
1000 
1001     default:
1002       /* Nothing to do */
1003       break;
1004   }
1005 
1006   return sdmmc_frequency;
1007 }
1008 
1009 /**
1010   * @brief  Return RNG clock frequency
1011   * @param  RNGxSource This parameter can be one of the following values:
1012   *         @arg @ref LL_RCC_RNG_CLKSOURCE
1013   * @retval RNG clock frequency (in Hz)
1014   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1015   */
1016 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
1017 {
1018   uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1019   LL_PLL_ClocksTypeDef PLL_Clocks;
1020 
1021   switch (LL_RCC_GetRNGClockSource(RNGxSource))
1022   {
1023     case LL_RCC_RNG_CLKSOURCE_PLL1Q:
1024       if (LL_RCC_PLL1_IsReady() != 0U)
1025       {
1026         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1027         rng_frequency = PLL_Clocks.PLL_Q_Frequency;
1028       }
1029       break;
1030 
1031     case LL_RCC_RNG_CLKSOURCE_HSI48:
1032       if (LL_RCC_HSI48_IsReady() != 0U)
1033       {
1034         rng_frequency = 48000000U;
1035       }
1036       break;
1037 
1038     case LL_RCC_RNG_CLKSOURCE_LSE:
1039       if (LL_RCC_LSE_IsReady() != 0U)
1040       {
1041         rng_frequency = LSE_VALUE;
1042       }
1043       break;
1044 
1045     case LL_RCC_RNG_CLKSOURCE_LSI:
1046       if (LL_RCC_LSI_IsReady() != 0U)
1047       {
1048         rng_frequency = LSI_VALUE;
1049       }
1050       break;
1051 
1052     default:
1053       /* Nothing to do */
1054       break;
1055   }
1056 
1057   return rng_frequency;
1058 }
1059 
1060 /**
1061   * @brief  Return CEC clock frequency
1062   * @param  CECxSource This parameter can be one of the following values:
1063   *         @arg @ref LL_RCC_RNG_CLKSOURCE
1064   * @retval CEC clock frequency (in Hz)
1065   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1066   */
1067 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
1068 {
1069   uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1070 
1071   switch (LL_RCC_GetCECClockSource(CECxSource))
1072   {
1073     case LL_RCC_CEC_CLKSOURCE_LSE:
1074       if (LL_RCC_LSE_IsReady() != 0U)
1075       {
1076         cec_frequency = LSE_VALUE;
1077       }
1078       break;
1079 
1080     case LL_RCC_CEC_CLKSOURCE_LSI:
1081       if (LL_RCC_LSI_IsReady() != 0U)
1082       {
1083         cec_frequency = LSI_VALUE;
1084       }
1085       break;
1086 
1087     case LL_RCC_CEC_CLKSOURCE_CSI_DIV122:
1088       if (LL_RCC_CSI_IsReady() != 0U)
1089       {
1090         cec_frequency = CSI_VALUE / 122U;
1091       }
1092       break;
1093 
1094     default:
1095       /* Kernel clock disabled */
1096       break;
1097   }
1098 
1099   return cec_frequency;
1100 }
1101 
1102 /**
1103   * @brief  Return USB clock frequency
1104   * @param  USBxSource This parameter can be one of the following values:
1105   *         @arg @ref LL_RCC_USB_CLKSOURCE
1106   * @retval USB clock frequency (in Hz)
1107   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
1108   */
1109 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
1110 {
1111   uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1112   LL_PLL_ClocksTypeDef PLL_Clocks;
1113 
1114   switch (LL_RCC_GetUSBClockSource(USBxSource))
1115   {
1116     case LL_RCC_USB_CLKSOURCE_PLL1Q:
1117       if (LL_RCC_PLL1_IsReady() != 0U)
1118       {
1119         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1120         usb_frequency = PLL_Clocks.PLL_Q_Frequency;
1121       }
1122       break;
1123 
1124     case LL_RCC_USB_CLKSOURCE_PLL3Q:
1125       if (LL_RCC_PLL3_IsReady() != 0U)
1126       {
1127         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1128         usb_frequency = PLL_Clocks.PLL_Q_Frequency;
1129       }
1130       break;
1131 
1132     case LL_RCC_USB_CLKSOURCE_HSI48:
1133       if (LL_RCC_HSI48_IsReady() != 0U)
1134       {
1135         usb_frequency = HSI48_VALUE;
1136       }
1137       break;
1138 
1139     case LL_RCC_USB_CLKSOURCE_DISABLE:
1140     default:
1141       /* Nothing to do */
1142       break;
1143   }
1144 
1145   return usb_frequency;
1146 }
1147 
1148 /**
1149   * @brief  Return DFSDM clock frequency
1150   * @param  DFSDMxSource This parameter can be one of the following values:
1151   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
1152   * @retval DFSDM clock frequency (in Hz)
1153   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1154   */
1155 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
1156 {
1157   uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1158 
1159   switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
1160   {
1161     case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:
1162       dfsdm_frequency = RCC_GetSystemClockFreq();
1163       break;
1164 
1165     case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:
1166       dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
1167       break;
1168 
1169     default:
1170       /* Nothing to do */
1171       break;
1172   }
1173 
1174   return dfsdm_frequency;
1175 }
1176 
1177 #if defined(DFSDM2_BASE)
1178 /**
1179   * @brief  Return DFSDM clock frequency
1180   * @param  DFSDMxSource This parameter can be one of the following values:
1181   *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE
1182   * @retval DFSDM clock frequency (in Hz)
1183   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1184   */
1185 uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource)
1186 {
1187   uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1188 
1189 
1190   switch (LL_RCC_GetDFSDM2ClockSource(DFSDMxSource))
1191   {
1192 
1193     case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK:
1194       dfsdm_frequency = RCC_GetSystemClockFreq();
1195       break;
1196 
1197     case LL_RCC_DFSDM2_CLKSOURCE_PCLK4:
1198       dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
1199       break;
1200 
1201     default:
1202       /* Nothing to do */
1203       break;
1204   }
1205 
1206   return dfsdm_frequency;
1207 }
1208 #endif /* DFSDM2_BASE */
1209 
1210 #if defined(DSI)
1211 /**
1212   * @brief  Return DSI clock frequency
1213   * @param  DSIxSource This parameter can be one of the following values:
1214   *         @arg @ref LL_RCC_DSI_CLKSOURCE
1215   * @retval DSI clock frequency (in Hz)
1216   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1217   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1218   */
1219 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1220 {
1221   uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1222   LL_PLL_ClocksTypeDef PLL_Clocks;
1223 
1224   switch (LL_RCC_GetDSIClockSource(DSIxSource))
1225   {
1226     case LL_RCC_DSI_CLKSOURCE_PLL2Q:
1227       if (LL_RCC_PLL2_IsReady() != 0U)
1228       {
1229         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1230         dsi_frequency = PLL_Clocks.PLL_Q_Frequency;
1231       }
1232       break;
1233 
1234     case LL_RCC_DSI_CLKSOURCE_PHY:
1235       dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1236       break;
1237 
1238     default:
1239       /* Nothing to do */
1240       break;
1241   }
1242 
1243   return dsi_frequency;
1244 }
1245 #endif /* DSI */
1246 
1247 /**
1248   * @brief  Return SPDIF clock frequency
1249   * @param  SPDIFxSource This parameter can be one of the following values:
1250   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE
1251   * @retval SPDIF clock frequency (in Hz)
1252   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1253   */
1254 uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource)
1255 {
1256   uint32_t spdif_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1257   LL_PLL_ClocksTypeDef PLL_Clocks;
1258 
1259   switch (LL_RCC_GetSPDIFClockSource(SPDIFxSource))
1260   {
1261     case LL_RCC_SPDIF_CLKSOURCE_PLL1Q:
1262       if (LL_RCC_PLL1_IsReady() != 0U)
1263       {
1264         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1265         spdif_frequency = PLL_Clocks.PLL_Q_Frequency;
1266       }
1267       break;
1268 
1269     case LL_RCC_SPDIF_CLKSOURCE_PLL2R:
1270       if (LL_RCC_PLL2_IsReady() != 0U)
1271       {
1272         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1273         spdif_frequency = PLL_Clocks.PLL_R_Frequency;
1274       }
1275       break;
1276 
1277     case LL_RCC_SPDIF_CLKSOURCE_PLL3R:
1278       if (LL_RCC_PLL3_IsReady() != 0U)
1279       {
1280         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1281         spdif_frequency = PLL_Clocks.PLL_R_Frequency;
1282       }
1283       break;
1284 
1285     case LL_RCC_SPDIF_CLKSOURCE_HSI:
1286       if (LL_RCC_HSI_IsReady() != 0U)
1287       {
1288         spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1289       }
1290       break;
1291 
1292     default:
1293       /* Nothing to do */
1294       break;
1295   }
1296 
1297   return spdif_frequency;
1298 }
1299 
1300 /**
1301   * @brief  Return SPIx clock frequency
1302   * @param  SPIxSource This parameter can be one of the following values:
1303   *         @arg @ref LL_RCC_SPI123_CLKSOURCE
1304   *         @arg @ref LL_RCC_SPI45_CLKSOURCE
1305   *         @arg @ref LL_RCC_SPI6_CLKSOURCE
1306   * @retval SPI clock frequency (in Hz)
1307   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1308   */
1309 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
1310 {
1311   uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1312   LL_PLL_ClocksTypeDef PLL_Clocks;
1313 
1314   /* Check parameter */
1315   assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
1316 
1317   switch (LL_RCC_GetSPIClockSource(SPIxSource))
1318   {
1319     case LL_RCC_SPI123_CLKSOURCE_PLL1Q:
1320       if (LL_RCC_PLL1_IsReady() != 0U)
1321       {
1322         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1323         spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1324       }
1325       break;
1326 
1327     case LL_RCC_SPI123_CLKSOURCE_PLL2P:
1328       if (LL_RCC_PLL2_IsReady() != 0U)
1329       {
1330         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1331         spi_frequency = PLL_Clocks.PLL_P_Frequency;
1332       }
1333       break;
1334 
1335     case LL_RCC_SPI123_CLKSOURCE_PLL3P:
1336       if (LL_RCC_PLL3_IsReady() != 0U)
1337       {
1338         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1339         spi_frequency = PLL_Clocks.PLL_P_Frequency;
1340       }
1341       break;
1342 
1343     case LL_RCC_SPI123_CLKSOURCE_I2S_CKIN:
1344 #if defined(LL_RCC_SPI6_CLKSOURCE_I2S_CKIN)
1345     case LL_RCC_SPI6_CLKSOURCE_I2S_CKIN:
1346 #endif /* LL_RCC_SPI6_CLKSOURCE_I2S_CKIN */
1347       spi_frequency = EXTERNAL_CLOCK_VALUE;
1348       break;
1349 
1350     case LL_RCC_SPI123_CLKSOURCE_CLKP:
1351       spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1352       break;
1353 
1354     case LL_RCC_SPI45_CLKSOURCE_PCLK2:
1355       spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
1356       break;
1357 
1358     case LL_RCC_SPI6_CLKSOURCE_PCLK4:
1359       spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
1360       break;
1361 
1362     case LL_RCC_SPI45_CLKSOURCE_PLL2Q:
1363     case LL_RCC_SPI6_CLKSOURCE_PLL2Q:
1364       if (LL_RCC_PLL2_IsReady() != 0U)
1365       {
1366         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1367         spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1368       }
1369       break;
1370 
1371     case LL_RCC_SPI45_CLKSOURCE_PLL3Q:
1372     case LL_RCC_SPI6_CLKSOURCE_PLL3Q:
1373       if (LL_RCC_PLL3_IsReady() != 0U)
1374       {
1375         LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1376         spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1377       }
1378       break;
1379 
1380     case LL_RCC_SPI45_CLKSOURCE_HSI:
1381     case LL_RCC_SPI6_CLKSOURCE_HSI:
1382       if (LL_RCC_HSI_IsReady() != 0U)
1383       {
1384         spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1385       }
1386       break;
1387 
1388     case LL_RCC_SPI45_CLKSOURCE_CSI:
1389     case LL_RCC_SPI6_CLKSOURCE_CSI:
1390       if (LL_RCC_CSI_IsReady() != 0U)
1391       {
1392         spi_frequency = CSI_VALUE;
1393       }
1394       break;
1395 
1396     case LL_RCC_SPI45_CLKSOURCE_HSE:
1397     case LL_RCC_SPI6_CLKSOURCE_HSE:
1398       if (LL_RCC_HSE_IsReady() != 0U)
1399       {
1400         spi_frequency = HSE_VALUE;
1401       }
1402       break;
1403 
1404     default:
1405       /* Kernel clock disabled */
1406       break;
1407   }
1408 
1409   return spi_frequency;
1410 }
1411 
1412 /**
1413   * @brief  Return SWP clock frequency
1414   * @param  SWPxSource This parameter can be one of the following values:
1415   *         @arg @ref LL_RCC_SWP_CLKSOURCE
1416   * @retval SWP clock frequency (in Hz)
1417   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1418   */
1419 uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource)
1420 {
1421   uint32_t swp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1422 
1423   switch (LL_RCC_GetSWPClockSource(SWPxSource))
1424   {
1425     case LL_RCC_SWP_CLKSOURCE_PCLK1:
1426       swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
1427       break;
1428 
1429     case LL_RCC_SWP_CLKSOURCE_HSI:
1430       if (LL_RCC_HSI_IsReady() != 0U)
1431       {
1432         swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1433       }
1434       break;
1435 
1436     default:
1437       /* Nothing to do */
1438       break;
1439   }
1440 
1441   return swp_frequency;
1442 }
1443 
1444 /**
1445   * @brief  Return FDCAN clock frequency
1446   * @param  FDCANxSource This parameter can be one of the following values:
1447   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
1448   * @retval FDCAN clock frequency (in Hz)
1449   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1450   */
1451 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
1452 {
1453   uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1454   LL_PLL_ClocksTypeDef PLL_Clocks;
1455 
1456   switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
1457   {
1458     case LL_RCC_FDCAN_CLKSOURCE_HSE:
1459       if (LL_RCC_HSE_IsReady() != 0U)
1460       {
1461         fdcan_frequency = HSE_VALUE;
1462       }
1463       break;
1464 
1465     case LL_RCC_FDCAN_CLKSOURCE_PLL1Q:
1466       if (LL_RCC_PLL1_IsReady() != 0U)
1467       {
1468         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1469         fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
1470       }
1471       break;
1472 
1473     case LL_RCC_FDCAN_CLKSOURCE_PLL2Q:
1474       if (LL_RCC_PLL2_IsReady() != 0U)
1475       {
1476         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1477         fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
1478       }
1479       break;
1480 
1481     default:
1482       /* Kernel clock disabled */
1483       break;
1484   }
1485 
1486   return fdcan_frequency;
1487 }
1488 
1489 /**
1490   * @brief  Return FMC clock frequency
1491   * @param  FMCxSource This parameter can be one of the following values:
1492   *         @arg @ref LL_RCC_FMC_CLKSOURCE
1493   * @retval FMC clock frequency (in Hz)
1494   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1495   */
1496 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
1497 {
1498   uint32_t fmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1499   LL_PLL_ClocksTypeDef PLL_Clocks;
1500 
1501   switch (LL_RCC_GetFMCClockSource(FMCxSource))
1502   {
1503     case LL_RCC_FMC_CLKSOURCE_HCLK:
1504       fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
1505       break;
1506 
1507     case LL_RCC_FMC_CLKSOURCE_PLL1Q:
1508       if (LL_RCC_PLL1_IsReady() != 0U)
1509       {
1510         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1511         fmc_frequency = PLL_Clocks.PLL_Q_Frequency;
1512       }
1513       break;
1514 
1515     case LL_RCC_FMC_CLKSOURCE_PLL2R:
1516       if (LL_RCC_PLL2_IsReady() != 0U)
1517       {
1518         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1519         fmc_frequency = PLL_Clocks.PLL_R_Frequency;
1520       }
1521       break;
1522 
1523     case LL_RCC_FMC_CLKSOURCE_CLKP:
1524       fmc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1525       break;
1526 
1527     default:
1528       /* Nothing to do */
1529       break;
1530   }
1531 
1532   return fmc_frequency;
1533 }
1534 
1535 #if defined(QUADSPI)
1536 /**
1537   * @brief  Return QSPI clock frequency
1538   * @param  QSPIxSource This parameter can be one of the following values:
1539   *         @arg @ref LL_RCC_QSPI_CLKSOURCE
1540   * @retval QSPI clock frequency (in Hz)
1541   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1542   */
1543 uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)
1544 {
1545   uint32_t qspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1546   LL_PLL_ClocksTypeDef PLL_Clocks;
1547 
1548   switch (LL_RCC_GetQSPIClockSource(QSPIxSource))
1549   {
1550     case LL_RCC_QSPI_CLKSOURCE_HCLK:
1551       qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
1552       break;
1553 
1554     case LL_RCC_QSPI_CLKSOURCE_PLL1Q:
1555       if (LL_RCC_PLL1_IsReady() != 0U)
1556       {
1557         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1558         qspi_frequency = PLL_Clocks.PLL_Q_Frequency;
1559       }
1560       break;
1561 
1562     case LL_RCC_QSPI_CLKSOURCE_PLL2R:
1563       if (LL_RCC_PLL2_IsReady() != 0U)
1564       {
1565         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1566         qspi_frequency = PLL_Clocks.PLL_R_Frequency;
1567       }
1568       break;
1569 
1570     case LL_RCC_QSPI_CLKSOURCE_CLKP:
1571       qspi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1572       break;
1573 
1574     default:
1575       /* Nothing to do */
1576       break;
1577   }
1578 
1579   return qspi_frequency;
1580 }
1581 #endif /* QUADSPI */
1582 
1583 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1584 /**
1585   * @brief  Return OSPI clock frequency
1586   * @param  OSPIxSource This parameter can be one of the following values:
1587   *         @arg @ref LL_RCC_OSPI_CLKSOURCE
1588   * @retval OSPI clock frequency (in Hz)
1589   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1590   */
1591 
1592 uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource)
1593 {
1594   uint32_t ospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1595   LL_PLL_ClocksTypeDef PLL_Clocks;
1596 
1597   switch (LL_RCC_GetOSPIClockSource(OSPIxSource))
1598   {
1599     case LL_RCC_OSPI_CLKSOURCE_HCLK:
1600       ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
1601       break;
1602 
1603     case LL_RCC_OSPI_CLKSOURCE_PLL1Q:
1604       if (LL_RCC_PLL1_IsReady() != 0U)
1605       {
1606         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1607         ospi_frequency = PLL_Clocks.PLL_Q_Frequency;
1608       }
1609       break;
1610 
1611     case LL_RCC_OSPI_CLKSOURCE_PLL2R:
1612       if (LL_RCC_PLL2_IsReady() != 0U)
1613       {
1614         LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1615         ospi_frequency = PLL_Clocks.PLL_R_Frequency;
1616       }
1617       break;
1618 
1619     case LL_RCC_OSPI_CLKSOURCE_CLKP:
1620       ospi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1621       break;
1622 
1623     default:
1624       /* Nothing to do */
1625       break;
1626   }
1627 
1628   return ospi_frequency;
1629 }
1630 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
1631 
1632 /**
1633   * @brief  Return CLKP clock frequency
1634   * @param  CLKPxSource This parameter can be one of the following values:
1635   *         @arg @ref LL_RCC_CLKP_CLKSOURCE
1636   * @retval CLKP clock frequency (in Hz)
1637   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1638   */
1639 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
1640 {
1641   uint32_t clkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1642 
1643   switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
1644   {
1645     case LL_RCC_CLKP_CLKSOURCE_HSI:
1646       if (LL_RCC_HSI_IsReady() != 0U)
1647       {
1648         clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1649       }
1650       break;
1651 
1652     case LL_RCC_CLKP_CLKSOURCE_CSI:
1653       if (LL_RCC_CSI_IsReady() != 0U)
1654       {
1655         clkp_frequency = CSI_VALUE;
1656       }
1657       break;
1658 
1659     case LL_RCC_CLKP_CLKSOURCE_HSE:
1660       if (LL_RCC_HSE_IsReady() != 0U)
1661       {
1662         clkp_frequency = HSE_VALUE;
1663       }
1664       break;
1665 
1666     default:
1667       /* CLKP clock disabled */
1668       break;
1669   }
1670 
1671   return clkp_frequency;
1672 }
1673 
1674 /**
1675   * @}
1676   */
1677 
1678 /**
1679   * @}
1680   */
1681 
1682 /** @addtogroup RCC_LL_Private_Functions
1683   * @{
1684   */
1685 
1686 /**
1687   * @brief  Return SYSTEM clock frequency
1688   * @retval SYSTEM clock frequency (in Hz)
1689   */
1690 static uint32_t RCC_GetSystemClockFreq(void)
1691 {
1692   uint32_t frequency = 0U;
1693   LL_PLL_ClocksTypeDef PLL_Clocks;
1694 
1695   /* Get SYSCLK source -------------------------------------------------------*/
1696   switch (LL_RCC_GetSysClkSource())
1697   {
1698     /* No check on Ready: Won't be selected by hardware if not */
1699     case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
1700       frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
1701       break;
1702 
1703     case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
1704       frequency = CSI_VALUE;
1705       break;
1706 
1707     case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
1708       frequency = HSE_VALUE;
1709       break;
1710 
1711     case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
1712       LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1713       frequency = PLL_Clocks.PLL_P_Frequency;
1714       break;
1715 
1716     default:
1717       /* Nothing to do */
1718       break;
1719   }
1720 
1721   return frequency;
1722 }
1723 
1724 /**
1725   * @brief  Return HCLK clock frequency
1726   * @param  SYSCLK_Frequency SYSCLK clock frequency
1727   * @retval HCLK clock frequency (in Hz)
1728   */
1729 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1730 {
1731   /* HCLK clock frequency */
1732   return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1733 }
1734 
1735 /**
1736   * @brief  Return PCLK1 clock frequency
1737   * @param  HCLK_Frequency HCLK clock frequency
1738   * @retval PCLK1 clock frequency (in Hz)
1739   */
1740 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1741 {
1742   /* PCLK1 clock frequency */
1743   return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1744 }
1745 
1746 /**
1747   * @brief  Return PCLK2 clock frequency
1748   * @param  HCLK_Frequency HCLK clock frequency
1749   * @retval PCLK2 clock frequency (in Hz)
1750   */
1751 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1752 {
1753   /* PCLK2 clock frequency */
1754   return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1755 }
1756 
1757 /**
1758   * @brief  Return PCLK3 clock frequency
1759   * @param  HCLK_Frequency HCLK clock frequency
1760   * @retval PCLK3 clock frequency (in Hz)
1761   */
1762 static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
1763 {
1764   /* PCLK3 clock frequency */
1765   return LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
1766 }
1767 
1768 /**
1769   * @brief  Return PCLK4 clock frequency
1770   * @param  HCLK_Frequency HCLK clock frequency
1771   * @retval PCLK4 clock frequency (in Hz)
1772   */
1773 static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
1774 {
1775   /* PCLK4 clock frequency */
1776   return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
1777 }
1778 
1779 /**
1780   * @}
1781   */
1782 
1783 /**
1784   * @}
1785   */
1786 
1787 #endif /* defined(RCC) */
1788 
1789 /**
1790   * @}
1791   */
1792 
1793 #endif /* USE_FULL_LL_DRIVER */
1794
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