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0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_ll_mdma.c
0004   * @author  MCD Application Team
0005   * @brief   MDMA LL module driver.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
0019 
0020 /* Includes ------------------------------------------------------------------*/
0021 #include "stm32h7xx_ll_mdma.h"
0022 #include "stm32h7xx_ll_bus.h"
0023 #ifdef  USE_FULL_ASSERT
0024 #include "stm32_assert.h"
0025 #else
0026 #define assert_param(expr) ((void)0U)
0027 #endif
0028 
0029 /** @addtogroup STM32H7xx_LL_Driver
0030   * @{
0031   */
0032 
0033 #if defined (MDMA)
0034 
0035 /** @defgroup MDMA_LL MDMA
0036   * @ingroup RTEMSBSPsARMSTM32H7
0037   * @{
0038   */
0039 
0040 /* Private types -------------------------------------------------------------*/
0041 /* Private variables ---------------------------------------------------------*/
0042 /* Private constants ---------------------------------------------------------*/
0043 /* Private macros ------------------------------------------------------------*/
0044 /** @addtogroup MDMA_LL_Private_Macros
0045   * @{
0046   */
0047 
0048 #define IS_LL_MDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) (((INSTANCE) == MDMA) && \
0049                                                             (((CHANNEL) == LL_MDMA_CHANNEL_0) || \
0050                                                              ((CHANNEL) == LL_MDMA_CHANNEL_1) || \
0051                                                              ((CHANNEL) == LL_MDMA_CHANNEL_2) || \
0052                                                              ((CHANNEL) == LL_MDMA_CHANNEL_3) || \
0053                                                              ((CHANNEL) == LL_MDMA_CHANNEL_4) || \
0054                                                              ((CHANNEL) == LL_MDMA_CHANNEL_5) || \
0055                                                              ((CHANNEL) == LL_MDMA_CHANNEL_6) || \
0056                                                              ((CHANNEL) == LL_MDMA_CHANNEL_7) || \
0057                                                              ((CHANNEL) == LL_MDMA_CHANNEL_8) || \
0058                                                              ((CHANNEL) == LL_MDMA_CHANNEL_9) || \
0059                                                              ((CHANNEL) == LL_MDMA_CHANNEL_10)|| \
0060                                                              ((CHANNEL) == LL_MDMA_CHANNEL_11)|| \
0061                                                              ((CHANNEL) == LL_MDMA_CHANNEL_12)|| \
0062                                                              ((CHANNEL) == LL_MDMA_CHANNEL_13)|| \
0063                                                              ((CHANNEL) == LL_MDMA_CHANNEL_14)|| \
0064                                                              ((CHANNEL) == LL_MDMA_CHANNEL_15)|| \
0065                                                              ((CHANNEL) == LL_MDMA_CHANNEL_ALL)))
0066 
0067 #define IS_LL_MDMA_BLK_DATALENGTH(__VALUE__)              ((__VALUE__)  <= 0x00010000U)
0068 
0069 #define IS_LL_MDMA_BLK_REPEATCOUNT(__VALUE__)             ((__VALUE__)  <= 0x00000FFFU)
0070 
0071 #define IS_LL_MDMA_WORDENDIANESS(__VALUE__)               (((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_PRESERVE) || \
0072                                                            ((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_EXCHANGE))
0073 
0074 #define IS_LL_MDMA_HALFWORDENDIANESS(__VALUE__)           (((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE) || \
0075                                                            ((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE))
0076 
0077 #define IS_LL_MDMA_BYTEENDIANESS(__VALUE__)               (((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_PRESERVE) || \
0078                                                            ((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_EXCHANGE))
0079 
0080 #define IS_LL_MDMA_PRIORITY(__VALUE__)                    (((__VALUE__) == LL_MDMA_PRIORITY_LOW)    || \
0081                                                            ((__VALUE__) == LL_MDMA_PRIORITY_MEDIUM) || \
0082                                                            ((__VALUE__) == LL_MDMA_PRIORITY_HIGH)   || \
0083                                                            ((__VALUE__) == LL_MDMA_PRIORITY_VERYHIGH))
0084 
0085 #define IS_LL_MDMA_BUFFWRITEMODE(__VALUE__)               (((__VALUE__) == LL_MDMA_BUFF_WRITE_DISABLE) || \
0086                                                            ((__VALUE__) == LL_MDMA_BUFF_WRITE_ENABLE))
0087 
0088 #define IS_LL_MDMA_REQUESTMODE(__VALUE__)                 (((__VALUE__) == LL_MDMA_REQUEST_MODE_HW) || \
0089                                                            ((__VALUE__) == LL_MDMA_REQUEST_MODE_SW))
0090 
0091 #define IS_LL_MDMA_TRIGGERMODE(__VALUE__)                 (((__VALUE__) == LL_MDMA_BUFFER_TRANSFER)       || \
0092                                                            ((__VALUE__) == LL_MDMA_BLOCK_TRANSFER)        || \
0093                                                            ((__VALUE__) == LL_MDMA_REPEAT_BLOCK_TRANSFER) || \
0094                                                            ((__VALUE__) == LL_MDMA_FULL_TRANSFER))
0095 
0096 #define IS_LL_MDMA_PADDINGALIGNEMENT(__VALUE__)           (((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT)        || \
0097                                                            ((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT_SIGNED) || \
0098                                                            ((__VALUE__) == LL_MDMA_DATAALIGN_LEFT))
0099 
0100 #define IS_LL_MDMA_PACKMODE(__VALUE__)                    (((__VALUE__) == LL_MDMA_PACK_DISABLE) || \
0101                                                            ((__VALUE__) == LL_MDMA_PACK_ENABLE))
0102 
0103 #define IS_LL_MDMA_BUFFER_XFERLENGTH(__VALUE__)           ((__VALUE__)  <= 0x0000007FU)
0104 
0105 #define IS_LL_MDMA_DESTBURST(__VALUE__)                   (((__VALUE__) == LL_MDMA_DEST_BURST_SINGLE) || \
0106                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_2BEATS) || \
0107                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_4BEATS) || \
0108                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_8BEATS) || \
0109                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_16BEATS)|| \
0110                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_32BEATS)|| \
0111                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_64BEATS)|| \
0112                                                            ((__VALUE__) == LL_MDMA_DEST_BURST_128BEATS))
0113 
0114 #define IS_LL_MDMA_SRCTBURST(__VALUE__)                   (((__VALUE__) == LL_MDMA_SRC_BURST_SINGLE) || \
0115                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_2BEATS) || \
0116                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_4BEATS) || \
0117                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_8BEATS) || \
0118                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_16BEATS)|| \
0119                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_32BEATS)|| \
0120                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_64BEATS)|| \
0121                                                            ((__VALUE__) == LL_MDMA_SRC_BURST_128BEATS))
0122 
0123 #define IS_LL_MDMA_DESTINCSIZE(__VALUE__)                 (((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_BYTE) || \
0124                                                            ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_HALFWORD) || \
0125                                                            ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_WORD) || \
0126                                                            ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD))
0127 
0128 #define IS_LL_MDMA_SRCINCSIZE(__VALUE__)                  (((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_BYTE)     || \
0129                                                            ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_HALFWORD) || \
0130                                                            ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_WORD)     || \
0131                                                            ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD))
0132 
0133 #define IS_LL_MDMA_DESTDATASIZE(__VALUE__)                (((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_BYTE) || \
0134                                                            ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_HALFWORD) || \
0135                                                            ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_WORD) || \
0136                                                            ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD))
0137 
0138 #define IS_LL_MDMA_SRCDATASIZE(__VALUE__)                 (((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_BYTE) || \
0139                                                            ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_HALFWORD) || \
0140                                                            ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_WORD) || \
0141                                                            ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD))
0142 
0143 #define IS_LL_MDMA_DESTINCMODE(__VALUE__)                 (((__VALUE__) == LL_MDMA_DEST_FIXED) || \
0144                                                            ((__VALUE__) == LL_MDMA_DEST_INCREMENT) || \
0145                                                            ((__VALUE__) == LL_MDMA_DEST_DECREMENT))
0146 
0147 #define IS_LL_MDMA_SRCINCMODE(__VALUE__)                  (((__VALUE__) == LL_MDMA_SRC_FIXED) || \
0148                                                            ((__VALUE__) == LL_MDMA_SRC_INCREMENT) || \
0149                                                            ((__VALUE__) == LL_MDMA_SRC_DECREMENT))
0150 
0151 #define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(__VALUE__)  (((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT) || \
0152                                                            ((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT))
0153 
0154 
0155 #define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(__VALUE__)   (((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT) || \
0156                                                            ((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT))
0157 
0158 #define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(__VALUE__)   ((__VALUE__)  <= 0x0000FFFFU)
0159 
0160 #define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(__VALUE__)    ((__VALUE__)  <= 0x0000FFFFU)
0161 
0162 #define IS_LL_MDMA_DEST_BUS(__VALUE__)                    (((__VALUE__) == LL_MDMA_DEST_BUS_SYSTEM_AXI) || \
0163                                                            ((__VALUE__) == LL_MDMA_DEST_BUS_AHB_TCM))
0164 
0165 #define IS_LL_MDMA_SRC_BUS(__VALUE__)                     (((__VALUE__) == LL_MDMA_SRC_BUS_SYSTEM_AXI) || \
0166                                                            ((__VALUE__) == LL_MDMA_SRC_BUS_AHB_TCM))
0167 #if defined (QUADSPI) && defined (JPEG) && defined (DSI) /* STM32H747/57 devices */
0168 #define IS_LL_MDMA_HWTRIGGER(__VALUE__)                   (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC)      || \
0169                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC)      || \
0170                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC)      || \
0171                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC)      || \
0172                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC)      || \
0173                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC)      || \
0174                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC)      || \
0175                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC)      || \
0176                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC)      || \
0177                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC)      || \
0178                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC)      || \
0179                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC)      || \
0180                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC)      || \
0181                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC)      || \
0182                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC)      || \
0183                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC)      || \
0184                                                            ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT)         || \
0185                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH)       || \
0186                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF)       || \
0187                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH)      || \
0188                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE)      || \
0189                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION)  || \
0190                                                            ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH)      || \
0191                                                            ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC)           || \
0192                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC)        || \
0193                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC)             || \
0194                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW)             || \
0195                                                            ((__VALUE__) == LL_MDMA_REQ_DSI_TEARING_EFFECT)   || \
0196                                                            ((__VALUE__) == LL_MDMA_REQ_DSI_END_REFRESH)      || \
0197                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA)      || \
0198                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
0199                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
0200 #elif defined (QUADSPI) && defined (JPEG) /* STM32H743/53/45/55 devices */
0201 #define IS_LL_MDMA_HWTRIGGER(__VALUE__)                   (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC)      || \
0202                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC)      || \
0203                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC)      || \
0204                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC)      || \
0205                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC)      || \
0206                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC)      || \
0207                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC)      || \
0208                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC)      || \
0209                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC)      || \
0210                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC)      || \
0211                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC)      || \
0212                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC)      || \
0213                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC)      || \
0214                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC)      || \
0215                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC)      || \
0216                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC)      || \
0217                                                            ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT)         || \
0218                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH)       || \
0219                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF)       || \
0220                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH)      || \
0221                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE)      || \
0222                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION)  || \
0223                                                            ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH)      || \
0224                                                            ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC)           || \
0225                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC)        || \
0226                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC)             || \
0227                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW)             || \
0228                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA)      || \
0229                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
0230                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
0231 #elif defined (QUADSPI) /* STM32H742 devices */
0232 #define IS_LL_MDMA_HWTRIGGER(__VALUE__)                   (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC)      || \
0233                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC)      || \
0234                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC)      || \
0235                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC)      || \
0236                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC)      || \
0237                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC)      || \
0238                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC)      || \
0239                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC)      || \
0240                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC)      || \
0241                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC)      || \
0242                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC)      || \
0243                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC)      || \
0244                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC)      || \
0245                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC)      || \
0246                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC)      || \
0247                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC)      || \
0248                                                            ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH)      || \
0249                                                            ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC)           || \
0250                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC)        || \
0251                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC)             || \
0252                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW)             || \
0253                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA)      || \
0254                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
0255                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
0256 
0257 #elif defined (OCTOSPI1) && defined (JPEG) /* STM32H7A3/B3 devices */
0258 #define IS_LL_MDMA_HWTRIGGER(__VALUE__)                   (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC)      || \
0259                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC)      || \
0260                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC)      || \
0261                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC)      || \
0262                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC)      || \
0263                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC)      || \
0264                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC)      || \
0265                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC)      || \
0266                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC)      || \
0267                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC)      || \
0268                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC)      || \
0269                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC)      || \
0270                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC)      || \
0271                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC)      || \
0272                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC)      || \
0273                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC)      || \
0274                                                            ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT)         || \
0275                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH)       || \
0276                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF)       || \
0277                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH)      || \
0278                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE)      || \
0279                                                            ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION)  || \
0280                                                            ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_FIFO_TH)     || \
0281                                                            ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_TC)          || \
0282                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC)        || \
0283                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC)             || \
0284                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW)             || \
0285                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA)      || \
0286                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
0287                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END)   || \
0288                                                            ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_FIFO_TH)     || \
0289                                                            ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_TC))
0290 #else /* STM32H723/25/33/35 devices */
0291 #define IS_LL_MDMA_HWTRIGGER(__VALUE__)                   (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC)      || \
0292                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC)      || \
0293                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC)      || \
0294                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC)      || \
0295                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC)      || \
0296                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC)      || \
0297                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC)      || \
0298                                                            ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC)      || \
0299                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC)      || \
0300                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC)      || \
0301                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC)      || \
0302                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC)      || \
0303                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC)      || \
0304                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC)      || \
0305                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC)      || \
0306                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC)      || \
0307                                                            ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT)         || \
0308                                                            ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_FIFO_TH)     || \
0309                                                            ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_TC)          || \
0310                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC)        || \
0311                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC)             || \
0312                                                            ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW)             || \
0313                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA)      || \
0314                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
0315                                                            ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END)   || \
0316                                                            ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_FIFO_TH)     || \
0317                                                            ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_TC))
0318 #endif /* QUADSPI && JPEG && DSI */
0319 /**
0320   * @}
0321   */
0322 
0323 /* Private function prototypes -----------------------------------------------*/
0324 
0325 /* Exported functions --------------------------------------------------------*/
0326 /** @addtogroup MDMA_LL_Exported_Functions
0327   * @{
0328   */
0329 
0330 /** @addtogroup MDMA_LL_EF_Init
0331   * @{
0332   */
0333 
0334 /**
0335   * @brief  De-initialize the MDMA registers to their default reset values.
0336   * @param  MDMAx MDMAx Instance
0337   * @param  Channel This parameter can be one of the following values:
0338   *         @arg @ref LL_MDMA_CHANNEL_0
0339   *         @arg @ref LL_MDMA_CHANNEL_1
0340   *         @arg @ref LL_MDMA_CHANNEL_2
0341   *         @arg @ref LL_MDMA_CHANNEL_3
0342   *         @arg @ref LL_MDMA_CHANNEL_4
0343   *         @arg @ref LL_MDMA_CHANNEL_5
0344   *         @arg @ref LL_MDMA_CHANNEL_6
0345   *         @arg @ref LL_MDMA_CHANNEL_7
0346   *         @arg @ref LL_MDMA_CHANNEL_8
0347   *         @arg @ref LL_MDMA_CHANNEL_9
0348   *         @arg @ref LL_MDMA_CHANNEL_10
0349   *         @arg @ref LL_MDMA_CHANNEL_11
0350   *         @arg @ref LL_MDMA_CHANNEL_12
0351   *         @arg @ref LL_MDMA_CHANNEL_13
0352   *         @arg @ref LL_MDMA_CHANNEL_14
0353   *         @arg @ref LL_MDMA_CHANNEL_15
0354   *         @arg @ref LL_MDMA_CHANNEL_ALL
0355   * @retval An ErrorStatus enumeration value:
0356   *          - SUCCESS: MDMA registers are de-initialized
0357   *          - ERROR: Not applicable
0358   */
0359 uint32_t LL_MDMA_DeInit(MDMA_TypeDef *MDMAx, uint32_t Channel)
0360 {
0361   MDMA_Channel_TypeDef *tmp;
0362   ErrorStatus status = SUCCESS;
0363 
0364   /* Check the MDMA Instance MDMAx and Channel parameters*/
0365   assert_param(IS_LL_MDMA_ALL_CHANNEL_INSTANCE(MDMAx, Channel));
0366 
0367   if (Channel == LL_MDMA_CHANNEL_ALL)
0368   {
0369     LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_MDMA);
0370     LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_MDMA);
0371   }
0372   else
0373   {
0374     /* Disable the selected Channel */
0375     LL_MDMA_DisableChannel(MDMAx,Channel);
0376 
0377     /* Get the MDMA Channel Instance */
0378     tmp = (MDMA_Channel_TypeDef *)(LL_MDMA_GET_CHANNEL_INSTANCE(MDMAx, Channel));
0379 
0380     /* Reset MDMAx_Channely control register */
0381     LL_MDMA_WriteReg(tmp, CCR, 0U);
0382 
0383     /* Reset MDMAx_Channely Configuration register */
0384     LL_MDMA_WriteReg(tmp, CTCR, 0U);
0385 
0386     /* Reset MDMAx_Channely block number of data register */
0387     LL_MDMA_WriteReg(tmp, CBNDTR, 0U);
0388 
0389     /* Reset MDMAx_Channely source address register */
0390     LL_MDMA_WriteReg(tmp, CSAR, 0U);
0391 
0392     /* Reset MDMAx_Channely destination address register */
0393     LL_MDMA_WriteReg(tmp, CDAR, 0U);
0394 
0395     /* Reset MDMAx_Channely Block Repeat address Update register */
0396     LL_MDMA_WriteReg(tmp, CBRUR, 0U);
0397 
0398     /* Reset MDMAx_Channely Link Address register */
0399     LL_MDMA_WriteReg(tmp, CLAR, 0U);
0400 
0401     /* Reset MDMAx_Channely Trigger and Bus selection register */
0402     LL_MDMA_WriteReg(tmp, CTBR, 0U);
0403 
0404     /* Reset MDMAx_Channely Mask address register */
0405     LL_MDMA_WriteReg(tmp, CMAR, 0U);
0406 
0407     /* Reset MDMAx_Channely Mask Data register */
0408     LL_MDMA_WriteReg(tmp, CMDR, 0U);
0409 
0410     /* Reset the Channel pending flags */
0411     LL_MDMA_WriteReg(tmp, CIFCR, 0x0000001FU);
0412   }
0413 
0414   return (uint32_t)status;
0415 }
0416 
0417 /**
0418   * @brief  Initialize the MDMA registers according to the specified parameters in MDMA_InitStruct.
0419   * @note   To convert MDMAx_Channely Instance to MDMAx Instance and Channely, use helper macros :
0420   *         @arg @ref LL_MDMA_GET_INSTANCE
0421   *         @arg @ref LL_MDMA_GET_CHANNEL
0422   * @param  MDMAx MDMAx Instance
0423   * @param  Channel This parameter can be one of the following values:
0424   *         @arg @ref LL_MDMA_CHANNEL_0
0425   *         @arg @ref LL_MDMA_CHANNEL_1
0426   *         @arg @ref LL_MDMA_CHANNEL_2
0427   *         @arg @ref LL_MDMA_CHANNEL_3
0428   *         @arg @ref LL_MDMA_CHANNEL_4
0429   *         @arg @ref LL_MDMA_CHANNEL_5
0430   *         @arg @ref LL_MDMA_CHANNEL_6
0431   *         @arg @ref LL_MDMA_CHANNEL_7
0432   *         @arg @ref LL_MDMA_CHANNEL_8
0433   *         @arg @ref LL_MDMA_CHANNEL_9
0434   *         @arg @ref LL_MDMA_CHANNEL_10
0435   *         @arg @ref LL_MDMA_CHANNEL_11
0436   *         @arg @ref LL_MDMA_CHANNEL_12
0437   *         @arg @ref LL_MDMA_CHANNEL_13
0438   *         @arg @ref LL_MDMA_CHANNEL_14
0439   *         @arg @ref LL_MDMA_CHANNEL_15
0440   * @param  MDMA_InitStruct pointer to a @ref LL_MDMA_InitTypeDef structure.
0441   * @retval An ErrorStatus enumeration value:
0442   *          - SUCCESS: MDMA registers are initialized
0443   *          - ERROR: Not applicable
0444   */
0445 uint32_t LL_MDMA_Init(MDMA_TypeDef *MDMAx, uint32_t Channel, LL_MDMA_InitTypeDef *MDMA_InitStruct)
0446 {
0447   /* Check the MDMA Instance MDMAx and Channel parameters*/
0448   assert_param(IS_LL_MDMA_ALL_CHANNEL_INSTANCE(MDMAx, Channel));
0449 
0450   /* Check the MDMA parameters from MDMA_InitStruct */
0451   assert_param(IS_LL_MDMA_BLK_DATALENGTH(MDMA_InitStruct->BlockDataLength));
0452   assert_param(IS_LL_MDMA_BLK_REPEATCOUNT(MDMA_InitStruct->BlockRepeatCount));
0453   assert_param(IS_LL_MDMA_WORDENDIANESS(MDMA_InitStruct->WordEndianess));
0454   assert_param(IS_LL_MDMA_HALFWORDENDIANESS(MDMA_InitStruct->HalfWordEndianess));
0455   assert_param(IS_LL_MDMA_BYTEENDIANESS(MDMA_InitStruct->ByteEndianess));
0456   assert_param(IS_LL_MDMA_PRIORITY(MDMA_InitStruct->Priority));
0457   assert_param(IS_LL_MDMA_BUFFWRITEMODE(MDMA_InitStruct->BufferableWriteMode));
0458   assert_param(IS_LL_MDMA_REQUESTMODE(MDMA_InitStruct->RequestMode));
0459   assert_param(IS_LL_MDMA_TRIGGERMODE(MDMA_InitStruct->TriggerMode));
0460   assert_param(IS_LL_MDMA_PADDINGALIGNEMENT(MDMA_InitStruct->PaddingAlignment));
0461   assert_param(IS_LL_MDMA_PACKMODE(MDMA_InitStruct->PackMode));
0462   assert_param(IS_LL_MDMA_BUFFER_XFERLENGTH(MDMA_InitStruct->BufferTransferLength));
0463   assert_param(IS_LL_MDMA_DESTBURST(MDMA_InitStruct->DestBurst));
0464   assert_param(IS_LL_MDMA_SRCTBURST(MDMA_InitStruct->SrctBurst));
0465   assert_param(IS_LL_MDMA_DESTINCSIZE(MDMA_InitStruct->DestIncSize));
0466   assert_param(IS_LL_MDMA_SRCINCSIZE(MDMA_InitStruct->SrcIncSize));
0467   assert_param(IS_LL_MDMA_DESTDATASIZE(MDMA_InitStruct->DestDataSize));
0468   assert_param(IS_LL_MDMA_SRCDATASIZE(MDMA_InitStruct->SrcDataSize));
0469   assert_param(IS_LL_MDMA_DESTINCMODE(MDMA_InitStruct->DestIncMode));
0470   assert_param(IS_LL_MDMA_SRCINCMODE(MDMA_InitStruct->SrcIncMode));
0471   assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatDestAddrUpdateMode));
0472   assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode));
0473   assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatDestAddrUpdateVal));
0474   assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal));
0475   assert_param(IS_LL_MDMA_DEST_BUS(MDMA_InitStruct->DestBus));
0476   assert_param(IS_LL_MDMA_SRC_BUS(MDMA_InitStruct->SrcBus));
0477   assert_param(IS_LL_MDMA_HWTRIGGER(MDMA_InitStruct->HWTrigger));
0478 
0479 
0480   /*-------------------------- MDMAx CCR Configuration --------------------------
0481    * Configure the Transfer endianness na priority with parameter :
0482    * - WordEndianess:     MDMA_CCR_WEX[14] bit
0483    * - HalfWordEndianess: MDMA_CCR_HEX[13] bit
0484    * - WordEndianess:     MDMA_CCR_BEX[12] bit
0485    * - Priority:          MDMA_CCR_BEX[7:6] bits
0486    */
0487   LL_MDMA_ConfigXferEndianness(MDMAx, Channel, MDMA_InitStruct->WordEndianess     | \
0488                                                MDMA_InitStruct->HalfWordEndianess | \
0489                                                MDMA_InitStruct->ByteEndianess);
0490 
0491   LL_MDMA_SetChannelPriorityLevel(MDMAx, Channel, MDMA_InitStruct->Priority);
0492 
0493   /*-------------------------- MDMAx CTCR Configuration --------------------------
0494    * Configure the Transfer  parameter :
0495    * - BufferableWriteMode:     MDMA_CTCR_BWM[31] bit
0496    * - RequestMode:             MDMA_CTCR_SWRM[30] bit
0497    * - TriggerMode:             MDMA_CTCR_TRGM[29:28] bits
0498    * - PaddingAlignment:       MDMA_CTCR_PAM[27:26] bits
0499    * - PackMode:                MDMA_CTCR_PKE[25] bit
0500    * - BufferTransferLength:    MDMA_CTCR_TLEN[24:18] bits
0501    * - DestBurst:               MDMA_CTCR_DBURST[17:15] bits
0502    * - SrctBurst:               MDMA_CTCR_SBURST[14:12] bits
0503    * - DestIncSize:             MDMA_CTCR_DINCOS[11:10] bits
0504    * - SrcIncSize:              MDMA_CTCR_SINCOS[9:8] bits
0505    * - DestDataSize:            MDMA_CTCR_DSIZE[7:6] bits
0506    * - SrcDataSize:             MDMA_CTCR_SSIZE[5:4] bits
0507    * - DestIncMode:             MDMA_CTCR_DINC[3:2] bits
0508    * - SrcIncMode:              MDMA_CTCR_SINC[1:0] bits
0509    */
0510   LL_MDMA_ConfigTransfer(MDMAx, Channel, MDMA_InitStruct->BufferableWriteMode | \
0511                                          MDMA_InitStruct->RequestMode         | \
0512                                          MDMA_InitStruct->TriggerMode         | \
0513                                          MDMA_InitStruct->PaddingAlignment    | \
0514                                          MDMA_InitStruct->PackMode            | \
0515                                          MDMA_InitStruct->DestBurst           | \
0516                                          MDMA_InitStruct->SrctBurst           | \
0517                                          MDMA_InitStruct->DestIncSize         | \
0518                                          MDMA_InitStruct->SrcIncSize          | \
0519                                          MDMA_InitStruct->DestDataSize        | \
0520                                          MDMA_InitStruct->SrcDataSize         | \
0521                                          MDMA_InitStruct->DestIncMode         | \
0522                                          MDMA_InitStruct->SrcIncMode, MDMA_InitStruct->BufferTransferLength);
0523 
0524   /*-------------------------- MDMAx CBNDTR Configuration --------------------------
0525    * Configure the Transfer Block counters and update mode with parameter :
0526    * - BlockRepeatCount:                MDMA_CBNDTR_BRC[31:20] bits
0527    * - BlockDataLength:                 MDMA_CBNDTR_BNDT[16:0] bits
0528    * - BlockRepeatDestAddrUpdateMode:   MDMA_CBNDTR_BRDUM[19] bit
0529    * - BlockRepeatDestAddrUpdateMode:   MDMA_CBNDTR_BRSUM[18] bit
0530    */
0531   LL_MDMA_ConfigBlkCounters(MDMAx, Channel, MDMA_InitStruct->BlockRepeatCount, MDMA_InitStruct->BlockDataLength);
0532 
0533   LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMAx, Channel, MDMA_InitStruct->BlockRepeatDestAddrUpdateMode | \
0534                                                    MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode);
0535 
0536 
0537 
0538   /*-------------------------- MDMAx CSAR Configuration --------------------------
0539    * Configure the Transfer source address with parameter :
0540    * - SrcAddress:     MDMA_CSAR_SAR[31:0] bits
0541    */
0542   LL_MDMA_SetSourceAddress(MDMAx, Channel, MDMA_InitStruct->SrcAddress);
0543 
0544   /*-------------------------- MDMAx CDAR Configuration --------------------------
0545    * Configure the Transfer destination address with parameter :
0546    * - DstAddress:     MDMA_CDAR_DAR[31:0] bits
0547    */
0548   LL_MDMA_SetDestinationAddress(MDMAx, Channel, MDMA_InitStruct->DstAddress);
0549 
0550   /*-------------------------- MDMAx CBRUR Configuration --------------------------
0551    * Configure the Transfer Block repeat address update value with parameter :
0552    * - BlockRepeatDestAddrUpdateVal:    MDMA_CBRUR_DUV[31:16] bits
0553    * - BlockRepeatSrcAddrUpdateVal:     MDMA_CBRUR_SUV[15:0] bits
0554    */
0555   LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMAx, Channel, MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal, \
0556                                                MDMA_InitStruct->BlockRepeatDestAddrUpdateVal);
0557 
0558   /*-------------------------- MDMAx CLAR Configuration --------------------------
0559    * Configure the Transfer linked list address with parameter :
0560    * - LinkAddress:     MDMA_CLAR_LAR[31:0] bits
0561    */
0562   LL_MDMA_SetLinkAddress(MDMAx, Channel, MDMA_InitStruct->LinkAddress);
0563 
0564   /*-------------------------- MDMAx CTBR Configuration --------------------------
0565    * Configure the Transfer HW trigger and bus selection with parameter :
0566    * - DestBus:     MDMA_TBR_DBUS[17] bit
0567    * - SrcBus:      MDMA_TBR_SBUS[16] bit
0568    * - HWTrigger:   MDMA_TBR_TSEL[5:0] bits
0569    */
0570   LL_MDMA_ConfigBusSelection(MDMAx, Channel, MDMA_InitStruct->DestBus | MDMA_InitStruct->SrcBus);
0571 
0572   LL_MDMA_SetHWTrigger(MDMAx, Channel, MDMA_InitStruct->HWTrigger);
0573 
0574   /*-------------------------- MDMAx CMAR Configuration --------------------------
0575    * Configure the mask address with parameter :
0576    * - MaskAddress:     MDMA_CMAR_MAR[31:0] bits
0577    */
0578   LL_MDMA_SetMaskAddress(MDMAx, Channel, MDMA_InitStruct->MaskAddress);
0579 
0580   /*-------------------------- MDMAx CMDR Configuration --------------------------
0581    * Configure the mask data with parameter :
0582    * - MaskData:     MDMA_CMDR_MDR[31:0] bits
0583    */
0584   LL_MDMA_SetMaskData(MDMAx, Channel, MDMA_InitStruct->MaskData);
0585 
0586   return (uint32_t)SUCCESS;
0587 }
0588 
0589 /**
0590   * @brief  Set each @ref LL_MDMA_InitTypeDef field to default value.
0591   * @param  MDMA_InitStruct Pointer to a @ref LL_MDMA_InitTypeDef structure.
0592   * @retval None
0593   */
0594 void LL_MDMA_StructInit(LL_MDMA_InitTypeDef *MDMA_InitStruct)
0595 {
0596   /* Set DMA_InitStruct fields to default values */
0597   MDMA_InitStruct->SrcAddress                     = 0x00000000U;
0598   MDMA_InitStruct->DstAddress                     = 0x00000000U;
0599   MDMA_InitStruct->BlockDataLength                = 0x00000000U;
0600   MDMA_InitStruct->BlockRepeatCount               = 0x00000000U;
0601   MDMA_InitStruct->WordEndianess                  = LL_MDMA_WORD_ENDIANNESS_PRESERVE;
0602   MDMA_InitStruct->HalfWordEndianess              = LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE;
0603   MDMA_InitStruct->ByteEndianess                  = LL_MDMA_BYTE_ENDIANNESS_PRESERVE;
0604   MDMA_InitStruct->Priority                       = LL_MDMA_PRIORITY_LOW;
0605   MDMA_InitStruct->BufferableWriteMode            = LL_MDMA_BUFF_WRITE_DISABLE;
0606   MDMA_InitStruct->RequestMode                    = LL_MDMA_REQUEST_MODE_HW;
0607   MDMA_InitStruct->TriggerMode                    = LL_MDMA_BUFFER_TRANSFER;
0608   MDMA_InitStruct->PaddingAlignment               = LL_MDMA_DATAALIGN_RIGHT;
0609   MDMA_InitStruct->PackMode                       = LL_MDMA_PACK_DISABLE;
0610   MDMA_InitStruct->BufferTransferLength           = 0x00000000U;
0611   MDMA_InitStruct->DestBurst                      = LL_MDMA_DEST_BURST_SINGLE;
0612   MDMA_InitStruct->SrctBurst                      = LL_MDMA_SRC_BURST_SINGLE;
0613   MDMA_InitStruct->DestIncSize                    = LL_MDMA_DEST_INC_OFFSET_BYTE;
0614   MDMA_InitStruct->SrcIncSize                     = LL_MDMA_SRC_INC_OFFSET_BYTE;
0615   MDMA_InitStruct->DestDataSize                   = LL_MDMA_DEST_DATA_SIZE_BYTE;
0616   MDMA_InitStruct->SrcDataSize                    = LL_MDMA_SRC_DATA_SIZE_BYTE;
0617   MDMA_InitStruct->DestIncMode                    = LL_MDMA_DEST_FIXED;
0618   MDMA_InitStruct->SrcIncMode                     = LL_MDMA_SRC_FIXED;
0619   MDMA_InitStruct->BlockRepeatDestAddrUpdateMode  = LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT;
0620   MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode   = LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT;
0621   MDMA_InitStruct->BlockRepeatDestAddrUpdateVal   = 0x00000000U;
0622   MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal    = 0x00000000U;
0623   MDMA_InitStruct->LinkAddress                    = 0x00000000U;
0624   MDMA_InitStruct->DestBus                        = LL_MDMA_DEST_BUS_SYSTEM_AXI;
0625   MDMA_InitStruct->SrcBus                         = LL_MDMA_SRC_BUS_SYSTEM_AXI;
0626   MDMA_InitStruct->HWTrigger                      = LL_MDMA_REQ_DMA1_STREAM0_TC;
0627   MDMA_InitStruct->MaskAddress                    = 0x00000000U;
0628   MDMA_InitStruct->MaskData                       = 0x00000000U;
0629 }
0630 
0631 /**
0632   * @brief  Initializes MDMA linked list node according to the specified
0633   *         parameters in the MDMA_InitStruct.
0634   * @param  MDMA_InitStruct Pointer to a @ref LL_MDMA_InitTypeDef structure that contains
0635   *         linked list node registers configurations.
0636   * @param  pNode Pointer to linked list node to fill according to MDMA_InitStruct parameters.
0637   * @retval None
0638   */
0639 void LL_MDMA_CreateLinkNode(LL_MDMA_InitTypeDef *MDMA_InitStruct, LL_MDMA_LinkNodeTypeDef *pNode)
0640 {
0641 
0642   /* Check the MDMA parameters from MDMA_InitStruct */
0643   assert_param(IS_LL_MDMA_BLK_DATALENGTH(MDMA_InitStruct->BlockDataLength));
0644   assert_param(IS_LL_MDMA_BLK_REPEATCOUNT(MDMA_InitStruct->BlockRepeatCount));
0645 
0646   assert_param(IS_LL_MDMA_BUFFWRITEMODE(MDMA_InitStruct->BufferableWriteMode));
0647   assert_param(IS_LL_MDMA_REQUESTMODE(MDMA_InitStruct->RequestMode));
0648   assert_param(IS_LL_MDMA_TRIGGERMODE(MDMA_InitStruct->TriggerMode));
0649   assert_param(IS_LL_MDMA_PADDINGALIGNEMENT(MDMA_InitStruct->PaddingAlignment));
0650   assert_param(IS_LL_MDMA_PACKMODE(MDMA_InitStruct->PackMode));
0651   assert_param(IS_LL_MDMA_BUFFER_XFERLENGTH(MDMA_InitStruct->BufferTransferLength));
0652   assert_param(IS_LL_MDMA_DESTBURST(MDMA_InitStruct->DestBurst));
0653   assert_param(IS_LL_MDMA_SRCTBURST(MDMA_InitStruct->SrctBurst));
0654   assert_param(IS_LL_MDMA_DESTINCSIZE(MDMA_InitStruct->DestIncSize));
0655   assert_param(IS_LL_MDMA_SRCINCSIZE(MDMA_InitStruct->SrcIncSize));
0656   assert_param(IS_LL_MDMA_DESTDATASIZE(MDMA_InitStruct->DestDataSize));
0657   assert_param(IS_LL_MDMA_SRCDATASIZE(MDMA_InitStruct->SrcDataSize));
0658   assert_param(IS_LL_MDMA_DESTINCMODE(MDMA_InitStruct->DestIncMode));
0659   assert_param(IS_LL_MDMA_SRCINCMODE(MDMA_InitStruct->SrcIncMode));
0660   assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatDestAddrUpdateMode));
0661   assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode));
0662   assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatDestAddrUpdateVal));
0663   assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal));
0664   assert_param(IS_LL_MDMA_DEST_BUS(MDMA_InitStruct->DestBus));
0665   assert_param(IS_LL_MDMA_SRC_BUS(MDMA_InitStruct->SrcBus));
0666   assert_param(IS_LL_MDMA_HWTRIGGER(MDMA_InitStruct->HWTrigger));
0667 
0668 
0669   /*-------------------------- MDMAx CTCR Configuration --------------------------
0670    * Configure the Transfer  parameter :
0671    * - BufferableWriteMode:     MDMA_CTCR_BWM[31] bit
0672    * - RequestMode:             MDMA_CTCR_SWRM[30] bit
0673    * - TriggerMode:             MDMA_CTCR_TRGM[29:28] bits
0674    * - PaddingAlignment:       MDMA_CTCR_PAM[27:26] bits
0675    * - PackMode:                MDMA_CTCR_PKE[25] bit
0676    * - BufferTransferLength:    MDMA_CTCR_TLEN[24:18] bits
0677    * - DestBurst:               MDMA_CTCR_DBURST[17:15] bits
0678    * - SrctBurst:               MDMA_CTCR_SBURST[14:12] bits
0679    * - DestIncSize:             MDMA_CTCR_DINCOS[11:10] bits
0680    * - SrcIncSize:              MDMA_CTCR_SINCOS[9:8] bits
0681    * - DestDataSize:            MDMA_CTCR_DSIZE[7:6] bits
0682    * - SrcDataSize:             MDMA_CTCR_SSIZE[5:4] bits
0683    * - DestIncMode:             MDMA_CTCR_DINC[3:2] bits
0684    * - SrcIncMode:              MDMA_CTCR_SINC[1:0] bits
0685    */
0686   pNode->CTCR =  MDMA_InitStruct->BufferableWriteMode | \
0687                  MDMA_InitStruct->RequestMode         | \
0688                  MDMA_InitStruct->TriggerMode         | \
0689                  MDMA_InitStruct->PaddingAlignment    | \
0690                  MDMA_InitStruct->PackMode            | \
0691                  MDMA_InitStruct->DestBurst           | \
0692                  MDMA_InitStruct->SrctBurst           | \
0693                  MDMA_InitStruct->DestIncSize         | \
0694                  MDMA_InitStruct->SrcIncSize          | \
0695                  MDMA_InitStruct->DestDataSize        | \
0696                  MDMA_InitStruct->SrcDataSize         | \
0697                  MDMA_InitStruct->DestIncMode         | \
0698                  MDMA_InitStruct->SrcIncMode          | \
0699                 ((MDMA_InitStruct->BufferTransferLength << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk);
0700 
0701 
0702 
0703   /*-------------------------- MDMAx CBNDTR Configuration --------------------------
0704    * Configure the Transfer Block counters and update mode with parameter :
0705    * - BlockRepeatCount:                MDMA_CBNDTR_BRC[31:20] bits
0706    * - BlockDataLength:                 MDMA_CBNDTR_BNDT[16:0] bits
0707    * - BlockRepeatDestAddrUpdateMode:   MDMA_CBNDTR_BRDUM[19] bit
0708    * - BlockRepeatDestAddrUpdateMode:   MDMA_CBNDTR_BRSUM[18] bit
0709    */
0710   pNode->CBNDTR =  ((MDMA_InitStruct->BlockRepeatCount << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC_Msk) | \
0711                     MDMA_InitStruct->BlockRepeatDestAddrUpdateMode                                    | \
0712                     MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode                                     | \
0713                    (MDMA_InitStruct->BlockDataLength & MDMA_CBNDTR_BNDT_Msk);
0714 
0715 
0716   /*-------------------------- MDMAx CSAR Configuration --------------------------
0717    * Configure the Transfer source address with parameter :
0718    * - SrcAddress:     MDMA_CSAR_SAR[31:0] bits
0719    */
0720   pNode->CSAR =  MDMA_InitStruct->SrcAddress;
0721 
0722 
0723   /*-------------------------- MDMAx CDAR Configuration --------------------------
0724    * Configure the Transfer destination address with parameter :
0725    * - DstAddress:     MDMA_CDAR_DAR[31:0] bits
0726    */
0727   pNode->CDAR =  MDMA_InitStruct->DstAddress;
0728 
0729   /*-------------------------- MDMAx CBRUR Configuration --------------------------
0730    * Configure the Transfer Block repeat address update value with parameter :
0731    * - BlockRepeatDestAddrUpdateVal:    MDMA_CBRUR_DUV[31:16] bits
0732    * - BlockRepeatSrcAddrUpdateVal:     MDMA_CBRUR_SUV[15:0] bits
0733    */
0734   pNode->CBRUR =  (MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal & MDMA_CBRUR_SUV_Msk)  | \
0735                   ((MDMA_InitStruct->BlockRepeatDestAddrUpdateVal << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk) ;
0736 
0737   /*-------------------------- MDMAx CLAR Configuration --------------------------
0738    * Configure the Transfer linked list address with parameter :
0739    * - LinkAddress:     MDMA_CLAR_LAR[31:0] bits
0740    */
0741   pNode->CLAR = MDMA_InitStruct->LinkAddress;
0742 
0743   /*-------------------------- MDMAx CTBR Configuration --------------------------
0744    * Configure the Transfer HW trigger and bus selection with parameter :
0745    * - DestBus:     MDMA_TBR_DBUS[17] bit
0746    * - SrcBus:      MDMA_TBR_SBUS[16] bit
0747    * - HWTrigger:   MDMA_TBR_TSEL[5:0] bits
0748    */
0749   pNode->CTBR = MDMA_InitStruct->DestBus | MDMA_InitStruct->SrcBus | MDMA_InitStruct->HWTrigger;
0750 
0751   /*-------------------------- MDMAx CMAR Configuration --------------------------
0752    * Configure the mask address with parameter :
0753    * - MaskAddress:     MDMA_CMAR_MAR[31:0] bits
0754    */
0755   pNode->CMAR = MDMA_InitStruct->MaskAddress;
0756 
0757   /*-------------------------- MDMAx CMDR Configuration --------------------------
0758    * Configure the mask data with parameter :
0759    * - MaskData:     MDMA_CMDR_MDR[31:0] bits
0760    */
0761   pNode->CMDR = MDMA_InitStruct->MaskData;
0762 
0763 
0764   pNode->Reserved = 0;
0765 
0766 }
0767 
0768 /**
0769   * @brief  Connect Linked list Nodes.
0770   * @param  pPrevLinkNode Pointer to previous linked list node to be connected to new Lined list node.
0771   * @param  pNewLinkNode Pointer to new Linked list.
0772   * @retval None
0773   */
0774 void LL_MDMA_ConnectLinkNode(LL_MDMA_LinkNodeTypeDef *pPrevLinkNode, LL_MDMA_LinkNodeTypeDef *pNewLinkNode)
0775 {
0776   pPrevLinkNode->CLAR = (uint32_t)pNewLinkNode;
0777 }
0778 
0779 /**
0780   * @brief  Disconnect the next linked list node.
0781   * @param  pLinkNode Pointer to linked list node to be disconnected from the next one.
0782   * @retval None
0783   */
0784 void LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef *pLinkNode)
0785 {
0786   pLinkNode->CLAR = 0;
0787 }
0788 
0789 /**
0790   * @}
0791   */
0792 
0793 /**
0794   * @}
0795   */
0796 
0797 /**
0798   * @}
0799   */
0800 
0801 #endif /* MDMA */
0802 
0803 /**
0804   * @}
0805   */
0806 
0807 #endif /* USE_FULL_LL_DRIVER */
0808
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