stm32h7/hal/stm32h7xx_ll_fmc.c

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_ll_fmc.c
0004   * @author  MCD Application Team
0005   * @brief   FMC Low Layer HAL module driver.
0006   *
0007   *          This file provides firmware functions to manage the following
0008   *          functionalities of the Flexible Memory Controller (FMC) peripheral memories:
0009   *           + Initialization/de-initialization functions
0010   *           + Peripheral Control functions
0011   *           + Peripheral State functions
0012   *
0013   ******************************************************************************
0014   * @attention
0015   *
0016   * Copyright (c) 2017 STMicroelectronics.
0017   * All rights reserved.
0018   *
0019   * This software is licensed under terms that can be found in the LICENSE file
0020   * in the root directory of this software component.
0021   * If no LICENSE file comes with this software, it is provided AS-IS.
0022   *
0023   ******************************************************************************
0024   @verbatim
0025   ==============================================================================
0026                         ##### FMC peripheral features #####
0027   ==============================================================================
0028   [..] The Flexible memory controller (FMC) includes following memory controllers:
0029        (+) The NOR/PSRAM memory controller
0030      (+) The NAND memory controller
0031        (+) The Synchronous DRAM (SDRAM) controller
0032
0033   [..] The FMC functional block makes the interface with synchronous and asynchronous static
0034        memories and SDRAM memories. Its main purposes are:
0035        (+) to translate AHB transactions into the appropriate external device protocol
0036        (+) to meet the access time requirements of the external memory devices
0037
0038   [..] All external memories share the addresses, data and control signals with the controller.
0039        Each external device is accessed by means of a unique Chip Select. The FMC performs
0040        only one access at a time to an external device.
0041        The main features of the FMC controller are the following:
0042         (+) Interface with static-memory mapped devices including:
0043            (++) Static random access memory (SRAM)
0044            (++) Read-only memory (ROM)
0045            (++) NOR Flash memory/OneNAND Flash memory
0046            (++) PSRAM (4 memory banks)
0047            (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
0048                 data
0049         (+) Interface with synchronous DRAM (SDRAM) memories
0050         (+) Independent Chip Select control for each memory bank
0051         (+) Independent configuration for each memory bank
0052
0053   @endverbatim
0054   ******************************************************************************
0055   */
0056
0057 /* Includes ------------------------------------------------------------------*/
0058 #include "stm32h7xx_hal.h"
0059
0060 /** @addtogroup STM32H7xx_HAL_Driver
0061   * @{
0062   */
0063 #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\
0064  || defined(HAL_SRAM_MODULE_ENABLED)
0065
0066 /** @defgroup FMC_LL  FMC Low Layer
0067   * @ingroup RTEMSBSPsARMSTM32H7
0068   * @brief FMC driver modules
0069   * @{
0070   */
0071
0072 /* Private typedef -----------------------------------------------------------*/
0073 /* Private define ------------------------------------------------------------*/
0074
0075 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
0076   * @ingroup RTEMSBSPsARMSTM32H7
0077   * @{
0078   */
0079
0080 /* ----------------------- FMC registers bit mask --------------------------- */
0081
0082 /* --- BCR Register ---*/
0083 /* BCR register clear mask */
0084
0085 /* --- BTR Register ---*/
0086 /* BTR register clear mask */
0087 #define BTR_CLEAR_MASK    ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD  |\
0088                                       FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
0089                                       FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT  |\
0090                                       FMC_BTRx_ACCMOD))
0091
0092 /* --- BWTR Register ---*/
0093 /* BWTR register clear mask */
0094 #define BWTR_CLEAR_MASK   ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD  |\
0095                                       FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
0096                                       FMC_BWTRx_ACCMOD))
0097
0098 /* --- PCR Register ---*/
0099 /* PCR register clear mask */
0100 #define PCR_CLEAR_MASK    ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN  | \
0101                                       FMC_PCR_PWID    | FMC_PCR_ECCEN  | \
0102                                       FMC_PCR_TCLR    | FMC_PCR_TAR    | \
0103                                       FMC_PCR_ECCPS))
0104 /* --- PMEM Register ---*/
0105 /* PMEM register clear mask */
0106 #define PMEM_CLEAR_MASK   ((uint32_t)(FMC_PMEM_MEMSET  | FMC_PMEM_MEMWAIT |\
0107                                       FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
0108
0109 /* --- PATT Register ---*/
0110 /* PATT register clear mask */
0111 #define PATT_CLEAR_MASK   ((uint32_t)(FMC_PATT_ATTSET  | FMC_PATT_ATTWAIT |\
0112                                       FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
0113
0114
0115 /* --- SDCR Register ---*/
0116 /* SDCR register clear mask */
0117 #define SDCR_CLEAR_MASK   ((uint32_t)(FMC_SDCRx_NC    | FMC_SDCRx_NR     | \
0118                                       FMC_SDCRx_MWID  | FMC_SDCRx_NB     | \
0119                                       FMC_SDCRx_CAS   | FMC_SDCRx_WP     | \
0120                                       FMC_SDCRx_SDCLK | FMC_SDCRx_RBURST | \
0121                                       FMC_SDCRx_RPIPE))
0122
0123 /* --- SDTR Register ---*/
0124 /* SDTR register clear mask */
0125 #define SDTR_CLEAR_MASK   ((uint32_t)(FMC_SDTRx_TMRD  | FMC_SDTRx_TXSR   | \
0126                                       FMC_SDTRx_TRAS  | FMC_SDTRx_TRC    | \
0127                                       FMC_SDTRx_TWR   | FMC_SDTRx_TRP    | \
0128                                       FMC_SDTRx_TRCD))
0129
0130 /**
0131   * @}
0132   */
0133
0134 /* Private macro -------------------------------------------------------------*/
0135 /* Private variables ---------------------------------------------------------*/
0136 /* Private function prototypes -----------------------------------------------*/
0137 /* Exported functions --------------------------------------------------------*/
0138
0139 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
0140   * @ingroup RTEMSBSPsARMSTM32H7
0141   * @{
0142   */
0143
0144
0145 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
0146   * @ingroup RTEMSBSPsARMSTM32H7
0147   * @brief  NORSRAM Controller functions
0148   *
0149   @verbatim
0150   ==============================================================================
0151                    ##### How to use NORSRAM device driver #####
0152   ==============================================================================
0153
0154   [..]
0155     This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
0156     to run the NORSRAM external devices.
0157
0158     (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
0159     (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
0160     (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
0161     (+) FMC NORSRAM bank extended timing configuration using the function
0162         FMC_NORSRAM_Extended_Timing_Init()
0163     (+) FMC NORSRAM bank enable/disable write operation using the functions
0164         FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
0165
0166 @endverbatim
0167   * @{
0168   */
0169
0170 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
0171   * @ingroup RTEMSBSPsARMSTM32H7
0172   * @brief    Initialization and Configuration functions
0173   *
0174   @verbatim
0175   ==============================================================================
0176               ##### Initialization and de_initialization functions #####
0177   ==============================================================================
0178   [..]
0179     This section provides functions allowing to:
0180     (+) Initialize and configure the FMC NORSRAM interface
0181     (+) De-initialize the FMC NORSRAM interface
0182     (+) Configure the FMC clock and associated GPIOs
0183
0184 @endverbatim
0185   * @{
0186   */
0187
0188 /**
0189   * @brief  Initialize the FMC_NORSRAM device according to the specified
0190   *         control parameters in the FMC_NORSRAM_InitTypeDef
0191   * @param  Device Pointer to NORSRAM device instance
0192   * @param  Init Pointer to NORSRAM Initialization structure
0193   * @retval HAL status
0194   */
0195 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
0196                                     FMC_NORSRAM_InitTypeDef *Init)
0197 {
0198   uint32_t flashaccess;
0199   uint32_t btcr_reg;
0200   uint32_t mask;
0201
0202   /* Check the parameters */
0203   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
0204   assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
0205   assert_param(IS_FMC_MUX(Init->DataAddressMux));
0206   assert_param(IS_FMC_MEMORY(Init->MemoryType));
0207   assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
0208   assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
0209   assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
0210   assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
0211   assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
0212   assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
0213   assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
0214   assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
0215   assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
0216   assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
0217   assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
0218   assert_param(IS_FMC_PAGESIZE(Init->PageSize));
0219
0220   /* Disable NORSRAM Device */
0221   __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
0222
0223   /* Set NORSRAM device control parameters */
0224   if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
0225   {
0226     flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
0227   }
0228   else
0229   {
0230     flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
0231   }
0232
0233   btcr_reg = (flashaccess                   | \
0234               Init->DataAddressMux          | \
0235               Init->MemoryType              | \
0236               Init->MemoryDataWidth         | \
0237               Init->BurstAccessMode         | \
0238               Init->WaitSignalPolarity      | \
0239               Init->WaitSignalActive        | \
0240               Init->WriteOperation          | \
0241               Init->WaitSignal              | \
0242               Init->ExtendedMode            | \
0243               Init->AsynchronousWait        | \
0244               Init->WriteBurst);
0245
0246   btcr_reg |= Init->ContinuousClock;
0247   btcr_reg |= Init->WriteFifo;
0248   btcr_reg |= Init->PageSize;
0249
0250   mask = (FMC_BCRx_MBKEN                |
0251           FMC_BCRx_MUXEN                |
0252           FMC_BCRx_MTYP                 |
0253           FMC_BCRx_MWID                 |
0254           FMC_BCRx_FACCEN               |
0255           FMC_BCRx_BURSTEN              |
0256           FMC_BCRx_WAITPOL              |
0257           FMC_BCRx_WAITCFG              |
0258           FMC_BCRx_WREN                 |
0259           FMC_BCRx_WAITEN               |
0260           FMC_BCRx_EXTMOD               |
0261           FMC_BCRx_ASYNCWAIT            |
0262           FMC_BCRx_CBURSTRW);
0263
0264   mask |= FMC_BCR1_CCLKEN;
0265   mask |= FMC_BCR1_WFDIS;
0266   mask |= FMC_BCRx_CPSIZE;
0267
0268   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
0269
0270   /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
0271   if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
0272   {
0273     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
0274   }
0275
0276   if (Init->NSBank != FMC_NORSRAM_BANK1)
0277   {
0278     /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
0279     SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
0280   }
0281
0282   return HAL_OK;
0283 }
0284
0285 /**
0286   * @brief  DeInitialize the FMC_NORSRAM peripheral
0287   * @param  Device Pointer to NORSRAM device instance
0288   * @param  ExDevice Pointer to NORSRAM extended mode device instance
0289   * @param  Bank NORSRAM bank number
0290   * @retval HAL status
0291   */
0292 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
0293                                      FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
0294 {
0295   /* Check the parameters */
0296   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
0297   assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
0298   assert_param(IS_FMC_NORSRAM_BANK(Bank));
0299
0300   /* Disable the FMC_NORSRAM device */
0301   __FMC_NORSRAM_DISABLE(Device, Bank);
0302
0303   /* De-initialize the FMC_NORSRAM device */
0304   /* FMC_NORSRAM_BANK1 */
0305   if (Bank == FMC_NORSRAM_BANK1)
0306   {
0307     Device->BTCR[Bank] = 0x000030DBU;
0308   }
0309   /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
0310   else
0311   {
0312     Device->BTCR[Bank] = 0x000030D2U;
0313   }
0314
0315   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
0316   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
0317
0318   return HAL_OK;
0319 }
0320
0321 /**
0322   * @brief  Initialize the FMC_NORSRAM Timing according to the specified
0323   *         parameters in the FMC_NORSRAM_TimingTypeDef
0324   * @param  Device Pointer to NORSRAM device instance
0325   * @param  Timing Pointer to NORSRAM Timing structure
0326   * @param  Bank NORSRAM bank number
0327   * @retval HAL status
0328   */
0329 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
0330                                           FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
0331 {
0332   uint32_t tmpr;
0333
0334   /* Check the parameters */
0335   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
0336   assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
0337   assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
0338   assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
0339   assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
0340   assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
0341   assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
0342   assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
0343   assert_param(IS_FMC_NORSRAM_BANK(Bank));
0344
0345   /* Set FMC_NORSRAM device timing parameters */
0346   MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                                  |
0347                                                        ((Timing->AddressHoldTime)        << FMC_BTRx_ADDHLD_Pos)  |
0348                                                        ((Timing->DataSetupTime)          << FMC_BTRx_DATAST_Pos)  |
0349                                                        ((Timing->BusTurnAroundDuration)  << FMC_BTRx_BUSTURN_Pos) |
0350                                                        (((Timing->CLKDivision) - 1U)     << FMC_BTRx_CLKDIV_Pos)  |
0351                                                        (((Timing->DataLatency) - 2U)     << FMC_BTRx_DATLAT_Pos)  |
0352                                                        (Timing->AccessMode)));
0353
0354   /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
0355   if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
0356   {
0357     tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));
0358     tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
0359     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
0360   }
0361
0362   return HAL_OK;
0363 }
0364
0365 /**
0366   * @brief  Initialize the FMC_NORSRAM Extended mode Timing according to the specified
0367   *         parameters in the FMC_NORSRAM_TimingTypeDef
0368   * @param  Device Pointer to NORSRAM device instance
0369   * @param  Timing Pointer to NORSRAM Timing structure
0370   * @param  Bank NORSRAM bank number
0371   * @param  ExtendedMode FMC Extended Mode
0372   *          This parameter can be one of the following values:
0373   *            @arg FMC_EXTENDED_MODE_DISABLE
0374   *            @arg FMC_EXTENDED_MODE_ENABLE
0375   * @retval HAL status
0376   */
0377 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
0378                                                    FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
0379                                                    uint32_t ExtendedMode)
0380 {
0381   /* Check the parameters */
0382   assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
0383
0384   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
0385   if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
0386   {
0387     /* Check the parameters */
0388     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
0389     assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
0390     assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
0391     assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
0392     assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
0393     assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
0394     assert_param(IS_FMC_NORSRAM_BANK(Bank));
0395
0396     /* Set NORSRAM device timing register for write configuration, if extended mode is used */
0397     MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
0398                                                      ((Timing->AddressHoldTime)        << FMC_BWTRx_ADDHLD_Pos)  |
0399                                                      ((Timing->DataSetupTime)          << FMC_BWTRx_DATAST_Pos)  |
0400                                                      Timing->AccessMode                                          |
0401                                                      ((Timing->BusTurnAroundDuration)  << FMC_BWTRx_BUSTURN_Pos)));
0402   }
0403   else
0404   {
0405     Device->BWTR[Bank] = 0x0FFFFFFFU;
0406   }
0407
0408   return HAL_OK;
0409 }
0410 /**
0411   * @}
0412   */
0413
0414 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
0415   *  @brief   management functions
0416   *
0417 @verbatim
0418   ==============================================================================
0419                       ##### FMC_NORSRAM Control functions #####
0420   ==============================================================================
0421   [..]
0422     This subsection provides a set of functions allowing to control dynamically
0423     the FMC NORSRAM interface.
0424
0425 @endverbatim
0426   * @{
0427   */
0428
0429 /**
0430   * @brief  Enables dynamically FMC_NORSRAM write operation.
0431   * @param  Device Pointer to NORSRAM device instance
0432   * @param  Bank NORSRAM bank number
0433   * @retval HAL status
0434   */
0435 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
0436 {
0437   /* Check the parameters */
0438   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
0439   assert_param(IS_FMC_NORSRAM_BANK(Bank));
0440
0441   /* Enable write operation */
0442   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
0443
0444   return HAL_OK;
0445 }
0446
0447 /**
0448   * @brief  Disables dynamically FMC_NORSRAM write operation.
0449   * @param  Device Pointer to NORSRAM device instance
0450   * @param  Bank NORSRAM bank number
0451   * @retval HAL status
0452   */
0453 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
0454 {
0455   /* Check the parameters */
0456   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
0457   assert_param(IS_FMC_NORSRAM_BANK(Bank));
0458
0459   /* Disable write operation */
0460   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
0461
0462   return HAL_OK;
0463 }
0464
0465 /**
0466   * @}
0467   */
0468
0469 /**
0470   * @}
0471   */
0472
0473
0474 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
0475   * @ingroup RTEMSBSPsARMSTM32H7
0476   * @brief    NAND Controller functions
0477   *
0478   @verbatim
0479   ==============================================================================
0480                     ##### How to use NAND device driver #####
0481   ==============================================================================
0482   [..]
0483     This driver contains a set of APIs to interface with the FMC NAND banks in order
0484     to run the NAND external devices.
0485
0486     (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
0487     (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
0488     (+) FMC NAND bank common space timing configuration using the function
0489         FMC_NAND_CommonSpace_Timing_Init()
0490     (+) FMC NAND bank attribute space timing configuration using the function
0491         FMC_NAND_AttributeSpace_Timing_Init()
0492     (+) FMC NAND bank enable/disable ECC correction feature using the functions
0493         FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
0494     (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
0495
0496 @endverbatim
0497   * @{
0498   */
0499
0500 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
0501   * @ingroup RTEMSBSPsARMSTM32H7
0502   *  @brief    Initialization and Configuration functions
0503   *
0504 @verbatim
0505   ==============================================================================
0506               ##### Initialization and de_initialization functions #####
0507   ==============================================================================
0508   [..]
0509     This section provides functions allowing to:
0510     (+) Initialize and configure the FMC NAND interface
0511     (+) De-initialize the FMC NAND interface
0512     (+) Configure the FMC clock and associated GPIOs
0513
0514 @endverbatim
0515   * @{
0516   */
0517
0518 /**
0519   * @brief  Initializes the FMC_NAND device according to the specified
0520   *         control parameters in the FMC_NAND_HandleTypeDef
0521   * @param  Device Pointer to NAND device instance
0522   * @param  Init Pointer to NAND Initialization structure
0523   * @retval HAL status
0524   */
0525 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
0526 {
0527   /* Check the parameters */
0528   assert_param(IS_FMC_NAND_DEVICE(Device));
0529   assert_param(IS_FMC_NAND_BANK(Init->NandBank));
0530   assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
0531   assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
0532   assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
0533   assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
0534   assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
0535   assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
0536
0537   /* NAND bank 3 registers configuration */
0538   MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature                            |
0539                                            FMC_PCR_MEMORY_TYPE_NAND                     |
0540                                            Init->MemoryDataWidth                        |
0541                                            Init->EccComputation                         |
0542                                            Init->ECCPageSize                            |
0543                                            ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos)  |
0544                                            ((Init->TARSetupTime)  << FMC_PCR_TAR_Pos)));
0545
0546   return HAL_OK;
0547 }
0548
0549 /**
0550   * @brief  Initializes the FMC_NAND Common space Timing according to the specified
0551   *         parameters in the FMC_NAND_PCC_TimingTypeDef
0552   * @param  Device Pointer to NAND device instance
0553   * @param  Timing Pointer to NAND timing structure
0554   * @param  Bank NAND bank number
0555   * @retval HAL status
0556   */
0557 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
0558                                                    FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
0559 {
0560   /* Check the parameters */
0561   assert_param(IS_FMC_NAND_DEVICE(Device));
0562   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
0563   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
0564   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
0565   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
0566   assert_param(IS_FMC_NAND_BANK(Bank));
0567
0568   /* Prevent unused argument(s) compilation warning if no assert_param check */
0569   UNUSED(Bank);
0570
0571   /* NAND bank 3 registers configuration */
0572   MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime                                 |
0573                                              ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
0574                                              ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
0575                                              ((Timing->HiZSetupTime)  << FMC_PMEM_MEMHIZ_Pos)));
0576
0577   return HAL_OK;
0578 }
0579
0580 /**
0581   * @brief  Initializes the FMC_NAND Attribute space Timing according to the specified
0582   *         parameters in the FMC_NAND_PCC_TimingTypeDef
0583   * @param  Device Pointer to NAND device instance
0584   * @param  Timing Pointer to NAND timing structure
0585   * @param  Bank NAND bank number
0586   * @retval HAL status
0587   */
0588 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
0589                                                       FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
0590 {
0591   /* Check the parameters */
0592   assert_param(IS_FMC_NAND_DEVICE(Device));
0593   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
0594   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
0595   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
0596   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
0597   assert_param(IS_FMC_NAND_BANK(Bank));
0598
0599   /* Prevent unused argument(s) compilation warning if no assert_param check */
0600   UNUSED(Bank);
0601
0602   /* NAND bank 3 registers configuration */
0603   MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime                                 |
0604                                              ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
0605                                              ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
0606                                              ((Timing->HiZSetupTime)  << FMC_PATT_ATTHIZ_Pos)));
0607
0608   return HAL_OK;
0609 }
0610
0611 /**
0612   * @brief  DeInitializes the FMC_NAND device
0613   * @param  Device Pointer to NAND device instance
0614   * @param  Bank NAND bank number
0615   * @retval HAL status
0616   */
0617 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
0618 {
0619   /* Check the parameters */
0620   assert_param(IS_FMC_NAND_DEVICE(Device));
0621   assert_param(IS_FMC_NAND_BANK(Bank));
0622
0623   /* Disable the NAND Bank */
0624   __FMC_NAND_DISABLE(Device, Bank);
0625
0626   /* De-initialize the NAND Bank */
0627   /* Prevent unused argument(s) compilation warning if no assert_param check */
0628   UNUSED(Bank);
0629
0630   /* Set the FMC_NAND_BANK3 registers to their reset values */
0631   WRITE_REG(Device->PCR,  0x00000018U);
0632   WRITE_REG(Device->SR,   0x00000040U);
0633   WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
0634   WRITE_REG(Device->PATT, 0xFCFCFCFCU);
0635
0636   return HAL_OK;
0637 }
0638
0639 /**
0640   * @}
0641   */
0642
0643 /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
0644   * @ingroup RTEMSBSPsARMSTM32H7
0645   *  @brief   management functions
0646   *
0647 @verbatim
0648   ==============================================================================
0649                        ##### FMC_NAND Control functions #####
0650   ==============================================================================
0651   [..]
0652     This subsection provides a set of functions allowing to control dynamically
0653     the FMC NAND interface.
0654
0655 @endverbatim
0656   * @{
0657   */
0658
0659
0660 /**
0661   * @brief  Enables dynamically FMC_NAND ECC feature.
0662   * @param  Device Pointer to NAND device instance
0663   * @param  Bank NAND bank number
0664   * @retval HAL status
0665   */
0666 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
0667 {
0668   /* Check the parameters */
0669   assert_param(IS_FMC_NAND_DEVICE(Device));
0670   assert_param(IS_FMC_NAND_BANK(Bank));
0671
0672   /* Enable ECC feature */
0673   /* Prevent unused argument(s) compilation warning if no assert_param check */
0674   UNUSED(Bank);
0675
0676   SET_BIT(Device->PCR, FMC_PCR_ECCEN);
0677
0678   return HAL_OK;
0679 }
0680
0681
0682 /**
0683   * @brief  Disables dynamically FMC_NAND ECC feature.
0684   * @param  Device Pointer to NAND device instance
0685   * @param  Bank NAND bank number
0686   * @retval HAL status
0687   */
0688 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
0689 {
0690   /* Check the parameters */
0691   assert_param(IS_FMC_NAND_DEVICE(Device));
0692   assert_param(IS_FMC_NAND_BANK(Bank));
0693
0694   /* Disable ECC feature */
0695   /* Prevent unused argument(s) compilation warning if no assert_param check */
0696   UNUSED(Bank);
0697
0698   CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
0699
0700   return HAL_OK;
0701 }
0702
0703 /**
0704   * @brief  Disables dynamically FMC_NAND ECC feature.
0705   * @param  Device Pointer to NAND device instance
0706   * @param  ECCval Pointer to ECC value
0707   * @param  Bank NAND bank number
0708   * @param  Timeout Timeout wait value
0709   * @retval HAL status
0710   */
0711 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
0712                                   uint32_t Timeout)
0713 {
0714   uint32_t tickstart;
0715
0716   /* Check the parameters */
0717   assert_param(IS_FMC_NAND_DEVICE(Device));
0718   assert_param(IS_FMC_NAND_BANK(Bank));
0719
0720   /* Get tick */
0721   tickstart = HAL_GetTick();
0722
0723   /* Wait until FIFO is empty */
0724   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
0725   {
0726     /* Check for the Timeout */
0727     if (Timeout != HAL_MAX_DELAY)
0728     {
0729       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
0730       {
0731         return HAL_TIMEOUT;
0732       }
0733     }
0734   }
0735
0736   /* Prevent unused argument(s) compilation warning if no assert_param check */
0737   UNUSED(Bank);
0738
0739   /* Get the ECCR register value */
0740   *ECCval = (uint32_t)Device->ECCR;
0741
0742   return HAL_OK;
0743 }
0744
0745 /**
0746   * @}
0747   */
0748
0749
0750
0751 /** @defgroup FMC_LL_SDRAM
0752   * @ingroup RTEMSBSPsARMSTM32H7
0753   * @brief    SDRAM Controller functions
0754   *
0755   @verbatim
0756   ==============================================================================
0757                      ##### How to use SDRAM device driver #####
0758   ==============================================================================
0759   [..]
0760     This driver contains a set of APIs to interface with the FMC SDRAM banks in order
0761     to run the SDRAM external devices.
0762
0763     (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
0764     (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
0765     (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
0766     (+) FMC SDRAM bank enable/disable write operation using the functions
0767         FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
0768     (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
0769
0770 @endverbatim
0771   * @{
0772   */
0773
0774 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
0775   *  @brief    Initialization and Configuration functions
0776   *
0777 @verbatim
0778   ==============================================================================
0779               ##### Initialization and de_initialization functions #####
0780   ==============================================================================
0781   [..]
0782     This section provides functions allowing to:
0783     (+) Initialize and configure the FMC SDRAM interface
0784     (+) De-initialize the FMC SDRAM interface
0785     (+) Configure the FMC clock and associated GPIOs
0786
0787 @endverbatim
0788   * @{
0789   */
0790
0791 /**
0792   * @brief  Initializes the FMC_SDRAM device according to the specified
0793   *         control parameters in the FMC_SDRAM_InitTypeDef
0794   * @param  Device Pointer to SDRAM device instance
0795   * @param  Init Pointer to SDRAM Initialization structure
0796   * @retval HAL status
0797   */
0798 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
0799 {
0800   /* Check the parameters */
0801   assert_param(IS_FMC_SDRAM_DEVICE(Device));
0802   assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
0803   assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
0804   assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
0805   assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
0806   assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
0807   assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
0808   assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
0809   assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
0810   assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
0811   assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
0812
0813   /* Set SDRAM bank configuration parameters */
0814   if (Init->SDBank == FMC_SDRAM_BANK1)
0815   {
0816     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
0817                SDCR_CLEAR_MASK,
0818                (Init->ColumnBitsNumber   |
0819                 Init->RowBitsNumber      |
0820                 Init->MemoryDataWidth    |
0821                 Init->InternalBankNumber |
0822                 Init->CASLatency         |
0823                 Init->WriteProtection    |
0824                 Init->SDClockPeriod      |
0825                 Init->ReadBurst          |
0826                 Init->ReadPipeDelay));
0827   }
0828   else /* FMC_Bank2_SDRAM */
0829   {
0830     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
0831                FMC_SDCRx_SDCLK           |
0832                FMC_SDCRx_RBURST          |
0833                FMC_SDCRx_RPIPE,
0834                (Init->SDClockPeriod      |
0835                 Init->ReadBurst          |
0836                 Init->ReadPipeDelay));
0837
0838     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
0839                SDCR_CLEAR_MASK,
0840                (Init->ColumnBitsNumber   |
0841                 Init->RowBitsNumber      |
0842                 Init->MemoryDataWidth    |
0843                 Init->InternalBankNumber |
0844                 Init->CASLatency         |
0845                 Init->WriteProtection));
0846   }
0847
0848   return HAL_OK;
0849 }
0850
0851
0852 /**
0853   * @brief  Initializes the FMC_SDRAM device timing according to the specified
0854   *         parameters in the FMC_SDRAM_TimingTypeDef
0855   * @param  Device Pointer to SDRAM device instance
0856   * @param  Timing Pointer to SDRAM Timing structure
0857   * @param  Bank SDRAM bank number
0858   * @retval HAL status
0859   */
0860 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
0861                                         FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
0862 {
0863   /* Check the parameters */
0864   assert_param(IS_FMC_SDRAM_DEVICE(Device));
0865   assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
0866   assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
0867   assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
0868   assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
0869   assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
0870   assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
0871   assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
0872   assert_param(IS_FMC_SDRAM_BANK(Bank));
0873
0874   /* Set SDRAM device timing parameters */
0875   if (Bank == FMC_SDRAM_BANK1)
0876   {
0877     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
0878                SDTR_CLEAR_MASK,
0879                (((Timing->LoadToActiveDelay) - 1U)                                      |
0880                 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
0881                 (((Timing->SelfRefreshTime) - 1U)      << FMC_SDTRx_TRAS_Pos) |
0882                 (((Timing->RowCycleDelay) - 1U)        << FMC_SDTRx_TRC_Pos)  |
0883                 (((Timing->WriteRecoveryTime) - 1U)    << FMC_SDTRx_TWR_Pos)  |
0884                 (((Timing->RPDelay) - 1U)              << FMC_SDTRx_TRP_Pos)  |
0885                 (((Timing->RCDDelay) - 1U)             << FMC_SDTRx_TRCD_Pos)));
0886   }
0887   else /* FMC_Bank2_SDRAM */
0888   {
0889     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
0890                FMC_SDTRx_TRC |
0891                FMC_SDTRx_TRP,
0892                (((Timing->RowCycleDelay) - 1U)         << FMC_SDTRx_TRC_Pos)  |
0893                (((Timing->RPDelay) - 1U)               << FMC_SDTRx_TRP_Pos));
0894
0895     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
0896                SDTR_CLEAR_MASK,
0897                (((Timing->LoadToActiveDelay) - 1U)                                      |
0898                 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
0899                 (((Timing->SelfRefreshTime) - 1U)      << FMC_SDTRx_TRAS_Pos) |
0900                 (((Timing->WriteRecoveryTime) - 1U)    << FMC_SDTRx_TWR_Pos)  |
0901                 (((Timing->RCDDelay) - 1U)             << FMC_SDTRx_TRCD_Pos)));
0902   }
0903
0904   return HAL_OK;
0905 }
0906
0907 /**
0908   * @brief  DeInitializes the FMC_SDRAM peripheral
0909   * @param  Device Pointer to SDRAM device instance
0910   * @retval HAL status
0911   */
0912 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
0913 {
0914   /* Check the parameters */
0915   assert_param(IS_FMC_SDRAM_DEVICE(Device));
0916   assert_param(IS_FMC_SDRAM_BANK(Bank));
0917
0918   /* De-initialize the SDRAM device */
0919   Device->SDCR[Bank] = 0x000002D0U;
0920   Device->SDTR[Bank] = 0x0FFFFFFFU;
0921   Device->SDCMR      = 0x00000000U;
0922   Device->SDRTR      = 0x00000000U;
0923   Device->SDSR       = 0x00000000U;
0924
0925   return HAL_OK;
0926 }
0927
0928 /**
0929   * @}
0930   */
0931
0932 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
0933   *  @brief   management functions
0934   *
0935 @verbatim
0936   ==============================================================================
0937                       ##### FMC_SDRAM Control functions #####
0938   ==============================================================================
0939   [..]
0940     This subsection provides a set of functions allowing to control dynamically
0941     the FMC SDRAM interface.
0942
0943 @endverbatim
0944   * @{
0945   */
0946
0947 /**
0948   * @brief  Enables dynamically FMC_SDRAM write protection.
0949   * @param  Device Pointer to SDRAM device instance
0950   * @param  Bank SDRAM bank number
0951   * @retval HAL status
0952   */
0953 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
0954 {
0955   /* Check the parameters */
0956   assert_param(IS_FMC_SDRAM_DEVICE(Device));
0957   assert_param(IS_FMC_SDRAM_BANK(Bank));
0958
0959   /* Enable write protection */
0960   SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
0961
0962   return HAL_OK;
0963 }
0964
0965 /**
0966   * @brief  Disables dynamically FMC_SDRAM write protection.
0967   * @param  hsdram FMC_SDRAM handle
0968   * @retval HAL status
0969   */
0970 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
0971 {
0972   /* Check the parameters */
0973   assert_param(IS_FMC_SDRAM_DEVICE(Device));
0974   assert_param(IS_FMC_SDRAM_BANK(Bank));
0975
0976   /* Disable write protection */
0977   CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
0978
0979   return HAL_OK;
0980 }
0981
0982 /**
0983   * @brief  Send Command to the FMC SDRAM bank
0984   * @param  Device Pointer to SDRAM device instance
0985   * @param  Command Pointer to SDRAM command structure
0986   * @param  Timing Pointer to SDRAM Timing structure
0987   * @param  Timeout Timeout wait value
0988   * @retval HAL state
0989   */
0990 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
0991                                         FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
0992 {
0993   /* Check the parameters */
0994   assert_param(IS_FMC_SDRAM_DEVICE(Device));
0995   assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
0996   assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
0997   assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
0998   assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
0999
1000   /* Set command register */
1001   MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
1002              ((Command->CommandMode) | (Command->CommandTarget) |
1003               (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
1004               ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
1005   /* Prevent unused argument(s) compilation warning */
1006   UNUSED(Timeout);
1007   return HAL_OK;
1008 }
1009
1010 /**
1011   * @brief  Program the SDRAM Memory Refresh rate.
1012   * @param  Device Pointer to SDRAM device instance
1013   * @param  RefreshRate The SDRAM refresh rate value.
1014   * @retval HAL state
1015   */
1016 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1017 {
1018   /* Check the parameters */
1019   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1020   assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1021
1022   /* Set the refresh rate in command register */
1023   MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));
1024
1025   return HAL_OK;
1026 }
1027
1028 /**
1029   * @brief  Set the Number of consecutive SDRAM Memory auto Refresh commands.
1030   * @param  Device Pointer to SDRAM device instance
1031   * @param  AutoRefreshNumber Specifies the auto Refresh number.
1032   * @retval None
1033   */
1034 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
1035                                                  uint32_t AutoRefreshNumber)
1036 {
1037   /* Check the parameters */
1038   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1039   assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1040
1041   /* Set the Auto-refresh number in command register */
1042   MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
1043
1044   return HAL_OK;
1045 }
1046
1047 /**
1048   * @brief  Returns the indicated FMC SDRAM bank mode status.
1049   * @param  Device Pointer to SDRAM device instance
1050   * @param  Bank Defines the FMC SDRAM bank. This parameter can be
1051   *                     FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1052   * @retval The FMC SDRAM bank mode status, could be on of the following values:
1053   *         FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1054   *         FMC_SDRAM_POWER_DOWN_MODE.
1055   */
1056 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1057 {
1058   uint32_t tmpreg;
1059
1060   /* Check the parameters */
1061   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1062   assert_param(IS_FMC_SDRAM_BANK(Bank));
1063
1064   /* Get the corresponding bank mode */
1065   if (Bank == FMC_SDRAM_BANK1)
1066   {
1067     tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1068   }
1069   else
1070   {
1071     tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1072   }
1073
1074   /* Return the mode status */
1075   return tmpreg;
1076 }
1077
1078 /**
1079   * @}
1080   */
1081
1082 /**
1083   * @}
1084   */
1085
1086
1087 /**
1088   * @}
1089   */
1090
1091 /**
1092   * @}
1093   */
1094
1095 #endif /* HAL_NOR_MODULE_ENABLED */
1096 /**
1097   * @}
1098   */
1099 /**
1100   * @}
1101   */