stm32h7/hal/stm32h7xx_ll_exti.c

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_ll_exti.c
0004   * @author  MCD Application Team
0005   * @brief   EXTI LL module driver.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
0019
0020 /* Includes ------------------------------------------------------------------*/
0021 #include "stm32h7xx_ll_exti.h"
0022 #ifdef  USE_FULL_ASSERT
0023 #include "stm32_assert.h"
0024 #else
0025 #define assert_param(expr) ((void)0U)
0026 #endif
0027
0028 /** @addtogroup STM32H7xx_LL_Driver
0029   * @{
0030   */
0031
0032 #if defined (EXTI)
0033
0034 /** @defgroup EXTI_LL EXTI
0035   * @ingroup RTEMSBSPsARMSTM32H7
0036   * @{
0037   */
0038
0039 /* Private types -------------------------------------------------------------*/
0040 /* Private variables ---------------------------------------------------------*/
0041 /* Private constants ---------------------------------------------------------*/
0042 /* Private macros ------------------------------------------------------------*/
0043 /** @addtogroup EXTI_LL_Private_Macros
0044   * @{
0045   */
0046
0047 #define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31)  == 0x00000000U)
0048 #define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
0049 #define IS_LL_EXTI_LINE_64_95(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_64_95) == 0x00000000U)
0050
0051 #define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
0052                                                    || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
0053                                                    || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
0054
0055
0056 #define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
0057                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
0058                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
0059                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
0060
0061 /**
0062   * @}
0063   */
0064
0065 /* Private function prototypes -----------------------------------------------*/
0066
0067 /* Exported functions --------------------------------------------------------*/
0068 /** @addtogroup EXTI_LL_Exported_Functions
0069   * @{
0070   */
0071
0072 /** @addtogroup EXTI_LL_EF_Init
0073   * @{
0074   */
0075
0076 /**
0077   * @brief  De-initialize the EXTI registers to their default reset values.
0078   * @retval An ErrorStatus enumeration value:
0079   *          - SUCCESS: EXTI registers are de-initialized
0080   *          - ERROR: not applicable
0081   */
0082 ErrorStatus LL_EXTI_DeInit(void)
0083 {
0084   /* Rising Trigger selection register set to default reset values */
0085   LL_EXTI_WriteReg(RTSR1,  0x00000000U);
0086   LL_EXTI_WriteReg(RTSR2,  0x00000000U);
0087   LL_EXTI_WriteReg(RTSR3,  0x00000000U);
0088
0089   /* Falling Trigger selection register set to default reset values */
0090   LL_EXTI_WriteReg(FTSR1,  0x00000000U);
0091   LL_EXTI_WriteReg(FTSR2,  0x00000000U);
0092   LL_EXTI_WriteReg(FTSR3,  0x00000000U);
0093
0094   /* Software interrupt event register set to default reset values */
0095   LL_EXTI_WriteReg(SWIER1, 0x00000000U);
0096   LL_EXTI_WriteReg(SWIER2, 0x00000000U);
0097   LL_EXTI_WriteReg(SWIER3, 0x00000000U);
0098
0099   /* D3 Pending register set to default reset values */
0100   LL_EXTI_WriteReg(D3PMR1, 0x00000000U);
0101   LL_EXTI_WriteReg(D3PMR2, 0x00000000U);
0102   LL_EXTI_WriteReg(D3PMR3, 0x00000000U);
0103
0104   /* D3 Pending clear selection register low to default reset values */
0105   LL_EXTI_WriteReg(D3PCR1L, 0x00000000U);
0106   LL_EXTI_WriteReg(D3PCR2L, 0x00000000U);
0107   LL_EXTI_WriteReg(D3PCR3L, 0x00000000U);
0108
0109   /* D3 Pending clear selection register high to default reset values */
0110   LL_EXTI_WriteReg(D3PCR1H, 0x00000000U);
0111   LL_EXTI_WriteReg(D3PCR2H, 0x00000000U);
0112   LL_EXTI_WriteReg(D3PCR3H, 0x00000000U);
0113
0114   /* Interrupt mask register reset */
0115   LL_EXTI_WriteReg(IMR1, 0x00000000U);
0116   LL_EXTI_WriteReg(IMR2, 0x00000000U);
0117   LL_EXTI_WriteReg(IMR3, 0x00000000U);
0118
0119   /*  Event mask register reset */
0120   LL_EXTI_WriteReg(EMR1, 0x00000000U);
0121   LL_EXTI_WriteReg(EMR2, 0x00000000U);
0122   LL_EXTI_WriteReg(EMR3, 0x00000000U);
0123
0124   /* Clear Pending requests */
0125   LL_EXTI_WriteReg(PR1, EXTI_PR1_PR_Msk);
0126   LL_EXTI_WriteReg(PR2, EXTI_PR2_PR_Msk);
0127   LL_EXTI_WriteReg(PR3, EXTI_PR3_PR_Msk);
0128
0129 #if defined(DUAL_CORE)
0130   /* Interrupt mask register set to default reset values  for Core 2 (Coretx-M4)*/
0131   LL_EXTI_WriteReg(C2IMR1, 0x00000000U);
0132   LL_EXTI_WriteReg(C2IMR2, 0x00000000U);
0133   LL_EXTI_WriteReg(C2IMR3, 0x00000000U);
0134
0135   /*  Event mask register set to default reset values */
0136   LL_EXTI_WriteReg(C2EMR1, 0x00000000U);
0137   LL_EXTI_WriteReg(C2EMR2, 0x00000000U);
0138   LL_EXTI_WriteReg(C2EMR3, 0x00000000U);
0139
0140   /* Clear Pending requests */
0141   LL_EXTI_WriteReg(C2PR1, EXTI_PR1_PR_Msk);
0142   LL_EXTI_WriteReg(C2PR2, EXTI_PR2_PR_Msk);
0143   LL_EXTI_WriteReg(C2PR3, EXTI_PR3_PR_Msk);
0144
0145 #endif /* DUAL_CORE*/
0146   return SUCCESS;
0147 }
0148
0149 /**
0150   * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
0151   * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
0152   * @retval An ErrorStatus enumeration value:
0153   *          - SUCCESS: EXTI registers are initialized
0154   *          - ERROR: not applicable
0155   */
0156 ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
0157 {
0158   ErrorStatus status = SUCCESS;
0159   /* Check the parameters */
0160   assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
0161   assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
0162   assert_param(IS_LL_EXTI_LINE_64_95(EXTI_InitStruct->Line_64_95));
0163   assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
0164   assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
0165
0166   /* ENABLE LineCommand */
0167   if (EXTI_InitStruct->LineCommand != DISABLE)
0168   {
0169     assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
0170
0171     /* Configure EXTI Lines in range from 0 to 31 */
0172     if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
0173     {
0174       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
0175       {
0176         /* Enable IT on provided Lines for Cortex-M7*/
0177         LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
0178       }
0179       else
0180       {
0181         /* Disable IT on provided Lines for Cortex-M7*/
0182         LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
0183       }
0184
0185       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
0186       {
0187         /* Enable event on provided Lines for Cortex-M7 */
0188         LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
0189       }
0190       else
0191       {
0192         /* Disable event on provided Lines for Cortex-M7 */
0193         LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
0194       }
0195 #if defined(DUAL_CORE)
0196       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
0197       {
0198         /* Enable IT on provided Lines for Cortex-M4 */
0199         LL_C2_EXTI_EnableIT_0_31 (EXTI_InitStruct->Line_0_31);
0200       }
0201       else
0202       {
0203         /* Disable IT on provided Lines for Cortex-M4*/
0204         LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
0205       }
0206
0207       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
0208       {
0209         /* Enable event on provided Lines for Cortex-M4 */
0210         LL_C2_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
0211       }
0212       else
0213       {
0214         /* Disable event on provided Lines for Cortex-M4*/
0215         LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
0216       }
0217 #endif /* DUAL_CORE */
0218
0219       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
0220       {
0221         switch (EXTI_InitStruct->Trigger)
0222         {
0223           case LL_EXTI_TRIGGER_RISING:
0224             /* First Disable Falling Trigger on provided Lines */
0225             LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
0226             /* Then Enable Rising Trigger on provided Lines */
0227             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
0228             break;
0229           case LL_EXTI_TRIGGER_FALLING:
0230             /* First Disable Rising Trigger on provided Lines */
0231             LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
0232             /* Then Enable Falling Trigger on provided Lines */
0233             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
0234             break;
0235           case LL_EXTI_TRIGGER_RISING_FALLING:
0236             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
0237             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
0238             break;
0239           default:
0240             status = ERROR;
0241             break;
0242         }
0243       }
0244     }
0245     /* Configure EXTI Lines in range from 32 to 63 */
0246     if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
0247     {
0248       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
0249       {
0250         /* Enable IT on provided Lines for Cortex-M7*/
0251         LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
0252       }
0253       else
0254       {
0255         /* Disable IT on provided Lines for Cortex-M7*/
0256         LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
0257       }
0258
0259       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
0260       {
0261         /* Enable event on provided Lines for Cortex-M7 */
0262         LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
0263       }
0264       else
0265       {
0266         /* Disable event on provided Lines for Cortex-M7 */
0267         LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
0268       }
0269 #if defined(DUAL_CORE)
0270       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
0271       {
0272         /* Enable IT on provided Lines for Cortex-M4 */
0273         LL_C2_EXTI_EnableIT_32_63 (EXTI_InitStruct->Line_32_63);
0274       }
0275       else
0276       {
0277         /* Disable IT on provided Lines for Cortex-M4 */
0278         LL_C2_EXTI_DisableIT_32_63 (EXTI_InitStruct->Line_32_63);
0279       }
0280
0281       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
0282       {
0283         /* Enable event on provided Lines for Cortex-M4 */
0284         LL_C2_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
0285       }
0286       else
0287       {
0288         /* Disable event on provided Lines for Cortex-M4 */
0289         LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
0290       }
0291 #endif /* DUAL_CORE */
0292
0293       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
0294       {
0295         switch (EXTI_InitStruct->Trigger)
0296         {
0297           case LL_EXTI_TRIGGER_RISING:
0298             /* First Disable Falling Trigger on provided Lines */
0299             LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
0300             /* Then Enable IT on provided Lines */
0301             LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
0302             break;
0303           case LL_EXTI_TRIGGER_FALLING:
0304             /* First Disable Rising Trigger on provided Lines */
0305             LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
0306             /* Then Enable Falling Trigger on provided Lines */
0307             LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
0308             break;
0309           case LL_EXTI_TRIGGER_RISING_FALLING:
0310             LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
0311             LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
0312             break;
0313           default:
0314             status = ERROR;
0315             break;
0316         }
0317       }
0318     }
0319     /* Configure EXTI Lines in range from 64 to 95 */
0320     if (EXTI_InitStruct->Line_64_95 != LL_EXTI_LINE_NONE)
0321     {
0322       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
0323       {
0324         /* Enable IT on provided Lines for Cortex-M7*/
0325         LL_EXTI_EnableIT_64_95(EXTI_InitStruct->Line_64_95);
0326       }
0327       else
0328       {
0329         /* Disable IT on provided Lines for Cortex-M7*/
0330         LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
0331       }
0332
0333       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
0334       {
0335         /* Enable event on provided Lines for Cortex-M7 */
0336         LL_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
0337       }
0338       else
0339       {
0340         /* Disable event on provided Lines for Cortex-M7 */
0341         LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
0342       }
0343
0344 #if defined(DUAL_CORE)
0345       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
0346       {
0347         /* Enable IT on provided Lines for Cortex-M4 */
0348         LL_C2_EXTI_EnableIT_64_95 (EXTI_InitStruct->Line_64_95);
0349       }
0350       else
0351       {
0352         /* Disable IT on provided Lines for Cortex-M4 */
0353         LL_C2_EXTI_DisableIT_64_95 (EXTI_InitStruct->Line_64_95);
0354       }
0355
0356       if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
0357       {
0358         /* Enable event on provided Lines for Cortex-M4 */
0359         LL_C2_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
0360       }
0361       else
0362       {
0363         /* Disable event on provided Lines for Cortex-M4 */
0364         LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
0365       }
0366 #endif /* DUAL_CORE */
0367
0368       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
0369       {
0370         switch (EXTI_InitStruct->Trigger)
0371         {
0372           case LL_EXTI_TRIGGER_RISING:
0373             /* First Disable Falling Trigger on provided Lines */
0374             LL_EXTI_DisableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
0375             /* Then Enable IT on provided Lines */
0376             LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
0377             break;
0378           case LL_EXTI_TRIGGER_FALLING:
0379             /* First Disable Rising Trigger on provided Lines */
0380             LL_EXTI_DisableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
0381             /* Then Enable Falling Trigger on provided Lines */
0382             LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
0383             break;
0384           case LL_EXTI_TRIGGER_RISING_FALLING:
0385             LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
0386             LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
0387             break;
0388           default:
0389             status = ERROR;
0390             break;
0391         }
0392       }
0393     }
0394   }
0395   else /* DISABLE LineCommand */
0396   {
0397     /* Disable IT on provided Lines for Cortex-M7*/
0398     LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
0399     LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
0400     LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
0401
0402     /* Disable event on provided Lines for Cortex-M7 */
0403     LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
0404     LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
0405     LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
0406
0407 #if defined(DUAL_CORE)
0408     /* Disable IT on provided Lines for Cortex-M4*/
0409     LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
0410     LL_C2_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
0411     LL_C2_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
0412
0413     /* Disable event on provided Lines for Cortex-M4 */
0414     LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
0415     LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
0416     LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
0417 #endif /* DUAL_CORE */
0418   }
0419
0420   return status;
0421 }
0422
0423 /**
0424   * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
0425   * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
0426   * @retval None
0427   */
0428 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
0429 {
0430   EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
0431   EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;
0432   EXTI_InitStruct->Line_64_95     = LL_EXTI_LINE_NONE;
0433   EXTI_InitStruct->LineCommand    = DISABLE;
0434   EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
0435   EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
0436 }
0437
0438 /**
0439   * @}
0440   */
0441
0442 /**
0443   * @}
0444   */
0445
0446 /**
0447   * @}
0448   */
0449
0450 #endif /* defined (EXTI) */
0451
0452 /**
0453   * @}
0454   */
0455
0456 #endif /* USE_FULL_LL_DRIVER */
0457