stm32h7/hal/stm32h7xx_ll_dma.c

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_ll_dma.c
0004   * @author  MCD Application Team
0005   * @brief   DMA LL module driver.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
0019
0020 /* Includes ------------------------------------------------------------------*/
0021 #include "stm32h7xx_ll_dma.h"
0022 #include "stm32h7xx_ll_bus.h"
0023 #ifdef  USE_FULL_ASSERT
0024 #include "stm32_assert.h"
0025 #else
0026 #define assert_param(expr) ((void)0U)
0027 #endif
0028
0029 /** @addtogroup STM32H7xx_LL_Driver
0030   * @{
0031   */
0032
0033 #if defined (DMA1) || defined (DMA2)
0034
0035 /** @addtogroup DMA_LL
0036   * @{
0037   */
0038
0039 /* Private types -------------------------------------------------------------*/
0040 /* Private variables ---------------------------------------------------------*/
0041 /* Private constants ---------------------------------------------------------*/
0042 /* Private macros ------------------------------------------------------------*/
0043 /** @addtogroup DMA_LL_Private_Macros
0044   * @{
0045   */
0046 #define IS_LL_DMA_DIRECTION(__VALUE__)                     (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
0047                                                             ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
0048                                                             ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
0049
0050 #define IS_LL_DMA_MODE(__VALUE__)                          (((__VALUE__) == LL_DMA_MODE_NORMAL)    || \
0051                                                             ((__VALUE__) == LL_DMA_MODE_CIRCULAR)  || \
0052                                                             ((__VALUE__) == LL_DMA_MODE_PFCTRL))
0053
0054 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__)                 (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
0055                                                             ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
0056
0057 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__)                 (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
0058                                                             ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
0059
0060 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)                (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
0061                                                             ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
0062                                                             ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
0063
0064 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)                (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
0065                                                             ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
0066                                                             ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
0067
0068 #define IS_LL_DMA_NBDATA(__VALUE__)                        ((__VALUE__)  <= 0x0000FFFFU)
0069
0070 #if defined(TIM24)
0071 #define IS_LL_DMA_REQUEST(REQUEST)                         (((REQUEST)   <= LL_DMAMUX1_REQ_TIM24_TRIG))
0072 #elif defined(ADC3)
0073 #define IS_LL_DMA_REQUEST(REQUEST)                         (((REQUEST)   <= LL_DMAMUX1_REQ_ADC3))
0074 #else
0075 #define IS_LL_DMA_REQUEST(REQUEST)                         (((REQUEST)   <= LL_DMAMUX1_REQ_USART10_TX))
0076 #endif /* TIM24 */
0077
0078 #define IS_LL_DMA_PRIORITY(__VALUE__)                      (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
0079                                                             ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
0080                                                             ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
0081                                                             ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
0082
0083 #define IS_LL_DMA_DOUBLEBUFFER_MODE(__VALUE__)             (((__VALUE__) == LL_DMA_DOUBLEBUFFER_MODE_DISABLE) || \
0084                                                             ((__VALUE__) == LL_DMA_DOUBLEBUFFER_MODE_ENABLE))
0085
0086 #define IS_LL_DMA_DOUBLEBUFFER_TARGETMEM(__VALUE__)        (((__VALUE__) == LL_DMA_CURRENTTARGETMEM0)    || \
0087                                                             ((__VALUE__) == LL_DMA_CURRENTTARGETMEM1))
0088
0089 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM)   ((((INSTANCE) == DMA1) && \
0090                                                            (((STREAM) == LL_DMA_STREAM_0)     || \
0091                                                             ((STREAM) == LL_DMA_STREAM_1)     || \
0092                                                             ((STREAM) == LL_DMA_STREAM_2)     || \
0093                                                             ((STREAM) == LL_DMA_STREAM_3)     || \
0094                                                             ((STREAM) == LL_DMA_STREAM_4)     || \
0095                                                             ((STREAM) == LL_DMA_STREAM_5)     || \
0096                                                             ((STREAM) == LL_DMA_STREAM_6)     || \
0097                                                             ((STREAM) == LL_DMA_STREAM_7)     || \
0098                                                             ((STREAM) == LL_DMA_STREAM_ALL))) || \
0099                                                            (((INSTANCE) == DMA2) && \
0100                                                            (((STREAM) == LL_DMA_STREAM_0)     || \
0101                                                             ((STREAM) == LL_DMA_STREAM_1)     || \
0102                                                             ((STREAM) == LL_DMA_STREAM_2)     || \
0103                                                             ((STREAM) == LL_DMA_STREAM_3)     || \
0104                                                             ((STREAM) == LL_DMA_STREAM_4)     || \
0105                                                             ((STREAM) == LL_DMA_STREAM_5)     || \
0106                                                             ((STREAM) == LL_DMA_STREAM_6)     || \
0107                                                             ((STREAM) == LL_DMA_STREAM_7)     || \
0108                                                             ((STREAM) == LL_DMA_STREAM_ALL))))
0109
0110 #define IS_LL_DMA_FIFO_MODE_STATE(STATE)                   (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
0111                                                             ((STATE) == LL_DMA_FIFOMODE_ENABLE))
0112
0113 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD)                (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4)  || \
0114                                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2)  || \
0115                                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4)  || \
0116                                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
0117
0118 #define IS_LL_DMA_MEMORY_BURST(BURST)                      (((BURST) == LL_DMA_MBURST_SINGLE) || \
0119                                                             ((BURST) == LL_DMA_MBURST_INC4)   || \
0120                                                             ((BURST) == LL_DMA_MBURST_INC8)   || \
0121                                                             ((BURST) == LL_DMA_MBURST_INC16))
0122
0123 #define IS_LL_DMA_PERIPHERAL_BURST(BURST)                  (((BURST) == LL_DMA_PBURST_SINGLE) || \
0124                                                             ((BURST) == LL_DMA_PBURST_INC4)   || \
0125                                                             ((BURST) == LL_DMA_PBURST_INC8)   || \
0126                                                             ((BURST) == LL_DMA_PBURST_INC16))
0127
0128 /**
0129   * @}
0130   */
0131
0132 /* Private function prototypes -----------------------------------------------*/
0133
0134 /* Exported functions --------------------------------------------------------*/
0135 /** @addtogroup DMA_LL_Exported_Functions
0136   * @{
0137   */
0138
0139 /** @addtogroup DMA_LL_EF_Init
0140   * @{
0141   */
0142
0143 /**
0144   * @brief  De-initialize the DMA registers to their default reset values.
0145   * @param  DMAx DMAx Instance
0146   * @param  Stream This parameter can be one of the following values:
0147   *         @arg @ref LL_DMA_STREAM_0
0148   *         @arg @ref LL_DMA_STREAM_1
0149   *         @arg @ref LL_DMA_STREAM_2
0150   *         @arg @ref LL_DMA_STREAM_3
0151   *         @arg @ref LL_DMA_STREAM_4
0152   *         @arg @ref LL_DMA_STREAM_5
0153   *         @arg @ref LL_DMA_STREAM_6
0154   *         @arg @ref LL_DMA_STREAM_7
0155   *         @arg @ref LL_DMA_STREAM_ALL
0156   * @retval An ErrorStatus enumeration value:
0157   *          - SUCCESS: DMA registers are de-initialized
0158   *          - ERROR: DMA registers are not de-initialized
0159   */
0160 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
0161 {
0162   DMA_Stream_TypeDef *tmp;
0163   ErrorStatus status = SUCCESS;
0164
0165   /* Check the DMA Instance DMAx and Stream parameters */
0166   assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
0167
0168   if (Stream == LL_DMA_STREAM_ALL)
0169   {
0170     if (DMAx == DMA1)
0171     {
0172       /* Force reset of DMA clock */
0173       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
0174
0175       /* Release reset of DMA clock */
0176       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
0177     }
0178     else if (DMAx == DMA2)
0179     {
0180       /* Force reset of DMA clock */
0181        LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
0182
0183       /* Release reset of DMA clock */
0184       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
0185     }
0186     else
0187     {
0188       status = ERROR;
0189     }
0190   }
0191   else
0192   {
0193     /* Disable the selected Stream */
0194     LL_DMA_DisableStream(DMAx, Stream);
0195
0196     /* Get the DMA Stream Instance */
0197     tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
0198
0199     /* Reset DMAx_Streamy configuration register */
0200     LL_DMA_WriteReg(tmp, CR, 0U);
0201
0202     /* Reset DMAx_Streamy remaining bytes register */
0203     LL_DMA_WriteReg(tmp, NDTR, 0U);
0204
0205     /* Reset DMAx_Streamy peripheral address register */
0206     LL_DMA_WriteReg(tmp, PAR, 0U);
0207
0208     /* Reset DMAx_Streamy memory address register */
0209     LL_DMA_WriteReg(tmp, M0AR, 0U);
0210
0211     /* Reset DMAx_Streamy memory address register */
0212     LL_DMA_WriteReg(tmp, M1AR, 0U);
0213
0214     /* Reset DMAx_Streamy FIFO control register */
0215     LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
0216
0217     /* Reset Channel register field for DMAx Stream */
0218     LL_DMA_SetPeriphRequest(DMAx, Stream, LL_DMAMUX1_REQ_MEM2MEM);
0219
0220     if (Stream == LL_DMA_STREAM_0)
0221     {
0222       /* Reset the Stream0 pending flags */
0223       DMAx->LIFCR = 0x0000003FU;
0224     }
0225     else if (Stream == LL_DMA_STREAM_1)
0226     {
0227       /* Reset the Stream1 pending flags */
0228       DMAx->LIFCR = 0x00000F40U;
0229     }
0230     else if (Stream == LL_DMA_STREAM_2)
0231     {
0232       /* Reset the Stream2 pending flags */
0233       DMAx->LIFCR = 0x003F0000U;
0234     }
0235     else if (Stream == LL_DMA_STREAM_3)
0236     {
0237       /* Reset the Stream3 pending flags */
0238       DMAx->LIFCR = 0x0F400000U;
0239     }
0240     else if (Stream == LL_DMA_STREAM_4)
0241     {
0242       /* Reset the Stream4 pending flags */
0243       DMAx->HIFCR = 0x0000003FU;
0244     }
0245     else if (Stream == LL_DMA_STREAM_5)
0246     {
0247       /* Reset the Stream5 pending flags */
0248       DMAx->HIFCR = 0x00000F40U;
0249     }
0250     else if (Stream == LL_DMA_STREAM_6)
0251     {
0252       /* Reset the Stream6 pending flags */
0253       DMAx->HIFCR = 0x003F0000U;
0254     }
0255     else if (Stream == LL_DMA_STREAM_7)
0256     {
0257       /* Reset the Stream7 pending flags */
0258       DMAx->HIFCR = 0x0F400000U;
0259     }
0260     else
0261     {
0262       status = ERROR;
0263     }
0264   }
0265
0266   return (uint32_t)status;
0267 }
0268
0269 /**
0270   * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
0271   * @note   To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
0272   *         @arg @ref __LL_DMA_GET_INSTANCE
0273   *         @arg @ref __LL_DMA_GET_STREAM
0274   * @param  DMAx DMAx Instance
0275   * @param  Stream This parameter can be one of the following values:
0276   *         @arg @ref LL_DMA_STREAM_0
0277   *         @arg @ref LL_DMA_STREAM_1
0278   *         @arg @ref LL_DMA_STREAM_2
0279   *         @arg @ref LL_DMA_STREAM_3
0280   *         @arg @ref LL_DMA_STREAM_4
0281   *         @arg @ref LL_DMA_STREAM_5
0282   *         @arg @ref LL_DMA_STREAM_6
0283   *         @arg @ref LL_DMA_STREAM_7
0284   * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
0285   * @retval An ErrorStatus enumeration value:
0286   *          - SUCCESS: DMA registers are initialized
0287   *          - ERROR: Not applicable
0288   */
0289 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
0290 {
0291   /* Check the DMA Instance DMAx and Stream parameters */
0292   assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
0293
0294   /* Check the DMA parameters from DMA_InitStruct */
0295   assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
0296   assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
0297   assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
0298   assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
0299   assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
0300   assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
0301   assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
0302   assert_param(IS_LL_DMA_REQUEST(DMA_InitStruct->PeriphRequest));
0303   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
0304   assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
0305   assert_param(IS_LL_DMA_DOUBLEBUFFER_MODE(DMA_InitStruct->DoubleBufferMode));
0306   assert_param(IS_LL_DMA_DOUBLEBUFFER_TARGETMEM(DMA_InitStruct->TargetMemInDoubleBufferMode));
0307
0308   /* Check the memory burst, peripheral burst and FIFO threshold parameters only
0309      when FIFO mode is enabled */
0310   if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
0311   {
0312     assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
0313     assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
0314     assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
0315   }
0316
0317   /*---------------------------- DMAx SxCR Configuration ------------------------
0318    * Configure DMAx_Streamy: data transfer direction, data transfer mode,
0319    *                          peripheral and memory increment mode,
0320    *                          data size alignment and  priority level with parameters :
0321    * - Direction:                   DMA_SxCR_DIR[1:0] bits
0322    * - Mode:                        DMA_SxCR_CIRC bit
0323    * - PeriphOrM2MSrcIncMode:       DMA_SxCR_PINC bit
0324    * - MemoryOrM2MDstIncMode:       DMA_SxCR_MINC bit
0325    * - PeriphOrM2MSrcDataSize:      DMA_SxCR_PSIZE[1:0] bits
0326    * - MemoryOrM2MDstDataSize:      DMA_SxCR_MSIZE[1:0] bits
0327    * - Priority:                    DMA_SxCR_PL[1:0] bits
0328    * - DoubleBufferMode:            DMA_SxCR_DBM bit
0329    * - TargetMemInDoubleBufferMode: DMA_SxCR_CT bit
0330    */
0331   LL_DMA_ConfigTransfer(DMAx, Stream,
0332                         DMA_InitStruct->Direction               | \
0333                         DMA_InitStruct->Mode                    | \
0334                         DMA_InitStruct->PeriphOrM2MSrcIncMode   | \
0335                         DMA_InitStruct->MemoryOrM2MDstIncMode   | \
0336                         DMA_InitStruct->PeriphOrM2MSrcDataSize  | \
0337                         DMA_InitStruct->MemoryOrM2MDstDataSize  | \
0338                         DMA_InitStruct->Priority                | \
0339                         DMA_InitStruct->DoubleBufferMode        | \
0340                         DMA_InitStruct->TargetMemInDoubleBufferMode);
0341
0342   if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
0343   {
0344     /*---------------------------- DMAx SxFCR Configuration ------------------------
0345      * Configure DMAx_Streamy:  fifo mode and fifo threshold with parameters :
0346      * - FIFOMode:                DMA_SxFCR_DMDIS bit
0347      * - FIFOThreshold:           DMA_SxFCR_FTH[1:0] bits
0348      */
0349     LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
0350
0351     /*---------------------------- DMAx SxCR Configuration --------------------------
0352      * Configure DMAx_Streamy:  memory burst transfer with parameters :
0353      * - MemBurst:                DMA_SxCR_MBURST[1:0] bits
0354      */
0355     LL_DMA_SetMemoryBurstxfer(DMAx, Stream, DMA_InitStruct->MemBurst);
0356
0357     /*---------------------------- DMAx SxCR Configuration --------------------------
0358      * Configure DMAx_Streamy:  peripheral burst transfer with parameters :
0359      * - PeriphBurst:             DMA_SxCR_PBURST[1:0] bits
0360      */
0361     LL_DMA_SetPeriphBurstxfer(DMAx, Stream, DMA_InitStruct->PeriphBurst);
0362   }
0363
0364   /*-------------------------- DMAx SxM0AR Configuration --------------------------
0365    * Configure the memory or destination base address with parameter :
0366    * - MemoryOrM2MDstAddress:     DMA_SxM0AR_M0A[31:0] bits
0367    */
0368   LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
0369
0370   /*-------------------------- DMAx SxPAR Configuration ---------------------------
0371    * Configure the peripheral or source base address with parameter :
0372    * - PeriphOrM2MSrcAddress:     DMA_SxPAR_PA[31:0] bits
0373    */
0374   LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
0375
0376   /*--------------------------- DMAx SxNDTR Configuration -------------------------
0377    * Configure the peripheral base address with parameter :
0378    * - NbData:                    DMA_SxNDT[15:0] bits
0379    */
0380   LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
0381
0382   /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
0383    * Configure the peripheral base address with parameter :
0384    * - PeriphRequest:             DMA_SxCR_CHSEL[3:0] bits
0385    */
0386   LL_DMA_SetPeriphRequest(DMAx, Stream, DMA_InitStruct->PeriphRequest);
0387
0388   return (uint32_t)SUCCESS;
0389 }
0390
0391 /**
0392   * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
0393   * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
0394   * @retval None
0395   */
0396 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
0397 {
0398   /* Set DMA_InitStruct fields to default values */
0399   DMA_InitStruct->PeriphOrM2MSrcAddress       = 0x00000000U;
0400   DMA_InitStruct->MemoryOrM2MDstAddress       = 0x00000000U;
0401   DMA_InitStruct->Direction                   = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
0402   DMA_InitStruct->Mode                        = LL_DMA_MODE_NORMAL;
0403   DMA_InitStruct->PeriphOrM2MSrcIncMode       = LL_DMA_PERIPH_NOINCREMENT;
0404   DMA_InitStruct->MemoryOrM2MDstIncMode       = LL_DMA_MEMORY_NOINCREMENT;
0405   DMA_InitStruct->PeriphOrM2MSrcDataSize      = LL_DMA_PDATAALIGN_BYTE;
0406   DMA_InitStruct->MemoryOrM2MDstDataSize      = LL_DMA_MDATAALIGN_BYTE;
0407   DMA_InitStruct->NbData                      = 0x00000000U;
0408   DMA_InitStruct->PeriphRequest               = LL_DMAMUX1_REQ_MEM2MEM;
0409   DMA_InitStruct->Priority                    = LL_DMA_PRIORITY_LOW;
0410   DMA_InitStruct->FIFOMode                    = LL_DMA_FIFOMODE_DISABLE;
0411   DMA_InitStruct->FIFOThreshold               = LL_DMA_FIFOTHRESHOLD_1_4;
0412   DMA_InitStruct->MemBurst                    = LL_DMA_MBURST_SINGLE;
0413   DMA_InitStruct->PeriphBurst                 = LL_DMA_PBURST_SINGLE;
0414   DMA_InitStruct->DoubleBufferMode            = LL_DMA_DOUBLEBUFFER_MODE_DISABLE;
0415   DMA_InitStruct->TargetMemInDoubleBufferMode = LL_DMA_CURRENTTARGETMEM0;
0416 }
0417
0418 /**
0419   * @}
0420   */
0421
0422 /**
0423   * @}
0424   */
0425
0426 /**
0427   * @}
0428   */
0429
0430 #endif /* DMA1 || DMA2 */
0431
0432 /**
0433   * @}
0434   */
0435
0436 #endif /* USE_FULL_LL_DRIVER */
0437