stm32h7/hal/stm32h7xx_ll_bdma.c

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_ll_bdma.c
0004   * @author  MCD Application Team
0005   * @brief   BDMA LL module driver.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018
0019 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
0020
0021 /* Includes ------------------------------------------------------------------*/
0022 #include "stm32h7xx_ll_bdma.h"
0023 #include "stm32h7xx_ll_bus.h"
0024 #ifdef  USE_FULL_ASSERT
0025 #include "stm32_assert.h"
0026 #else
0027 #define assert_param(expr) ((void)0U)
0028 #endif
0029
0030 /** @addtogroup STM32H7xx_LL_Driver
0031   * @{
0032   */
0033
0034 #if defined (BDMA) || defined (BDMA1) || defined (BDMA2)
0035
0036 /** @addtogroup BDMA_LL
0037   * @{
0038   */
0039
0040 /* Private types -------------------------------------------------------------*/
0041 /* Private variables ---------------------------------------------------------*/
0042 /* Private constants ---------------------------------------------------------*/
0043 /* Private macros ------------------------------------------------------------*/
0044 /** @addtogroup BDMA_LL_Private_Macros
0045   * @{
0046   */
0047 #define IS_LL_BDMA_DIRECTION(__VALUE__)                      (((__VALUE__) == LL_BDMA_DIRECTION_PERIPH_TO_MEMORY) || \
0048                                                               ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) || \
0049                                                               ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_MEMORY))
0050
0051 #define IS_LL_BDMA_MODE(__VALUE__)                           (((__VALUE__) == LL_BDMA_MODE_NORMAL) || \
0052                                                               ((__VALUE__) == LL_BDMA_MODE_CIRCULAR))
0053
0054 #define IS_LL_BDMA_PERIPHINCMODE(__VALUE__)                  (((__VALUE__) == LL_BDMA_PERIPH_INCREMENT) || \
0055                                                               ((__VALUE__) == LL_BDMA_PERIPH_NOINCREMENT))
0056
0057 #define IS_LL_BDMA_MEMORYINCMODE(__VALUE__)                  (((__VALUE__) == LL_BDMA_MEMORY_INCREMENT) || \
0058                                                               ((__VALUE__) == LL_BDMA_MEMORY_NOINCREMENT))
0059
0060 #define IS_LL_BDMA_PERIPHDATASIZE(__VALUE__)                 (((__VALUE__) == LL_BDMA_PDATAALIGN_BYTE)      || \
0061                                                               ((__VALUE__) == LL_BDMA_PDATAALIGN_HALFWORD)  || \
0062                                                               ((__VALUE__) == LL_BDMA_PDATAALIGN_WORD))
0063
0064 #define IS_LL_BDMA_MEMORYDATASIZE(__VALUE__)                 (((__VALUE__) == LL_BDMA_MDATAALIGN_BYTE)      || \
0065                                                               ((__VALUE__) == LL_BDMA_MDATAALIGN_HALFWORD)  || \
0066                                                               ((__VALUE__) == LL_BDMA_MDATAALIGN_WORD))
0067
0068 #define IS_LL_BDMA_NBDATA(__VALUE__)                        ((__VALUE__)  <= 0x0000FFFFU)
0069
0070 #if defined(ADC3)
0071 #define IS_LL_BDMA_PERIPHREQUEST(__VALUE__)                 ((__VALUE__) <= LL_DMAMUX2_REQ_ADC3)
0072 #else
0073 #define IS_LL_BDMA_PERIPHREQUEST(__VALUE__)                 ((__VALUE__) <= LL_DMAMUX2_REQ_DFSDM2_FLT0)
0074 #endif /* ADC3 */
0075
0076 #define IS_LL_BDMA_PRIORITY(__VALUE__)                       (((__VALUE__) == LL_BDMA_PRIORITY_LOW)    || \
0077                                                               ((__VALUE__) == LL_BDMA_PRIORITY_MEDIUM) || \
0078                                                               ((__VALUE__) == LL_BDMA_PRIORITY_HIGH)   || \
0079                                                               ((__VALUE__) == LL_BDMA_PRIORITY_VERYHIGH))
0080
0081 #define IS_LL_BDMA_DOUBLEBUFFER_MODE(__VALUE__)              (((__VALUE__) == LL_BDMA_DOUBLEBUFFER_MODE_DISABLE) || \
0082                                                               ((__VALUE__) == LL_BDMA_DOUBLEBUFFER_MODE_ENABLE))
0083
0084 #define IS_LL_BDMA_DOUBLEBUFFER_TARGETMEM(__VALUE__)         (((__VALUE__) == LL_BDMA_CURRENTTARGETMEM0)    || \
0085                                                               ((__VALUE__) == LL_BDMA_CURRENTTARGETMEM1))
0086
0087 #define IS_LL_BDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == BDMA) && \
0088                                                              (((CHANNEL) == LL_BDMA_CHANNEL_0) || \
0089                                                               ((CHANNEL) == LL_BDMA_CHANNEL_1) || \
0090                                                               ((CHANNEL) == LL_BDMA_CHANNEL_2) || \
0091                                                               ((CHANNEL) == LL_BDMA_CHANNEL_3) || \
0092                                                               ((CHANNEL) == LL_BDMA_CHANNEL_4) || \
0093                                                               ((CHANNEL) == LL_BDMA_CHANNEL_5) || \
0094                                                               ((CHANNEL) == LL_BDMA_CHANNEL_6) || \
0095                                                               ((CHANNEL) == LL_BDMA_CHANNEL_7))))
0096
0097 /**
0098   * @}
0099   */
0100
0101 /* Private function prototypes -----------------------------------------------*/
0102
0103 /* Exported functions --------------------------------------------------------*/
0104 /** @addtogroup BDMA_LL_Exported_Functions
0105   * @{
0106   */
0107
0108 /** @addtogroup BDMA_LL_EF_Init
0109   * @{
0110   */
0111
0112 /**
0113   * @brief  De-initialize the DMA registers to their default reset values.
0114   * @param  BDMAx BDMAx Instance
0115   * @param  Channel This parameter can be one of the following values:
0116   *         @arg @ref LL_BDMA_CHANNEL_0
0117   *         @arg @ref LL_BDMA_CHANNEL_1
0118   *         @arg @ref LL_BDMA_CHANNEL_2
0119   *         @arg @ref LL_BDMA_CHANNEL_3
0120   *         @arg @ref LL_BDMA_CHANNEL_4
0121   *         @arg @ref LL_BDMA_CHANNEL_5
0122   *         @arg @ref LL_BDMA_CHANNEL_6
0123   *         @arg @ref LL_BDMA_CHANNEL_7
0124   *         @arg @ref LL_BDMA_CHANNEL_ALL
0125   * @retval An ErrorStatus enumeration value:
0126   *          - SUCCESS: DMA registers are de-initialized
0127   *          - ERROR: DMA registers are not de-initialized
0128   */
0129 uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel)
0130 {
0131   BDMA_Channel_TypeDef *tmp ;
0132   ErrorStatus status = SUCCESS;
0133
0134   /* Check the DMA Instance DMAx and Channel parameters */
0135   assert_param(IS_LL_BDMA_ALL_CHANNEL_INSTANCE(BDMAx, Channel) || (Channel == LL_BDMA_CHANNEL_ALL));
0136
0137   if (Channel == LL_BDMA_CHANNEL_ALL)
0138   {
0139     if (BDMAx == BDMA)
0140     {
0141       /* Force reset of BDMA clock */
0142       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
0143
0144       /* Release reset of BDMA clock */
0145       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
0146     }
0147     else
0148     {
0149       status = ERROR;
0150     }
0151   }
0152   else
0153   {
0154     tmp = (BDMA_Channel_TypeDef *)(__LL_BDMA_GET_CHANNEL_INSTANCE(BDMAx, Channel));
0155
0156     /* Disable the selected DMAx_Channely */
0157     CLEAR_BIT(tmp->CCR, BDMA_CCR_EN);
0158
0159     /* Reset DMAx_Channely control register */
0160     LL_BDMA_WriteReg(tmp, CCR, 0U);
0161
0162     /* Reset DMAx_Channely remaining bytes register */
0163     LL_BDMA_WriteReg(tmp, CNDTR, 0U);
0164
0165     /* Reset DMAx_Channely peripheral address register */
0166     LL_BDMA_WriteReg(tmp, CPAR, 0U);
0167
0168     /* Reset DMAx_Channely memory 0 address register */
0169     LL_BDMA_WriteReg(tmp, CM0AR, 0U);
0170
0171     /* Reset DMAx_Channely memory 1 address register */
0172     LL_BDMA_WriteReg(tmp, CM1AR, 0U);
0173
0174     /* Reset Request register field for BDMAx Channel */
0175     LL_BDMA_SetPeriphRequest(BDMAx, Channel, LL_DMAMUX2_REQ_MEM2MEM);
0176
0177     if (Channel == LL_BDMA_CHANNEL_0)
0178     {
0179       /* Reset interrupt pending bits for DMAx Channel0 */
0180       LL_BDMA_ClearFlag_GI0(BDMAx);
0181     }
0182     else if (Channel == LL_BDMA_CHANNEL_1)
0183     {
0184       /* Reset interrupt pending bits for DMAx Channel1 */
0185       LL_BDMA_ClearFlag_GI1(BDMAx);
0186     }
0187     else if (Channel == LL_BDMA_CHANNEL_2)
0188     {
0189       /* Reset interrupt pending bits for DMAx Channel2 */
0190       LL_BDMA_ClearFlag_GI2(BDMAx);
0191     }
0192     else if (Channel == LL_BDMA_CHANNEL_3)
0193     {
0194       /* Reset interrupt pending bits for DMAx Channel3 */
0195       LL_BDMA_ClearFlag_GI3(BDMAx);
0196     }
0197     else if (Channel == LL_BDMA_CHANNEL_4)
0198     {
0199       /* Reset interrupt pending bits for DMAx Channel4 */
0200       LL_BDMA_ClearFlag_GI4(BDMAx);
0201     }
0202     else if (Channel == LL_BDMA_CHANNEL_5)
0203     {
0204       /* Reset interrupt pending bits for DMAx Channel5 */
0205       LL_BDMA_ClearFlag_GI5(BDMAx);
0206     }
0207
0208     else if (Channel == LL_BDMA_CHANNEL_6)
0209     {
0210       /* Reset interrupt pending bits for DMAx Channel6 */
0211       LL_BDMA_ClearFlag_GI6(BDMAx);
0212     }
0213     else if (Channel == LL_BDMA_CHANNEL_7)
0214     {
0215       /* Reset interrupt pending bits for DMAx Channel7 */
0216       LL_BDMA_ClearFlag_GI7(BDMAx);
0217     }
0218     else
0219     {
0220       status = ERROR;
0221     }
0222   }
0223
0224   return (uint32_t)status;
0225 }
0226
0227 /**
0228   * @brief  Initialize the BDMA registers according to the specified parameters in BDMA_InitStruct.
0229   * @note   To convert BDMAx_Channely Instance to BDMAx Instance and Channely, use helper macros :
0230   *         @arg @ref __LL_BDMA_GET_INSTANCE
0231   *         @arg @ref __LL_BDMA_GET_CHANNEL
0232   * @param  BDMAx BDMAx Instance
0233   * @param  Channel This parameter can be one of the following values:
0234   *         @arg @ref LL_BDMA_CHANNEL_0
0235   *         @arg @ref LL_BDMA_CHANNEL_1
0236   *         @arg @ref LL_BDMA_CHANNEL_2
0237   *         @arg @ref LL_BDMA_CHANNEL_3
0238   *         @arg @ref LL_BDMA_CHANNEL_4
0239   *         @arg @ref LL_BDMA_CHANNEL_5
0240   *         @arg @ref LL_BDMA_CHANNEL_6
0241   *         @arg @ref LL_BDMA_CHANNEL_7
0242   * @param  BDMA_InitStruct pointer to a @ref LL_BDMA_InitTypeDef structure.
0243   * @retval An ErrorStatus enumeration value:
0244   *          - SUCCESS: DMA registers are initialized
0245   *          - ERROR: Not applicable
0246   */
0247 uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct)
0248 {
0249   /* Check the DMA Instance DMAx and Channel parameters */
0250   assert_param(IS_LL_BDMA_ALL_CHANNEL_INSTANCE(BDMAx, Channel));
0251
0252   /* Check the DMA parameters from BDMA_InitStruct */
0253   assert_param(IS_LL_BDMA_DIRECTION(BDMA_InitStruct->Direction));
0254   assert_param(IS_LL_BDMA_MODE(BDMA_InitStruct->Mode));
0255   assert_param(IS_LL_BDMA_PERIPHINCMODE(BDMA_InitStruct->PeriphOrM2MSrcIncMode));
0256   assert_param(IS_LL_BDMA_MEMORYINCMODE(BDMA_InitStruct->MemoryOrM2MDstIncMode));
0257   assert_param(IS_LL_BDMA_PERIPHDATASIZE(BDMA_InitStruct->PeriphOrM2MSrcDataSize));
0258   assert_param(IS_LL_BDMA_MEMORYDATASIZE(BDMA_InitStruct->MemoryOrM2MDstDataSize));
0259   assert_param(IS_LL_BDMA_NBDATA(BDMA_InitStruct->NbData));
0260   assert_param(IS_LL_BDMA_PERIPHREQUEST(BDMA_InitStruct->PeriphRequest));
0261   assert_param(IS_LL_BDMA_PRIORITY(BDMA_InitStruct->Priority));
0262   assert_param(IS_LL_BDMA_DOUBLEBUFFER_MODE(BDMA_InitStruct->DoubleBufferMode));
0263   assert_param(IS_LL_BDMA_DOUBLEBUFFER_TARGETMEM(BDMA_InitStruct->TargetMemInDoubleBufferMode));
0264
0265   /*---------------------------- DMAx CCR Configuration ------------------------
0266    * Configure DMAx_Channely: data transfer direction, data transfer mode,
0267    *                          peripheral and memory increment mode,
0268    *                          data size alignment and  priority level with parameters :
0269    * - Direction:                   BDMA_CCR_DIR and BDMA_CCR_MEM2MEM bits
0270    * - Mode:                        BDMA_CCR_CIRC bit
0271    * - PeriphOrM2MSrcIncMode:       BDMA_CCR_PINC bit
0272    * - MemoryOrM2MDstIncMode:       BDMA_CCR_MINC bit
0273    * - PeriphOrM2MSrcDataSize:      BDMA_CCR_PSIZE[1:0] bits
0274    * - MemoryOrM2MDstDataSize:      BDMA_CCR_MSIZE[1:0] bits
0275    * - Priority:                    BDMA_CCR_PL[1:0] bits
0276    * - DoubleBufferMode:            BDMA_CCR_DBM bit
0277    * - TargetMemInDoubleBufferMode: BDMA_CCR_CT bit
0278    */
0279   LL_BDMA_ConfigTransfer(BDMAx, Channel,
0280                          BDMA_InitStruct->Direction              | \
0281                          BDMA_InitStruct->Mode                   | \
0282                          BDMA_InitStruct->PeriphOrM2MSrcIncMode  | \
0283                          BDMA_InitStruct->MemoryOrM2MDstIncMode  | \
0284                          BDMA_InitStruct->PeriphOrM2MSrcDataSize | \
0285                          BDMA_InitStruct->MemoryOrM2MDstDataSize | \
0286                          BDMA_InitStruct->Priority               | \
0287                          BDMA_InitStruct->DoubleBufferMode       | \
0288                          BDMA_InitStruct->TargetMemInDoubleBufferMode);
0289
0290   /*-------------------------- DMAx CMAR Configuration -------------------------
0291    * Configure the memory or destination base address with parameter :
0292    * - MemoryOrM2MDstAddress: BDMA_CMAR_MA[31:0] bits
0293    */
0294   LL_BDMA_SetMemoryAddress(BDMAx, Channel, BDMA_InitStruct->MemoryOrM2MDstAddress);
0295
0296   /*-------------------------- DMAx CPAR Configuration -------------------------
0297    * Configure the peripheral or source base address with parameter :
0298    * - PeriphOrM2MSrcAddress: BDMA_CPAR_PA[31:0] bits
0299    */
0300   LL_BDMA_SetPeriphAddress(BDMAx, Channel, BDMA_InitStruct->PeriphOrM2MSrcAddress);
0301
0302   /*--------------------------- DMAx CNDTR Configuration -----------------------
0303    * Configure the peripheral base address with parameter :
0304    * - NbData: BDMA_CNDTR_NDT[15:0] bits
0305    */
0306   LL_BDMA_SetDataLength(BDMAx, Channel, BDMA_InitStruct->NbData);
0307
0308   /*--------------------------- DMAMUXx CCR Configuration ----------------------
0309    * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
0310    * - PeriphRequest: BDMA_CxCR[7:0] bits
0311    */
0312   LL_BDMA_SetPeriphRequest(BDMAx, Channel, BDMA_InitStruct->PeriphRequest);
0313
0314   return (uint32_t)SUCCESS;
0315 }
0316
0317 /**
0318   * @brief  Set each @ref LL_BDMA_InitTypeDef field to default value.
0319   * @param  BDMA_InitStruct Pointer to a @ref LL_BDMA_InitTypeDef structure.
0320   * @retval None
0321   */
0322 void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct)
0323 {
0324   /* Set BDMA_InitStruct fields to default values */
0325   BDMA_InitStruct->PeriphOrM2MSrcAddress       = 0x00000000U;
0326   BDMA_InitStruct->MemoryOrM2MDstAddress       = 0x00000000U;
0327   BDMA_InitStruct->Direction                   = LL_BDMA_DIRECTION_PERIPH_TO_MEMORY;
0328   BDMA_InitStruct->Mode                        = LL_BDMA_MODE_NORMAL;
0329   BDMA_InitStruct->PeriphOrM2MSrcIncMode       = LL_BDMA_PERIPH_NOINCREMENT;
0330   BDMA_InitStruct->MemoryOrM2MDstIncMode       = LL_BDMA_MEMORY_NOINCREMENT;
0331   BDMA_InitStruct->PeriphOrM2MSrcDataSize      = LL_BDMA_PDATAALIGN_BYTE;
0332   BDMA_InitStruct->MemoryOrM2MDstDataSize      = LL_BDMA_MDATAALIGN_BYTE;
0333   BDMA_InitStruct->NbData                      = 0x00000000U;
0334   BDMA_InitStruct->PeriphRequest               = LL_DMAMUX2_REQ_MEM2MEM;
0335   BDMA_InitStruct->Priority                    = LL_BDMA_PRIORITY_LOW;
0336   BDMA_InitStruct->DoubleBufferMode            = LL_BDMA_DOUBLEBUFFER_MODE_DISABLE;
0337   BDMA_InitStruct->TargetMemInDoubleBufferMode = LL_BDMA_CURRENTTARGETMEM0;
0338 }
0339
0340 /**
0341   * @}
0342   */
0343
0344 /**
0345   * @}
0346   */
0347
0348 /**
0349   * @}
0350   */
0351
0352 #endif /* BDMA || BDMA1 || BDMA2 */
0353
0354 /**
0355   * @}
0356   */
0357
0358 #endif /* USE_FULL_LL_DRIVER */
0359