stm32h7/hal/stm32h7xx_hal_tim.c

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_tim.c
0004   * @author  MCD Application Team
0005   * @brief   TIM HAL module driver.
0006   *          This file provides firmware functions to manage the following
0007   *          functionalities of the Timer (TIM) peripheral:
0008   *           + TIM Time Base Initialization
0009   *           + TIM Time Base Start
0010   *           + TIM Time Base Start Interruption
0011   *           + TIM Time Base Start DMA
0012   *           + TIM Output Compare/PWM Initialization
0013   *           + TIM Output Compare/PWM Channel Configuration
0014   *           + TIM Output Compare/PWM  Start
0015   *           + TIM Output Compare/PWM  Start Interruption
0016   *           + TIM Output Compare/PWM Start DMA
0017   *           + TIM Input Capture Initialization
0018   *           + TIM Input Capture Channel Configuration
0019   *           + TIM Input Capture Start
0020   *           + TIM Input Capture Start Interruption
0021   *           + TIM Input Capture Start DMA
0022   *           + TIM One Pulse Initialization
0023   *           + TIM One Pulse Channel Configuration
0024   *           + TIM One Pulse Start
0025   *           + TIM Encoder Interface Initialization
0026   *           + TIM Encoder Interface Start
0027   *           + TIM Encoder Interface Start Interruption
0028   *           + TIM Encoder Interface Start DMA
0029   *           + Commutation Event configuration with Interruption and DMA
0030   *           + TIM OCRef clear configuration
0031   *           + TIM External Clock configuration
0032   ******************************************************************************
0033   * @attention
0034   *
0035   * Copyright (c) 2017 STMicroelectronics.
0036   * All rights reserved.
0037   *
0038   * This software is licensed under terms that can be found in the LICENSE file
0039   * in the root directory of this software component.
0040   * If no LICENSE file comes with this software, it is provided AS-IS.
0041   *
0042   ******************************************************************************
0043   @verbatim
0044   ==============================================================================
0045                       ##### TIMER Generic features #####
0046   ==============================================================================
0047   [..] The Timer features include:
0048        (#) 16-bit up, down, up/down auto-reload counter.
0049        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
0050            counter clock frequency either by any factor between 1 and 65536.
0051        (#) Up to 4 independent channels for:
0052            (++) Input Capture
0053            (++) Output Compare
0054            (++) PWM generation (Edge and Center-aligned Mode)
0055            (++) One-pulse mode output
0056        (#) Synchronization circuit to control the timer with external signals and to interconnect
0057             several timers together.
0058        (#) Supports incremental encoder for positioning purposes
0059
0060             ##### How to use this driver #####
0061   ==============================================================================
0062     [..]
0063      (#) Initialize the TIM low level resources by implementing the following functions
0064          depending on the selected feature:
0065            (++) Time Base : HAL_TIM_Base_MspInit()
0066            (++) Input Capture : HAL_TIM_IC_MspInit()
0067            (++) Output Compare : HAL_TIM_OC_MspInit()
0068            (++) PWM generation : HAL_TIM_PWM_MspInit()
0069            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
0070            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
0071
0072      (#) Initialize the TIM low level resources :
0073         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
0074         (##) TIM pins configuration
0075             (+++) Enable the clock for the TIM GPIOs using the following function:
0076              __HAL_RCC_GPIOx_CLK_ENABLE();
0077             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
0078
0079      (#) The external Clock can be configured, if needed (the default clock is the
0080          internal clock from the APBx), using the following function:
0081          HAL_TIM_ConfigClockSource, the clock configuration should be done before
0082          any start function.
0083
0084      (#) Configure the TIM in the desired functioning mode using one of the
0085        Initialization function of this driver:
0086        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
0087        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
0088             Output Compare signal.
0089        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
0090             PWM signal.
0091        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
0092             external signal.
0093        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
0094             in One Pulse Mode.
0095        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
0096
0097      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
0098            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
0099            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
0100            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
0101            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
0102            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
0103            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
0104
0105      (#) The DMA Burst is managed with the two following functions:
0106          HAL_TIM_DMABurst_WriteStart()
0107          HAL_TIM_DMABurst_ReadStart()
0108
0109     *** Callback registration ***
0110   =============================================
0111
0112   [..]
0113   The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
0114   allows the user to configure dynamically the driver callbacks.
0115
0116   [..]
0117   Use Function HAL_TIM_RegisterCallback() to register a callback.
0118   HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
0119   the Callback ID and a pointer to the user callback function.
0120
0121   [..]
0122   Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
0123   weak function.
0124   HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
0125   and the Callback ID.
0126
0127   [..]
0128   These functions allow to register/unregister following callbacks:
0129     (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
0130     (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
0131     (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
0132     (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
0133     (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
0134     (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
0135     (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
0136     (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
0137     (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
0138     (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
0139     (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
0140     (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
0141     (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
0142     (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
0143     (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
0144     (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
0145     (+) TriggerCallback                   : TIM Trigger Callback.
0146     (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
0147     (+) IC_CaptureCallback                : TIM Input Capture Callback.
0148     (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
0149     (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
0150     (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
0151     (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
0152     (+) ErrorCallback                     : TIM Error Callback.
0153     (+) CommutationCallback               : TIM Commutation Callback.
0154     (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
0155     (+) BreakCallback                     : TIM Break Callback.
0156     (+) Break2Callback                    : TIM Break2 Callback.
0157
0158   [..]
0159 By default, after the Init and when the state is HAL_TIM_STATE_RESET
0160 all interrupt callbacks are set to the corresponding weak functions:
0161   examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
0162
0163   [..]
0164   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
0165   functionalities in the Init / DeInit only when these callbacks are null
0166   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
0167     keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
0168
0169   [..]
0170     Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
0171     Exception done MspInit / MspDeInit that can be registered / unregistered
0172     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
0173     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
0174   In that case first register the MspInit/MspDeInit user callbacks
0175       using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
0176
0177   [..]
0178       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
0179       not defined, the callback registration feature is not available and all callbacks
0180       are set to the corresponding weak functions.
0181
0182   @endverbatim
0183   ******************************************************************************
0184   */
0185
0186 /* Includes ------------------------------------------------------------------*/
0187 #include "stm32h7xx_hal.h"
0188
0189 /** @addtogroup STM32H7xx_HAL_Driver
0190   * @{
0191   */
0192
0193 /** @defgroup TIM TIM
0194   * @ingroup RTEMSBSPsARMSTM32H7
0195   * @brief TIM HAL module driver
0196   * @{
0197   */
0198
0199 #ifdef HAL_TIM_MODULE_ENABLED
0200
0201 /* Private typedef -----------------------------------------------------------*/
0202 /* Private define ------------------------------------------------------------*/
0203 /* Private macros ------------------------------------------------------------*/
0204 /* Private variables ---------------------------------------------------------*/
0205 /* Private function prototypes -----------------------------------------------*/
0206 /** @addtogroup TIM_Private_Functions
0207   * @{
0208   */
0209 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
0210 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
0211 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
0212 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
0213 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
0214 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
0215 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
0216                               uint32_t TIM_ICFilter);
0217 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
0218 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
0219                               uint32_t TIM_ICFilter);
0220 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
0221                               uint32_t TIM_ICFilter);
0222 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
0223 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
0224 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
0225 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
0226 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
0227 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
0228 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
0229                                                   const TIM_SlaveConfigTypeDef *sSlaveConfig);
0230 /**
0231   * @}
0232   */
0233 /* Exported functions --------------------------------------------------------*/
0234
0235 /** @defgroup TIM_Exported_Functions TIM Exported Functions
0236   * @ingroup RTEMSBSPsARMSTM32H7
0237   * @{
0238   */
0239
0240 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
0241   * @ingroup RTEMSBSPsARMSTM32H7
0242   *  @brief    Time Base functions
0243   *
0244 @verbatim
0245   ==============================================================================
0246               ##### Time Base functions #####
0247   ==============================================================================
0248   [..]
0249     This section provides functions allowing to:
0250     (+) Initialize and configure the TIM base.
0251     (+) De-initialize the TIM base.
0252     (+) Start the Time Base.
0253     (+) Stop the Time Base.
0254     (+) Start the Time Base and enable interrupt.
0255     (+) Stop the Time Base and disable interrupt.
0256     (+) Start the Time Base and enable DMA transfer.
0257     (+) Stop the Time Base and disable DMA transfer.
0258
0259 @endverbatim
0260   * @{
0261   */
0262 /**
0263   * @brief  Initializes the TIM Time base Unit according to the specified
0264   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
0265   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
0266   *         requires a timer reset to avoid unexpected direction
0267   *         due to DIR bit readonly in center aligned mode.
0268   *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
0269   * @param  htim TIM Base handle
0270   * @retval HAL status
0271   */
0272 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
0273 {
0274   /* Check the TIM handle allocation */
0275   if (htim == NULL)
0276   {
0277     return HAL_ERROR;
0278   }
0279
0280   /* Check the parameters */
0281   assert_param(IS_TIM_INSTANCE(htim->Instance));
0282   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
0283   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
0284   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
0285   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
0286
0287   if (htim->State == HAL_TIM_STATE_RESET)
0288   {
0289     /* Allocate lock resource and initialize it */
0290     htim->Lock = HAL_UNLOCKED;
0291
0292 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
0293     /* Reset interrupt callbacks to legacy weak callbacks */
0294     TIM_ResetCallback(htim);
0295
0296     if (htim->Base_MspInitCallback == NULL)
0297     {
0298       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
0299     }
0300     /* Init the low level hardware : GPIO, CLOCK, NVIC */
0301     htim->Base_MspInitCallback(htim);
0302 #else
0303     /* Init the low level hardware : GPIO, CLOCK, NVIC */
0304     HAL_TIM_Base_MspInit(htim);
0305 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
0306   }
0307
0308   /* Set the TIM state */
0309   htim->State = HAL_TIM_STATE_BUSY;
0310
0311   /* Set the Time Base configuration */
0312   TIM_Base_SetConfig(htim->Instance, &htim->Init);
0313
0314   /* Initialize the DMA burst operation state */
0315   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
0316
0317   /* Initialize the TIM channels state */
0318   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
0319   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
0320
0321   /* Initialize the TIM state*/
0322   htim->State = HAL_TIM_STATE_READY;
0323
0324   return HAL_OK;
0325 }
0326
0327 /**
0328   * @brief  DeInitializes the TIM Base peripheral
0329   * @param  htim TIM Base handle
0330   * @retval HAL status
0331   */
0332 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
0333 {
0334   /* Check the parameters */
0335   assert_param(IS_TIM_INSTANCE(htim->Instance));
0336
0337   htim->State = HAL_TIM_STATE_BUSY;
0338
0339   /* Disable the TIM Peripheral Clock */
0340   __HAL_TIM_DISABLE(htim);
0341
0342 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
0343   if (htim->Base_MspDeInitCallback == NULL)
0344   {
0345     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
0346   }
0347   /* DeInit the low level hardware */
0348   htim->Base_MspDeInitCallback(htim);
0349 #else
0350   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
0351   HAL_TIM_Base_MspDeInit(htim);
0352 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
0353
0354   /* Change the DMA burst operation state */
0355   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
0356
0357   /* Change the TIM channels state */
0358   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
0359   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
0360
0361   /* Change TIM state */
0362   htim->State = HAL_TIM_STATE_RESET;
0363
0364   /* Release Lock */
0365   __HAL_UNLOCK(htim);
0366
0367   return HAL_OK;
0368 }
0369
0370 /**
0371   * @brief  Initializes the TIM Base MSP.
0372   * @param  htim TIM Base handle
0373   * @retval None
0374   */
0375 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
0376 {
0377   /* Prevent unused argument(s) compilation warning */
0378   UNUSED(htim);
0379
0380   /* NOTE : This function should not be modified, when the callback is needed,
0381             the HAL_TIM_Base_MspInit could be implemented in the user file
0382    */
0383 }
0384
0385 /**
0386   * @brief  DeInitializes TIM Base MSP.
0387   * @param  htim TIM Base handle
0388   * @retval None
0389   */
0390 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
0391 {
0392   /* Prevent unused argument(s) compilation warning */
0393   UNUSED(htim);
0394
0395   /* NOTE : This function should not be modified, when the callback is needed,
0396             the HAL_TIM_Base_MspDeInit could be implemented in the user file
0397    */
0398 }
0399
0400
0401 /**
0402   * @brief  Starts the TIM Base generation.
0403   * @param  htim TIM Base handle
0404   * @retval HAL status
0405   */
0406 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
0407 {
0408   uint32_t tmpsmcr;
0409
0410   /* Check the parameters */
0411   assert_param(IS_TIM_INSTANCE(htim->Instance));
0412
0413   /* Check the TIM state */
0414   if (htim->State != HAL_TIM_STATE_READY)
0415   {
0416     return HAL_ERROR;
0417   }
0418
0419   /* Set the TIM state */
0420   htim->State = HAL_TIM_STATE_BUSY;
0421
0422   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
0423   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
0424   {
0425     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
0426     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
0427     {
0428       __HAL_TIM_ENABLE(htim);
0429     }
0430   }
0431   else
0432   {
0433     __HAL_TIM_ENABLE(htim);
0434   }
0435
0436   /* Return function status */
0437   return HAL_OK;
0438 }
0439
0440 /**
0441   * @brief  Stops the TIM Base generation.
0442   * @param  htim TIM Base handle
0443   * @retval HAL status
0444   */
0445 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
0446 {
0447   /* Check the parameters */
0448   assert_param(IS_TIM_INSTANCE(htim->Instance));
0449
0450   /* Disable the Peripheral */
0451   __HAL_TIM_DISABLE(htim);
0452
0453   /* Set the TIM state */
0454   htim->State = HAL_TIM_STATE_READY;
0455
0456   /* Return function status */
0457   return HAL_OK;
0458 }
0459
0460 /**
0461   * @brief  Starts the TIM Base generation in interrupt mode.
0462   * @param  htim TIM Base handle
0463   * @retval HAL status
0464   */
0465 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
0466 {
0467   uint32_t tmpsmcr;
0468
0469   /* Check the parameters */
0470   assert_param(IS_TIM_INSTANCE(htim->Instance));
0471
0472   /* Check the TIM state */
0473   if (htim->State != HAL_TIM_STATE_READY)
0474   {
0475     return HAL_ERROR;
0476   }
0477
0478   /* Set the TIM state */
0479   htim->State = HAL_TIM_STATE_BUSY;
0480
0481   /* Enable the TIM Update interrupt */
0482   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
0483
0484   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
0485   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
0486   {
0487     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
0488     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
0489     {
0490       __HAL_TIM_ENABLE(htim);
0491     }
0492   }
0493   else
0494   {
0495     __HAL_TIM_ENABLE(htim);
0496   }
0497
0498   /* Return function status */
0499   return HAL_OK;
0500 }
0501
0502 /**
0503   * @brief  Stops the TIM Base generation in interrupt mode.
0504   * @param  htim TIM Base handle
0505   * @retval HAL status
0506   */
0507 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
0508 {
0509   /* Check the parameters */
0510   assert_param(IS_TIM_INSTANCE(htim->Instance));
0511
0512   /* Disable the TIM Update interrupt */
0513   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
0514
0515   /* Disable the Peripheral */
0516   __HAL_TIM_DISABLE(htim);
0517
0518   /* Set the TIM state */
0519   htim->State = HAL_TIM_STATE_READY;
0520
0521   /* Return function status */
0522   return HAL_OK;
0523 }
0524
0525 /**
0526   * @brief  Starts the TIM Base generation in DMA mode.
0527   * @param  htim TIM Base handle
0528   * @param  pData The source Buffer address.
0529   * @param  Length The length of data to be transferred from memory to peripheral.
0530   * @retval HAL status
0531   */
0532 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
0533 {
0534   uint32_t tmpsmcr;
0535
0536   /* Check the parameters */
0537   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
0538
0539   /* Set the TIM state */
0540   if (htim->State == HAL_TIM_STATE_BUSY)
0541   {
0542     return HAL_BUSY;
0543   }
0544   else if (htim->State == HAL_TIM_STATE_READY)
0545   {
0546     if ((pData == NULL) || (Length == 0U))
0547     {
0548       return HAL_ERROR;
0549     }
0550     else
0551     {
0552       htim->State = HAL_TIM_STATE_BUSY;
0553     }
0554   }
0555   else
0556   {
0557     return HAL_ERROR;
0558   }
0559
0560   /* Set the DMA Period elapsed callbacks */
0561   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
0562   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
0563
0564   /* Set the DMA error callback */
0565   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
0566
0567   /* Enable the DMA stream */
0568   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
0569                        Length) != HAL_OK)
0570   {
0571     /* Return error status */
0572     return HAL_ERROR;
0573   }
0574
0575   /* Enable the TIM Update DMA request */
0576   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
0577
0578   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
0579   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
0580   {
0581     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
0582     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
0583     {
0584       __HAL_TIM_ENABLE(htim);
0585     }
0586   }
0587   else
0588   {
0589     __HAL_TIM_ENABLE(htim);
0590   }
0591
0592   /* Return function status */
0593   return HAL_OK;
0594 }
0595
0596 /**
0597   * @brief  Stops the TIM Base generation in DMA mode.
0598   * @param  htim TIM Base handle
0599   * @retval HAL status
0600   */
0601 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
0602 {
0603   /* Check the parameters */
0604   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
0605
0606   /* Disable the TIM Update DMA request */
0607   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
0608
0609   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
0610
0611   /* Disable the Peripheral */
0612   __HAL_TIM_DISABLE(htim);
0613
0614   /* Set the TIM state */
0615   htim->State = HAL_TIM_STATE_READY;
0616
0617   /* Return function status */
0618   return HAL_OK;
0619 }
0620
0621 /**
0622   * @}
0623   */
0624
0625 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
0626   * @ingroup RTEMSBSPsARMSTM32H7
0627   *  @brief    TIM Output Compare functions
0628   *
0629 @verbatim
0630   ==============================================================================
0631                   ##### TIM Output Compare functions #####
0632   ==============================================================================
0633   [..]
0634     This section provides functions allowing to:
0635     (+) Initialize and configure the TIM Output Compare.
0636     (+) De-initialize the TIM Output Compare.
0637     (+) Start the TIM Output Compare.
0638     (+) Stop the TIM Output Compare.
0639     (+) Start the TIM Output Compare and enable interrupt.
0640     (+) Stop the TIM Output Compare and disable interrupt.
0641     (+) Start the TIM Output Compare and enable DMA transfer.
0642     (+) Stop the TIM Output Compare and disable DMA transfer.
0643
0644 @endverbatim
0645   * @{
0646   */
0647 /**
0648   * @brief  Initializes the TIM Output Compare according to the specified
0649   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
0650   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
0651   *         requires a timer reset to avoid unexpected direction
0652   *         due to DIR bit readonly in center aligned mode.
0653   *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
0654   * @param  htim TIM Output Compare handle
0655   * @retval HAL status
0656   */
0657 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
0658 {
0659   /* Check the TIM handle allocation */
0660   if (htim == NULL)
0661   {
0662     return HAL_ERROR;
0663   }
0664
0665   /* Check the parameters */
0666   assert_param(IS_TIM_INSTANCE(htim->Instance));
0667   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
0668   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
0669   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
0670   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
0671
0672   if (htim->State == HAL_TIM_STATE_RESET)
0673   {
0674     /* Allocate lock resource and initialize it */
0675     htim->Lock = HAL_UNLOCKED;
0676
0677 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
0678     /* Reset interrupt callbacks to legacy weak callbacks */
0679     TIM_ResetCallback(htim);
0680
0681     if (htim->OC_MspInitCallback == NULL)
0682     {
0683       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
0684     }
0685     /* Init the low level hardware : GPIO, CLOCK, NVIC */
0686     htim->OC_MspInitCallback(htim);
0687 #else
0688     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
0689     HAL_TIM_OC_MspInit(htim);
0690 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
0691   }
0692
0693   /* Set the TIM state */
0694   htim->State = HAL_TIM_STATE_BUSY;
0695
0696   /* Init the base time for the Output Compare */
0697   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
0698
0699   /* Initialize the DMA burst operation state */
0700   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
0701
0702   /* Initialize the TIM channels state */
0703   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
0704   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
0705
0706   /* Initialize the TIM state*/
0707   htim->State = HAL_TIM_STATE_READY;
0708
0709   return HAL_OK;
0710 }
0711
0712 /**
0713   * @brief  DeInitializes the TIM peripheral
0714   * @param  htim TIM Output Compare handle
0715   * @retval HAL status
0716   */
0717 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
0718 {
0719   /* Check the parameters */
0720   assert_param(IS_TIM_INSTANCE(htim->Instance));
0721
0722   htim->State = HAL_TIM_STATE_BUSY;
0723
0724   /* Disable the TIM Peripheral Clock */
0725   __HAL_TIM_DISABLE(htim);
0726
0727 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
0728   if (htim->OC_MspDeInitCallback == NULL)
0729   {
0730     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
0731   }
0732   /* DeInit the low level hardware */
0733   htim->OC_MspDeInitCallback(htim);
0734 #else
0735   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
0736   HAL_TIM_OC_MspDeInit(htim);
0737 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
0738
0739   /* Change the DMA burst operation state */
0740   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
0741
0742   /* Change the TIM channels state */
0743   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
0744   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
0745
0746   /* Change TIM state */
0747   htim->State = HAL_TIM_STATE_RESET;
0748
0749   /* Release Lock */
0750   __HAL_UNLOCK(htim);
0751
0752   return HAL_OK;
0753 }
0754
0755 /**
0756   * @brief  Initializes the TIM Output Compare MSP.
0757   * @param  htim TIM Output Compare handle
0758   * @retval None
0759   */
0760 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
0761 {
0762   /* Prevent unused argument(s) compilation warning */
0763   UNUSED(htim);
0764
0765   /* NOTE : This function should not be modified, when the callback is needed,
0766             the HAL_TIM_OC_MspInit could be implemented in the user file
0767    */
0768 }
0769
0770 /**
0771   * @brief  DeInitializes TIM Output Compare MSP.
0772   * @param  htim TIM Output Compare handle
0773   * @retval None
0774   */
0775 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
0776 {
0777   /* Prevent unused argument(s) compilation warning */
0778   UNUSED(htim);
0779
0780   /* NOTE : This function should not be modified, when the callback is needed,
0781             the HAL_TIM_OC_MspDeInit could be implemented in the user file
0782    */
0783 }
0784
0785 /**
0786   * @brief  Starts the TIM Output Compare signal generation.
0787   * @param  htim TIM Output Compare handle
0788   * @param  Channel TIM Channel to be enabled
0789   *          This parameter can be one of the following values:
0790   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
0791   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
0792   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
0793   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
0794   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
0795   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
0796   * @retval HAL status
0797   */
0798 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
0799 {
0800   uint32_t tmpsmcr;
0801
0802   /* Check the parameters */
0803   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
0804
0805   /* Check the TIM channel state */
0806   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
0807   {
0808     return HAL_ERROR;
0809   }
0810
0811   /* Set the TIM channel state */
0812   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
0813
0814   /* Enable the Output compare channel */
0815   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
0816
0817   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
0818   {
0819     /* Enable the main output */
0820     __HAL_TIM_MOE_ENABLE(htim);
0821   }
0822
0823   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
0824   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
0825   {
0826     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
0827     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
0828     {
0829       __HAL_TIM_ENABLE(htim);
0830     }
0831   }
0832   else
0833   {
0834     __HAL_TIM_ENABLE(htim);
0835   }
0836
0837   /* Return function status */
0838   return HAL_OK;
0839 }
0840
0841 /**
0842   * @brief  Stops the TIM Output Compare signal generation.
0843   * @param  htim TIM Output Compare handle
0844   * @param  Channel TIM Channel to be disabled
0845   *          This parameter can be one of the following values:
0846   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
0847   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
0848   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
0849   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
0850   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
0851   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
0852   * @retval HAL status
0853   */
0854 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
0855 {
0856   /* Check the parameters */
0857   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
0858
0859   /* Disable the Output compare channel */
0860   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
0861
0862   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
0863   {
0864     /* Disable the Main Output */
0865     __HAL_TIM_MOE_DISABLE(htim);
0866   }
0867
0868   /* Disable the Peripheral */
0869   __HAL_TIM_DISABLE(htim);
0870
0871   /* Set the TIM channel state */
0872   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
0873
0874   /* Return function status */
0875   return HAL_OK;
0876 }
0877
0878 /**
0879   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
0880   * @param  htim TIM Output Compare handle
0881   * @param  Channel TIM Channel to be enabled
0882   *          This parameter can be one of the following values:
0883   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
0884   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
0885   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
0886   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
0887   * @retval HAL status
0888   */
0889 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
0890 {
0891   HAL_StatusTypeDef status = HAL_OK;
0892   uint32_t tmpsmcr;
0893
0894   /* Check the parameters */
0895   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
0896
0897   /* Check the TIM channel state */
0898   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
0899   {
0900     return HAL_ERROR;
0901   }
0902
0903   /* Set the TIM channel state */
0904   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
0905
0906   switch (Channel)
0907   {
0908     case TIM_CHANNEL_1:
0909     {
0910       /* Enable the TIM Capture/Compare 1 interrupt */
0911       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
0912       break;
0913     }
0914
0915     case TIM_CHANNEL_2:
0916     {
0917       /* Enable the TIM Capture/Compare 2 interrupt */
0918       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
0919       break;
0920     }
0921
0922     case TIM_CHANNEL_3:
0923     {
0924       /* Enable the TIM Capture/Compare 3 interrupt */
0925       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
0926       break;
0927     }
0928
0929     case TIM_CHANNEL_4:
0930     {
0931       /* Enable the TIM Capture/Compare 4 interrupt */
0932       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
0933       break;
0934     }
0935
0936     default:
0937       status = HAL_ERROR;
0938       break;
0939   }
0940
0941   if (status == HAL_OK)
0942   {
0943     /* Enable the Output compare channel */
0944     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
0945
0946     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
0947     {
0948       /* Enable the main output */
0949       __HAL_TIM_MOE_ENABLE(htim);
0950     }
0951
0952     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
0953     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
0954     {
0955       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
0956       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
0957       {
0958         __HAL_TIM_ENABLE(htim);
0959       }
0960     }
0961     else
0962     {
0963       __HAL_TIM_ENABLE(htim);
0964     }
0965   }
0966
0967   /* Return function status */
0968   return status;
0969 }
0970
0971 /**
0972   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
0973   * @param  htim TIM Output Compare handle
0974   * @param  Channel TIM Channel to be disabled
0975   *          This parameter can be one of the following values:
0976   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
0977   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
0978   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
0979   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
0980   * @retval HAL status
0981   */
0982 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
0983 {
0984   HAL_StatusTypeDef status = HAL_OK;
0985
0986   /* Check the parameters */
0987   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
0988
0989   switch (Channel)
0990   {
0991     case TIM_CHANNEL_1:
0992     {
0993       /* Disable the TIM Capture/Compare 1 interrupt */
0994       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
0995       break;
0996     }
0997
0998     case TIM_CHANNEL_2:
0999     {
1000       /* Disable the TIM Capture/Compare 2 interrupt */
1001       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1002       break;
1003     }
1004
1005     case TIM_CHANNEL_3:
1006     {
1007       /* Disable the TIM Capture/Compare 3 interrupt */
1008       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1009       break;
1010     }
1011
1012     case TIM_CHANNEL_4:
1013     {
1014       /* Disable the TIM Capture/Compare 4 interrupt */
1015       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1016       break;
1017     }
1018
1019     default:
1020       status = HAL_ERROR;
1021       break;
1022   }
1023
1024   if (status == HAL_OK)
1025   {
1026     /* Disable the Output compare channel */
1027     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1028
1029     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1030     {
1031       /* Disable the Main Output */
1032       __HAL_TIM_MOE_DISABLE(htim);
1033     }
1034
1035     /* Disable the Peripheral */
1036     __HAL_TIM_DISABLE(htim);
1037
1038     /* Set the TIM channel state */
1039     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1040   }
1041
1042   /* Return function status */
1043   return status;
1044 }
1045
1046 /**
1047   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
1048   * @param  htim TIM Output Compare handle
1049   * @param  Channel TIM Channel to be enabled
1050   *          This parameter can be one of the following values:
1051   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1052   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1053   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1054   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1055   * @param  pData The source Buffer address.
1056   * @param  Length The length of data to be transferred from memory to TIM peripheral
1057   * @retval HAL status
1058   */
1059 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1060                                        uint16_t Length)
1061 {
1062   HAL_StatusTypeDef status = HAL_OK;
1063   uint32_t tmpsmcr;
1064
1065   /* Check the parameters */
1066   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1067
1068   /* Set the TIM channel state */
1069   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1070   {
1071     return HAL_BUSY;
1072   }
1073   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1074   {
1075     if ((pData == NULL) || (Length == 0U))
1076     {
1077       return HAL_ERROR;
1078     }
1079     else
1080     {
1081       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1082     }
1083   }
1084   else
1085   {
1086     return HAL_ERROR;
1087   }
1088
1089   switch (Channel)
1090   {
1091     case TIM_CHANNEL_1:
1092     {
1093       /* Set the DMA compare callbacks */
1094       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1095       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1096
1097       /* Set the DMA error callback */
1098       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1099
1100       /* Enable the DMA stream */
1101       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1102                            Length) != HAL_OK)
1103       {
1104         /* Return error status */
1105         return HAL_ERROR;
1106       }
1107
1108       /* Enable the TIM Capture/Compare 1 DMA request */
1109       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1110       break;
1111     }
1112
1113     case TIM_CHANNEL_2:
1114     {
1115       /* Set the DMA compare callbacks */
1116       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1117       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1118
1119       /* Set the DMA error callback */
1120       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1121
1122       /* Enable the DMA stream */
1123       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1124                            Length) != HAL_OK)
1125       {
1126         /* Return error status */
1127         return HAL_ERROR;
1128       }
1129
1130       /* Enable the TIM Capture/Compare 2 DMA request */
1131       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1132       break;
1133     }
1134
1135     case TIM_CHANNEL_3:
1136     {
1137       /* Set the DMA compare callbacks */
1138       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1139       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1140
1141       /* Set the DMA error callback */
1142       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1143
1144       /* Enable the DMA stream */
1145       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1146                            Length) != HAL_OK)
1147       {
1148         /* Return error status */
1149         return HAL_ERROR;
1150       }
1151       /* Enable the TIM Capture/Compare 3 DMA request */
1152       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1153       break;
1154     }
1155
1156     case TIM_CHANNEL_4:
1157     {
1158       /* Set the DMA compare callbacks */
1159       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1160       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1161
1162       /* Set the DMA error callback */
1163       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1164
1165       /* Enable the DMA stream */
1166       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1167                            Length) != HAL_OK)
1168       {
1169         /* Return error status */
1170         return HAL_ERROR;
1171       }
1172       /* Enable the TIM Capture/Compare 4 DMA request */
1173       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1174       break;
1175     }
1176
1177     default:
1178       status = HAL_ERROR;
1179       break;
1180   }
1181
1182   if (status == HAL_OK)
1183   {
1184     /* Enable the Output compare channel */
1185     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1186
1187     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1188     {
1189       /* Enable the main output */
1190       __HAL_TIM_MOE_ENABLE(htim);
1191     }
1192
1193     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1194     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1195     {
1196       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1197       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1198       {
1199         __HAL_TIM_ENABLE(htim);
1200       }
1201     }
1202     else
1203     {
1204       __HAL_TIM_ENABLE(htim);
1205     }
1206   }
1207
1208   /* Return function status */
1209   return status;
1210 }
1211
1212 /**
1213   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
1214   * @param  htim TIM Output Compare handle
1215   * @param  Channel TIM Channel to be disabled
1216   *          This parameter can be one of the following values:
1217   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1218   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1219   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1220   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1221   * @retval HAL status
1222   */
1223 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1224 {
1225   HAL_StatusTypeDef status = HAL_OK;
1226
1227   /* Check the parameters */
1228   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1229
1230   switch (Channel)
1231   {
1232     case TIM_CHANNEL_1:
1233     {
1234       /* Disable the TIM Capture/Compare 1 DMA request */
1235       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1236       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1237       break;
1238     }
1239
1240     case TIM_CHANNEL_2:
1241     {
1242       /* Disable the TIM Capture/Compare 2 DMA request */
1243       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1244       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1245       break;
1246     }
1247
1248     case TIM_CHANNEL_3:
1249     {
1250       /* Disable the TIM Capture/Compare 3 DMA request */
1251       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1252       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1253       break;
1254     }
1255
1256     case TIM_CHANNEL_4:
1257     {
1258       /* Disable the TIM Capture/Compare 4 interrupt */
1259       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1260       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1261       break;
1262     }
1263
1264     default:
1265       status = HAL_ERROR;
1266       break;
1267   }
1268
1269   if (status == HAL_OK)
1270   {
1271     /* Disable the Output compare channel */
1272     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1273
1274     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1275     {
1276       /* Disable the Main Output */
1277       __HAL_TIM_MOE_DISABLE(htim);
1278     }
1279
1280     /* Disable the Peripheral */
1281     __HAL_TIM_DISABLE(htim);
1282
1283     /* Set the TIM channel state */
1284     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1285   }
1286
1287   /* Return function status */
1288   return status;
1289 }
1290
1291 /**
1292   * @}
1293   */
1294
1295 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1296   * @ingroup RTEMSBSPsARMSTM32H7
1297   *  @brief    TIM PWM functions
1298   *
1299 @verbatim
1300   ==============================================================================
1301                           ##### TIM PWM functions #####
1302   ==============================================================================
1303   [..]
1304     This section provides functions allowing to:
1305     (+) Initialize and configure the TIM PWM.
1306     (+) De-initialize the TIM PWM.
1307     (+) Start the TIM PWM.
1308     (+) Stop the TIM PWM.
1309     (+) Start the TIM PWM and enable interrupt.
1310     (+) Stop the TIM PWM and disable interrupt.
1311     (+) Start the TIM PWM and enable DMA transfer.
1312     (+) Stop the TIM PWM and disable DMA transfer.
1313
1314 @endverbatim
1315   * @{
1316   */
1317 /**
1318   * @brief  Initializes the TIM PWM Time Base according to the specified
1319   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
1320   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1321   *         requires a timer reset to avoid unexpected direction
1322   *         due to DIR bit readonly in center aligned mode.
1323   *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1324   * @param  htim TIM PWM handle
1325   * @retval HAL status
1326   */
1327 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1328 {
1329   /* Check the TIM handle allocation */
1330   if (htim == NULL)
1331   {
1332     return HAL_ERROR;
1333   }
1334
1335   /* Check the parameters */
1336   assert_param(IS_TIM_INSTANCE(htim->Instance));
1337   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1338   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1339   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1340   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1341
1342   if (htim->State == HAL_TIM_STATE_RESET)
1343   {
1344     /* Allocate lock resource and initialize it */
1345     htim->Lock = HAL_UNLOCKED;
1346
1347 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1348     /* Reset interrupt callbacks to legacy weak callbacks */
1349     TIM_ResetCallback(htim);
1350
1351     if (htim->PWM_MspInitCallback == NULL)
1352     {
1353       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1354     }
1355     /* Init the low level hardware : GPIO, CLOCK, NVIC */
1356     htim->PWM_MspInitCallback(htim);
1357 #else
1358     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1359     HAL_TIM_PWM_MspInit(htim);
1360 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1361   }
1362
1363   /* Set the TIM state */
1364   htim->State = HAL_TIM_STATE_BUSY;
1365
1366   /* Init the base time for the PWM */
1367   TIM_Base_SetConfig(htim->Instance, &htim->Init);
1368
1369   /* Initialize the DMA burst operation state */
1370   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1371
1372   /* Initialize the TIM channels state */
1373   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1374   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1375
1376   /* Initialize the TIM state*/
1377   htim->State = HAL_TIM_STATE_READY;
1378
1379   return HAL_OK;
1380 }
1381
1382 /**
1383   * @brief  DeInitializes the TIM peripheral
1384   * @param  htim TIM PWM handle
1385   * @retval HAL status
1386   */
1387 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1388 {
1389   /* Check the parameters */
1390   assert_param(IS_TIM_INSTANCE(htim->Instance));
1391
1392   htim->State = HAL_TIM_STATE_BUSY;
1393
1394   /* Disable the TIM Peripheral Clock */
1395   __HAL_TIM_DISABLE(htim);
1396
1397 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1398   if (htim->PWM_MspDeInitCallback == NULL)
1399   {
1400     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1401   }
1402   /* DeInit the low level hardware */
1403   htim->PWM_MspDeInitCallback(htim);
1404 #else
1405   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1406   HAL_TIM_PWM_MspDeInit(htim);
1407 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1408
1409   /* Change the DMA burst operation state */
1410   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1411
1412   /* Change the TIM channels state */
1413   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1414   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1415
1416   /* Change TIM state */
1417   htim->State = HAL_TIM_STATE_RESET;
1418
1419   /* Release Lock */
1420   __HAL_UNLOCK(htim);
1421
1422   return HAL_OK;
1423 }
1424
1425 /**
1426   * @brief  Initializes the TIM PWM MSP.
1427   * @param  htim TIM PWM handle
1428   * @retval None
1429   */
1430 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1431 {
1432   /* Prevent unused argument(s) compilation warning */
1433   UNUSED(htim);
1434
1435   /* NOTE : This function should not be modified, when the callback is needed,
1436             the HAL_TIM_PWM_MspInit could be implemented in the user file
1437    */
1438 }
1439
1440 /**
1441   * @brief  DeInitializes TIM PWM MSP.
1442   * @param  htim TIM PWM handle
1443   * @retval None
1444   */
1445 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1446 {
1447   /* Prevent unused argument(s) compilation warning */
1448   UNUSED(htim);
1449
1450   /* NOTE : This function should not be modified, when the callback is needed,
1451             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1452    */
1453 }
1454
1455 /**
1456   * @brief  Starts the PWM signal generation.
1457   * @param  htim TIM handle
1458   * @param  Channel TIM Channels to be enabled
1459   *          This parameter can be one of the following values:
1460   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1461   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1462   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1463   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1464   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1465   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1466   * @retval HAL status
1467   */
1468 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1469 {
1470   uint32_t tmpsmcr;
1471
1472   /* Check the parameters */
1473   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1474
1475   /* Check the TIM channel state */
1476   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1477   {
1478     return HAL_ERROR;
1479   }
1480
1481   /* Set the TIM channel state */
1482   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1483
1484   /* Enable the Capture compare channel */
1485   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1486
1487   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1488   {
1489     /* Enable the main output */
1490     __HAL_TIM_MOE_ENABLE(htim);
1491   }
1492
1493   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1494   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1495   {
1496     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1497     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1498     {
1499       __HAL_TIM_ENABLE(htim);
1500     }
1501   }
1502   else
1503   {
1504     __HAL_TIM_ENABLE(htim);
1505   }
1506
1507   /* Return function status */
1508   return HAL_OK;
1509 }
1510
1511 /**
1512   * @brief  Stops the PWM signal generation.
1513   * @param  htim TIM PWM handle
1514   * @param  Channel TIM Channels to be disabled
1515   *          This parameter can be one of the following values:
1516   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1517   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1518   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1519   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1520   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1521   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1522   * @retval HAL status
1523   */
1524 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1525 {
1526   /* Check the parameters */
1527   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1528
1529   /* Disable the Capture compare channel */
1530   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1531
1532   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1533   {
1534     /* Disable the Main Output */
1535     __HAL_TIM_MOE_DISABLE(htim);
1536   }
1537
1538   /* Disable the Peripheral */
1539   __HAL_TIM_DISABLE(htim);
1540
1541   /* Set the TIM channel state */
1542   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1543
1544   /* Return function status */
1545   return HAL_OK;
1546 }
1547
1548 /**
1549   * @brief  Starts the PWM signal generation in interrupt mode.
1550   * @param  htim TIM PWM handle
1551   * @param  Channel TIM Channel to be enabled
1552   *          This parameter can be one of the following values:
1553   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1554   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1555   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1556   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1557   * @retval HAL status
1558   */
1559 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1560 {
1561   HAL_StatusTypeDef status = HAL_OK;
1562   uint32_t tmpsmcr;
1563
1564   /* Check the parameters */
1565   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1566
1567   /* Check the TIM channel state */
1568   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1569   {
1570     return HAL_ERROR;
1571   }
1572
1573   /* Set the TIM channel state */
1574   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1575
1576   switch (Channel)
1577   {
1578     case TIM_CHANNEL_1:
1579     {
1580       /* Enable the TIM Capture/Compare 1 interrupt */
1581       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1582       break;
1583     }
1584
1585     case TIM_CHANNEL_2:
1586     {
1587       /* Enable the TIM Capture/Compare 2 interrupt */
1588       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1589       break;
1590     }
1591
1592     case TIM_CHANNEL_3:
1593     {
1594       /* Enable the TIM Capture/Compare 3 interrupt */
1595       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1596       break;
1597     }
1598
1599     case TIM_CHANNEL_4:
1600     {
1601       /* Enable the TIM Capture/Compare 4 interrupt */
1602       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1603       break;
1604     }
1605
1606     default:
1607       status = HAL_ERROR;
1608       break;
1609   }
1610
1611   if (status == HAL_OK)
1612   {
1613     /* Enable the Capture compare channel */
1614     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1615
1616     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1617     {
1618       /* Enable the main output */
1619       __HAL_TIM_MOE_ENABLE(htim);
1620     }
1621
1622     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1623     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1624     {
1625       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1626       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1627       {
1628         __HAL_TIM_ENABLE(htim);
1629       }
1630     }
1631     else
1632     {
1633       __HAL_TIM_ENABLE(htim);
1634     }
1635   }
1636
1637   /* Return function status */
1638   return status;
1639 }
1640
1641 /**
1642   * @brief  Stops the PWM signal generation in interrupt mode.
1643   * @param  htim TIM PWM handle
1644   * @param  Channel TIM Channels to be disabled
1645   *          This parameter can be one of the following values:
1646   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1647   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1648   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1649   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1650   * @retval HAL status
1651   */
1652 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1653 {
1654   HAL_StatusTypeDef status = HAL_OK;
1655
1656   /* Check the parameters */
1657   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1658
1659   switch (Channel)
1660   {
1661     case TIM_CHANNEL_1:
1662     {
1663       /* Disable the TIM Capture/Compare 1 interrupt */
1664       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1665       break;
1666     }
1667
1668     case TIM_CHANNEL_2:
1669     {
1670       /* Disable the TIM Capture/Compare 2 interrupt */
1671       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1672       break;
1673     }
1674
1675     case TIM_CHANNEL_3:
1676     {
1677       /* Disable the TIM Capture/Compare 3 interrupt */
1678       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1679       break;
1680     }
1681
1682     case TIM_CHANNEL_4:
1683     {
1684       /* Disable the TIM Capture/Compare 4 interrupt */
1685       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1686       break;
1687     }
1688
1689     default:
1690       status = HAL_ERROR;
1691       break;
1692   }
1693
1694   if (status == HAL_OK)
1695   {
1696     /* Disable the Capture compare channel */
1697     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1698
1699     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1700     {
1701       /* Disable the Main Output */
1702       __HAL_TIM_MOE_DISABLE(htim);
1703     }
1704
1705     /* Disable the Peripheral */
1706     __HAL_TIM_DISABLE(htim);
1707
1708     /* Set the TIM channel state */
1709     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1710   }
1711
1712   /* Return function status */
1713   return status;
1714 }
1715
1716 /**
1717   * @brief  Starts the TIM PWM signal generation in DMA mode.
1718   * @param  htim TIM PWM handle
1719   * @param  Channel TIM Channels to be enabled
1720   *          This parameter can be one of the following values:
1721   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1722   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1723   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1724   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1725   * @param  pData The source Buffer address.
1726   * @param  Length The length of data to be transferred from memory to TIM peripheral
1727   * @retval HAL status
1728   */
1729 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1730                                         uint16_t Length)
1731 {
1732   HAL_StatusTypeDef status = HAL_OK;
1733   uint32_t tmpsmcr;
1734
1735   /* Check the parameters */
1736   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1737
1738   /* Set the TIM channel state */
1739   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1740   {
1741     return HAL_BUSY;
1742   }
1743   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1744   {
1745     if ((pData == NULL) || (Length == 0U))
1746     {
1747       return HAL_ERROR;
1748     }
1749     else
1750     {
1751       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1752     }
1753   }
1754   else
1755   {
1756     return HAL_ERROR;
1757   }
1758
1759   switch (Channel)
1760   {
1761     case TIM_CHANNEL_1:
1762     {
1763       /* Set the DMA compare callbacks */
1764       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1765       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1766
1767       /* Set the DMA error callback */
1768       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1769
1770       /* Enable the DMA stream */
1771       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1772                            Length) != HAL_OK)
1773       {
1774         /* Return error status */
1775         return HAL_ERROR;
1776       }
1777
1778       /* Enable the TIM Capture/Compare 1 DMA request */
1779       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1780       break;
1781     }
1782
1783     case TIM_CHANNEL_2:
1784     {
1785       /* Set the DMA compare callbacks */
1786       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1787       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1788
1789       /* Set the DMA error callback */
1790       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1791
1792       /* Enable the DMA stream */
1793       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1794                            Length) != HAL_OK)
1795       {
1796         /* Return error status */
1797         return HAL_ERROR;
1798       }
1799       /* Enable the TIM Capture/Compare 2 DMA request */
1800       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1801       break;
1802     }
1803
1804     case TIM_CHANNEL_3:
1805     {
1806       /* Set the DMA compare callbacks */
1807       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1808       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1809
1810       /* Set the DMA error callback */
1811       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1812
1813       /* Enable the DMA stream */
1814       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1815                            Length) != HAL_OK)
1816       {
1817         /* Return error status */
1818         return HAL_ERROR;
1819       }
1820       /* Enable the TIM Output Capture/Compare 3 request */
1821       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1822       break;
1823     }
1824
1825     case TIM_CHANNEL_4:
1826     {
1827       /* Set the DMA compare callbacks */
1828       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1829       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1830
1831       /* Set the DMA error callback */
1832       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1833
1834       /* Enable the DMA stream */
1835       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1836                            Length) != HAL_OK)
1837       {
1838         /* Return error status */
1839         return HAL_ERROR;
1840       }
1841       /* Enable the TIM Capture/Compare 4 DMA request */
1842       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1843       break;
1844     }
1845
1846     default:
1847       status = HAL_ERROR;
1848       break;
1849   }
1850
1851   if (status == HAL_OK)
1852   {
1853     /* Enable the Capture compare channel */
1854     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1855
1856     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1857     {
1858       /* Enable the main output */
1859       __HAL_TIM_MOE_ENABLE(htim);
1860     }
1861
1862     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1863     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1864     {
1865       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1866       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1867       {
1868         __HAL_TIM_ENABLE(htim);
1869       }
1870     }
1871     else
1872     {
1873       __HAL_TIM_ENABLE(htim);
1874     }
1875   }
1876
1877   /* Return function status */
1878   return status;
1879 }
1880
1881 /**
1882   * @brief  Stops the TIM PWM signal generation in DMA mode.
1883   * @param  htim TIM PWM handle
1884   * @param  Channel TIM Channels to be disabled
1885   *          This parameter can be one of the following values:
1886   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1887   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1888   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1889   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1890   * @retval HAL status
1891   */
1892 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1893 {
1894   HAL_StatusTypeDef status = HAL_OK;
1895
1896   /* Check the parameters */
1897   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1898
1899   switch (Channel)
1900   {
1901     case TIM_CHANNEL_1:
1902     {
1903       /* Disable the TIM Capture/Compare 1 DMA request */
1904       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1905       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1906       break;
1907     }
1908
1909     case TIM_CHANNEL_2:
1910     {
1911       /* Disable the TIM Capture/Compare 2 DMA request */
1912       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1913       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1914       break;
1915     }
1916
1917     case TIM_CHANNEL_3:
1918     {
1919       /* Disable the TIM Capture/Compare 3 DMA request */
1920       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1921       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1922       break;
1923     }
1924
1925     case TIM_CHANNEL_4:
1926     {
1927       /* Disable the TIM Capture/Compare 4 interrupt */
1928       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1929       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1930       break;
1931     }
1932
1933     default:
1934       status = HAL_ERROR;
1935       break;
1936   }
1937
1938   if (status == HAL_OK)
1939   {
1940     /* Disable the Capture compare channel */
1941     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1942
1943     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1944     {
1945       /* Disable the Main Output */
1946       __HAL_TIM_MOE_DISABLE(htim);
1947     }
1948
1949     /* Disable the Peripheral */
1950     __HAL_TIM_DISABLE(htim);
1951
1952     /* Set the TIM channel state */
1953     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1954   }
1955
1956   /* Return function status */
1957   return status;
1958 }
1959
1960 /**
1961   * @}
1962   */
1963
1964 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1965   * @ingroup RTEMSBSPsARMSTM32H7
1966   *  @brief    TIM Input Capture functions
1967   *
1968 @verbatim
1969   ==============================================================================
1970               ##### TIM Input Capture functions #####
1971   ==============================================================================
1972  [..]
1973    This section provides functions allowing to:
1974    (+) Initialize and configure the TIM Input Capture.
1975    (+) De-initialize the TIM Input Capture.
1976    (+) Start the TIM Input Capture.
1977    (+) Stop the TIM Input Capture.
1978    (+) Start the TIM Input Capture and enable interrupt.
1979    (+) Stop the TIM Input Capture and disable interrupt.
1980    (+) Start the TIM Input Capture and enable DMA transfer.
1981    (+) Stop the TIM Input Capture and disable DMA transfer.
1982
1983 @endverbatim
1984   * @{
1985   */
1986 /**
1987   * @brief  Initializes the TIM Input Capture Time base according to the specified
1988   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
1989   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1990   *         requires a timer reset to avoid unexpected direction
1991   *         due to DIR bit readonly in center aligned mode.
1992   *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1993   * @param  htim TIM Input Capture handle
1994   * @retval HAL status
1995   */
1996 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1997 {
1998   /* Check the TIM handle allocation */
1999   if (htim == NULL)
2000   {
2001     return HAL_ERROR;
2002   }
2003
2004   /* Check the parameters */
2005   assert_param(IS_TIM_INSTANCE(htim->Instance));
2006   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2007   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2008   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2009   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2010
2011   if (htim->State == HAL_TIM_STATE_RESET)
2012   {
2013     /* Allocate lock resource and initialize it */
2014     htim->Lock = HAL_UNLOCKED;
2015
2016 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2017     /* Reset interrupt callbacks to legacy weak callbacks */
2018     TIM_ResetCallback(htim);
2019
2020     if (htim->IC_MspInitCallback == NULL)
2021     {
2022       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2023     }
2024     /* Init the low level hardware : GPIO, CLOCK, NVIC */
2025     htim->IC_MspInitCallback(htim);
2026 #else
2027     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2028     HAL_TIM_IC_MspInit(htim);
2029 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2030   }
2031
2032   /* Set the TIM state */
2033   htim->State = HAL_TIM_STATE_BUSY;
2034
2035   /* Init the base time for the input capture */
2036   TIM_Base_SetConfig(htim->Instance, &htim->Init);
2037
2038   /* Initialize the DMA burst operation state */
2039   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2040
2041   /* Initialize the TIM channels state */
2042   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2043   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2044
2045   /* Initialize the TIM state*/
2046   htim->State = HAL_TIM_STATE_READY;
2047
2048   return HAL_OK;
2049 }
2050
2051 /**
2052   * @brief  DeInitializes the TIM peripheral
2053   * @param  htim TIM Input Capture handle
2054   * @retval HAL status
2055   */
2056 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2057 {
2058   /* Check the parameters */
2059   assert_param(IS_TIM_INSTANCE(htim->Instance));
2060
2061   htim->State = HAL_TIM_STATE_BUSY;
2062
2063   /* Disable the TIM Peripheral Clock */
2064   __HAL_TIM_DISABLE(htim);
2065
2066 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2067   if (htim->IC_MspDeInitCallback == NULL)
2068   {
2069     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2070   }
2071   /* DeInit the low level hardware */
2072   htim->IC_MspDeInitCallback(htim);
2073 #else
2074   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2075   HAL_TIM_IC_MspDeInit(htim);
2076 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2077
2078   /* Change the DMA burst operation state */
2079   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2080
2081   /* Change the TIM channels state */
2082   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2083   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2084
2085   /* Change TIM state */
2086   htim->State = HAL_TIM_STATE_RESET;
2087
2088   /* Release Lock */
2089   __HAL_UNLOCK(htim);
2090
2091   return HAL_OK;
2092 }
2093
2094 /**
2095   * @brief  Initializes the TIM Input Capture MSP.
2096   * @param  htim TIM Input Capture handle
2097   * @retval None
2098   */
2099 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2100 {
2101   /* Prevent unused argument(s) compilation warning */
2102   UNUSED(htim);
2103
2104   /* NOTE : This function should not be modified, when the callback is needed,
2105             the HAL_TIM_IC_MspInit could be implemented in the user file
2106    */
2107 }
2108
2109 /**
2110   * @brief  DeInitializes TIM Input Capture MSP.
2111   * @param  htim TIM handle
2112   * @retval None
2113   */
2114 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2115 {
2116   /* Prevent unused argument(s) compilation warning */
2117   UNUSED(htim);
2118
2119   /* NOTE : This function should not be modified, when the callback is needed,
2120             the HAL_TIM_IC_MspDeInit could be implemented in the user file
2121    */
2122 }
2123
2124 /**
2125   * @brief  Starts the TIM Input Capture measurement.
2126   * @param  htim TIM Input Capture handle
2127   * @param  Channel TIM Channels to be enabled
2128   *          This parameter can be one of the following values:
2129   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2130   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2131   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2132   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2133   * @retval HAL status
2134   */
2135 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2136 {
2137   uint32_t tmpsmcr;
2138   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2139   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2140
2141   /* Check the parameters */
2142   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2143
2144   /* Check the TIM channel state */
2145   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2146       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2147   {
2148     return HAL_ERROR;
2149   }
2150
2151   /* Set the TIM channel state */
2152   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2153   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2154
2155   /* Enable the Input Capture channel */
2156   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2157
2158   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2159   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2160   {
2161     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2162     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2163     {
2164       __HAL_TIM_ENABLE(htim);
2165     }
2166   }
2167   else
2168   {
2169     __HAL_TIM_ENABLE(htim);
2170   }
2171
2172   /* Return function status */
2173   return HAL_OK;
2174 }
2175
2176 /**
2177   * @brief  Stops the TIM Input Capture measurement.
2178   * @param  htim TIM Input Capture handle
2179   * @param  Channel TIM Channels to be disabled
2180   *          This parameter can be one of the following values:
2181   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2182   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2183   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2184   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2185   * @retval HAL status
2186   */
2187 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2188 {
2189   /* Check the parameters */
2190   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2191
2192   /* Disable the Input Capture channel */
2193   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2194
2195   /* Disable the Peripheral */
2196   __HAL_TIM_DISABLE(htim);
2197
2198   /* Set the TIM channel state */
2199   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2200   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2201
2202   /* Return function status */
2203   return HAL_OK;
2204 }
2205
2206 /**
2207   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
2208   * @param  htim TIM Input Capture handle
2209   * @param  Channel TIM Channels to be enabled
2210   *          This parameter can be one of the following values:
2211   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2212   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2213   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2214   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2215   * @retval HAL status
2216   */
2217 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2218 {
2219   HAL_StatusTypeDef status = HAL_OK;
2220   uint32_t tmpsmcr;
2221
2222   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2223   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2224
2225   /* Check the parameters */
2226   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2227
2228   /* Check the TIM channel state */
2229   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2230       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2231   {
2232     return HAL_ERROR;
2233   }
2234
2235   /* Set the TIM channel state */
2236   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2237   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2238
2239   switch (Channel)
2240   {
2241     case TIM_CHANNEL_1:
2242     {
2243       /* Enable the TIM Capture/Compare 1 interrupt */
2244       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2245       break;
2246     }
2247
2248     case TIM_CHANNEL_2:
2249     {
2250       /* Enable the TIM Capture/Compare 2 interrupt */
2251       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2252       break;
2253     }
2254
2255     case TIM_CHANNEL_3:
2256     {
2257       /* Enable the TIM Capture/Compare 3 interrupt */
2258       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2259       break;
2260     }
2261
2262     case TIM_CHANNEL_4:
2263     {
2264       /* Enable the TIM Capture/Compare 4 interrupt */
2265       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2266       break;
2267     }
2268
2269     default:
2270       status = HAL_ERROR;
2271       break;
2272   }
2273
2274   if (status == HAL_OK)
2275   {
2276     /* Enable the Input Capture channel */
2277     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2278
2279     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2280     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2281     {
2282       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2283       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2284       {
2285         __HAL_TIM_ENABLE(htim);
2286       }
2287     }
2288     else
2289     {
2290       __HAL_TIM_ENABLE(htim);
2291     }
2292   }
2293
2294   /* Return function status */
2295   return status;
2296 }
2297
2298 /**
2299   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
2300   * @param  htim TIM Input Capture handle
2301   * @param  Channel TIM Channels to be disabled
2302   *          This parameter can be one of the following values:
2303   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2304   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2305   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2306   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2307   * @retval HAL status
2308   */
2309 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2310 {
2311   HAL_StatusTypeDef status = HAL_OK;
2312
2313   /* Check the parameters */
2314   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2315
2316   switch (Channel)
2317   {
2318     case TIM_CHANNEL_1:
2319     {
2320       /* Disable the TIM Capture/Compare 1 interrupt */
2321       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2322       break;
2323     }
2324
2325     case TIM_CHANNEL_2:
2326     {
2327       /* Disable the TIM Capture/Compare 2 interrupt */
2328       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2329       break;
2330     }
2331
2332     case TIM_CHANNEL_3:
2333     {
2334       /* Disable the TIM Capture/Compare 3 interrupt */
2335       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2336       break;
2337     }
2338
2339     case TIM_CHANNEL_4:
2340     {
2341       /* Disable the TIM Capture/Compare 4 interrupt */
2342       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2343       break;
2344     }
2345
2346     default:
2347       status = HAL_ERROR;
2348       break;
2349   }
2350
2351   if (status == HAL_OK)
2352   {
2353     /* Disable the Input Capture channel */
2354     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2355
2356     /* Disable the Peripheral */
2357     __HAL_TIM_DISABLE(htim);
2358
2359     /* Set the TIM channel state */
2360     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2361     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2362   }
2363
2364   /* Return function status */
2365   return status;
2366 }
2367
2368 /**
2369   * @brief  Starts the TIM Input Capture measurement in DMA mode.
2370   * @param  htim TIM Input Capture handle
2371   * @param  Channel TIM Channels to be enabled
2372   *          This parameter can be one of the following values:
2373   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2374   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2375   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2376   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2377   * @param  pData The destination Buffer address.
2378   * @param  Length The length of data to be transferred from TIM peripheral to memory.
2379   * @retval HAL status
2380   */
2381 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2382 {
2383   HAL_StatusTypeDef status = HAL_OK;
2384   uint32_t tmpsmcr;
2385
2386   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2387   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2388
2389   /* Check the parameters */
2390   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2391   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2392
2393   /* Set the TIM channel state */
2394   if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2395       || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2396   {
2397     return HAL_BUSY;
2398   }
2399   else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2400            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2401   {
2402     if ((pData == NULL) || (Length == 0U))
2403     {
2404       return HAL_ERROR;
2405     }
2406     else
2407     {
2408       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2409       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2410     }
2411   }
2412   else
2413   {
2414     return HAL_ERROR;
2415   }
2416
2417   /* Enable the Input Capture channel */
2418   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2419
2420   switch (Channel)
2421   {
2422     case TIM_CHANNEL_1:
2423     {
2424       /* Set the DMA capture callbacks */
2425       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2426       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2427
2428       /* Set the DMA error callback */
2429       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2430
2431       /* Enable the DMA stream */
2432       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2433                            Length) != HAL_OK)
2434       {
2435         /* Return error status */
2436         return HAL_ERROR;
2437       }
2438       /* Enable the TIM Capture/Compare 1 DMA request */
2439       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2440       break;
2441     }
2442
2443     case TIM_CHANNEL_2:
2444     {
2445       /* Set the DMA capture callbacks */
2446       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2447       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2448
2449       /* Set the DMA error callback */
2450       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2451
2452       /* Enable the DMA stream */
2453       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2454                            Length) != HAL_OK)
2455       {
2456         /* Return error status */
2457         return HAL_ERROR;
2458       }
2459       /* Enable the TIM Capture/Compare 2  DMA request */
2460       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2461       break;
2462     }
2463
2464     case TIM_CHANNEL_3:
2465     {
2466       /* Set the DMA capture callbacks */
2467       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2468       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2469
2470       /* Set the DMA error callback */
2471       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2472
2473       /* Enable the DMA stream */
2474       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2475                            Length) != HAL_OK)
2476       {
2477         /* Return error status */
2478         return HAL_ERROR;
2479       }
2480       /* Enable the TIM Capture/Compare 3  DMA request */
2481       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2482       break;
2483     }
2484
2485     case TIM_CHANNEL_4:
2486     {
2487       /* Set the DMA capture callbacks */
2488       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2489       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2490
2491       /* Set the DMA error callback */
2492       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2493
2494       /* Enable the DMA stream */
2495       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2496                            Length) != HAL_OK)
2497       {
2498         /* Return error status */
2499         return HAL_ERROR;
2500       }
2501       /* Enable the TIM Capture/Compare 4  DMA request */
2502       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2503       break;
2504     }
2505
2506     default:
2507       status = HAL_ERROR;
2508       break;
2509   }
2510
2511   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2512   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2513   {
2514     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2515     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2516     {
2517       __HAL_TIM_ENABLE(htim);
2518     }
2519   }
2520   else
2521   {
2522     __HAL_TIM_ENABLE(htim);
2523   }
2524
2525   /* Return function status */
2526   return status;
2527 }
2528
2529 /**
2530   * @brief  Stops the TIM Input Capture measurement in DMA mode.
2531   * @param  htim TIM Input Capture handle
2532   * @param  Channel TIM Channels to be disabled
2533   *          This parameter can be one of the following values:
2534   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2535   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2536   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2537   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2538   * @retval HAL status
2539   */
2540 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2541 {
2542   HAL_StatusTypeDef status = HAL_OK;
2543
2544   /* Check the parameters */
2545   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2546   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2547
2548   /* Disable the Input Capture channel */
2549   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2550
2551   switch (Channel)
2552   {
2553     case TIM_CHANNEL_1:
2554     {
2555       /* Disable the TIM Capture/Compare 1 DMA request */
2556       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2557       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2558       break;
2559     }
2560
2561     case TIM_CHANNEL_2:
2562     {
2563       /* Disable the TIM Capture/Compare 2 DMA request */
2564       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2565       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2566       break;
2567     }
2568
2569     case TIM_CHANNEL_3:
2570     {
2571       /* Disable the TIM Capture/Compare 3  DMA request */
2572       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2573       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2574       break;
2575     }
2576
2577     case TIM_CHANNEL_4:
2578     {
2579       /* Disable the TIM Capture/Compare 4  DMA request */
2580       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2581       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2582       break;
2583     }
2584
2585     default:
2586       status = HAL_ERROR;
2587       break;
2588   }
2589
2590   if (status == HAL_OK)
2591   {
2592     /* Disable the Peripheral */
2593     __HAL_TIM_DISABLE(htim);
2594
2595     /* Set the TIM channel state */
2596     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2597     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2598   }
2599
2600   /* Return function status */
2601   return status;
2602 }
2603 /**
2604   * @}
2605   */
2606
2607 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2608   * @ingroup RTEMSBSPsARMSTM32H7
2609   *  @brief    TIM One Pulse functions
2610   *
2611 @verbatim
2612   ==============================================================================
2613                         ##### TIM One Pulse functions #####
2614   ==============================================================================
2615   [..]
2616     This section provides functions allowing to:
2617     (+) Initialize and configure the TIM One Pulse.
2618     (+) De-initialize the TIM One Pulse.
2619     (+) Start the TIM One Pulse.
2620     (+) Stop the TIM One Pulse.
2621     (+) Start the TIM One Pulse and enable interrupt.
2622     (+) Stop the TIM One Pulse and disable interrupt.
2623     (+) Start the TIM One Pulse and enable DMA transfer.
2624     (+) Stop the TIM One Pulse and disable DMA transfer.
2625
2626 @endverbatim
2627   * @{
2628   */
2629 /**
2630   * @brief  Initializes the TIM One Pulse Time Base according to the specified
2631   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
2632   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2633   *         requires a timer reset to avoid unexpected direction
2634   *         due to DIR bit readonly in center aligned mode.
2635   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2636   * @note   When the timer instance is initialized in One Pulse mode, timer
2637   *         channels 1 and channel 2 are reserved and cannot be used for other
2638   *         purpose.
2639   * @param  htim TIM One Pulse handle
2640   * @param  OnePulseMode Select the One pulse mode.
2641   *         This parameter can be one of the following values:
2642   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2643   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2644   * @retval HAL status
2645   */
2646 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2647 {
2648   /* Check the TIM handle allocation */
2649   if (htim == NULL)
2650   {
2651     return HAL_ERROR;
2652   }
2653
2654   /* Check the parameters */
2655   assert_param(IS_TIM_INSTANCE(htim->Instance));
2656   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2657   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2658   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2659   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2660   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2661
2662   if (htim->State == HAL_TIM_STATE_RESET)
2663   {
2664     /* Allocate lock resource and initialize it */
2665     htim->Lock = HAL_UNLOCKED;
2666
2667 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2668     /* Reset interrupt callbacks to legacy weak callbacks */
2669     TIM_ResetCallback(htim);
2670
2671     if (htim->OnePulse_MspInitCallback == NULL)
2672     {
2673       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2674     }
2675     /* Init the low level hardware : GPIO, CLOCK, NVIC */
2676     htim->OnePulse_MspInitCallback(htim);
2677 #else
2678     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2679     HAL_TIM_OnePulse_MspInit(htim);
2680 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2681   }
2682
2683   /* Set the TIM state */
2684   htim->State = HAL_TIM_STATE_BUSY;
2685
2686   /* Configure the Time base in the One Pulse Mode */
2687   TIM_Base_SetConfig(htim->Instance, &htim->Init);
2688
2689   /* Reset the OPM Bit */
2690   htim->Instance->CR1 &= ~TIM_CR1_OPM;
2691
2692   /* Configure the OPM Mode */
2693   htim->Instance->CR1 |= OnePulseMode;
2694
2695   /* Initialize the DMA burst operation state */
2696   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2697
2698   /* Initialize the TIM channels state */
2699   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2700   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2701   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2702   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2703
2704   /* Initialize the TIM state*/
2705   htim->State = HAL_TIM_STATE_READY;
2706
2707   return HAL_OK;
2708 }
2709
2710 /**
2711   * @brief  DeInitializes the TIM One Pulse
2712   * @param  htim TIM One Pulse handle
2713   * @retval HAL status
2714   */
2715 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2716 {
2717   /* Check the parameters */
2718   assert_param(IS_TIM_INSTANCE(htim->Instance));
2719
2720   htim->State = HAL_TIM_STATE_BUSY;
2721
2722   /* Disable the TIM Peripheral Clock */
2723   __HAL_TIM_DISABLE(htim);
2724
2725 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2726   if (htim->OnePulse_MspDeInitCallback == NULL)
2727   {
2728     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2729   }
2730   /* DeInit the low level hardware */
2731   htim->OnePulse_MspDeInitCallback(htim);
2732 #else
2733   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2734   HAL_TIM_OnePulse_MspDeInit(htim);
2735 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2736
2737   /* Change the DMA burst operation state */
2738   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2739
2740   /* Set the TIM channel state */
2741   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2742   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2743   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2744   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2745
2746   /* Change TIM state */
2747   htim->State = HAL_TIM_STATE_RESET;
2748
2749   /* Release Lock */
2750   __HAL_UNLOCK(htim);
2751
2752   return HAL_OK;
2753 }
2754
2755 /**
2756   * @brief  Initializes the TIM One Pulse MSP.
2757   * @param  htim TIM One Pulse handle
2758   * @retval None
2759   */
2760 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2761 {
2762   /* Prevent unused argument(s) compilation warning */
2763   UNUSED(htim);
2764
2765   /* NOTE : This function should not be modified, when the callback is needed,
2766             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2767    */
2768 }
2769
2770 /**
2771   * @brief  DeInitializes TIM One Pulse MSP.
2772   * @param  htim TIM One Pulse handle
2773   * @retval None
2774   */
2775 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2776 {
2777   /* Prevent unused argument(s) compilation warning */
2778   UNUSED(htim);
2779
2780   /* NOTE : This function should not be modified, when the callback is needed,
2781             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2782    */
2783 }
2784
2785 /**
2786   * @brief  Starts the TIM One Pulse signal generation.
2787   * @note Though OutputChannel parameter is deprecated and ignored by the function
2788   *        it has been kept to avoid HAL_TIM API compatibility break.
2789   * @note The pulse output channel is determined when calling
2790   *       @ref HAL_TIM_OnePulse_ConfigChannel().
2791   * @param  htim TIM One Pulse handle
2792   * @param  OutputChannel See note above
2793   * @retval HAL status
2794   */
2795 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2796 {
2797   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2798   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2799   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2800   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2801
2802   /* Prevent unused argument(s) compilation warning */
2803   UNUSED(OutputChannel);
2804
2805   /* Check the TIM channels state */
2806   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2807       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2808       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2809       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2810   {
2811     return HAL_ERROR;
2812   }
2813
2814   /* Set the TIM channels state */
2815   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2816   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2817   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2818   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2819
2820   /* Enable the Capture compare and the Input Capture channels
2821     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2822     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2823     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2824     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2825
2826     No need to enable the counter, it's enabled automatically by hardware
2827     (the counter starts in response to a stimulus and generate a pulse */
2828
2829   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2830   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2831
2832   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2833   {
2834     /* Enable the main output */
2835     __HAL_TIM_MOE_ENABLE(htim);
2836   }
2837
2838   /* Return function status */
2839   return HAL_OK;
2840 }
2841
2842 /**
2843   * @brief  Stops the TIM One Pulse signal generation.
2844   * @note Though OutputChannel parameter is deprecated and ignored by the function
2845   *        it has been kept to avoid HAL_TIM API compatibility break.
2846   * @note The pulse output channel is determined when calling
2847   *       @ref HAL_TIM_OnePulse_ConfigChannel().
2848   * @param  htim TIM One Pulse handle
2849   * @param  OutputChannel See note above
2850   * @retval HAL status
2851   */
2852 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2853 {
2854   /* Prevent unused argument(s) compilation warning */
2855   UNUSED(OutputChannel);
2856
2857   /* Disable the Capture compare and the Input Capture channels
2858   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2859   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2860   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2861   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2862
2863   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2864   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2865
2866   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2867   {
2868     /* Disable the Main Output */
2869     __HAL_TIM_MOE_DISABLE(htim);
2870   }
2871
2872   /* Disable the Peripheral */
2873   __HAL_TIM_DISABLE(htim);
2874
2875   /* Set the TIM channels state */
2876   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2877   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2878   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2879   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2880
2881   /* Return function status */
2882   return HAL_OK;
2883 }
2884
2885 /**
2886   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
2887   * @note Though OutputChannel parameter is deprecated and ignored by the function
2888   *        it has been kept to avoid HAL_TIM API compatibility break.
2889   * @note The pulse output channel is determined when calling
2890   *       @ref HAL_TIM_OnePulse_ConfigChannel().
2891   * @param  htim TIM One Pulse handle
2892   * @param  OutputChannel See note above
2893   * @retval HAL status
2894   */
2895 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2896 {
2897   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2898   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2899   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2900   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2901
2902   /* Prevent unused argument(s) compilation warning */
2903   UNUSED(OutputChannel);
2904
2905   /* Check the TIM channels state */
2906   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2907       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2908       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2909       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2910   {
2911     return HAL_ERROR;
2912   }
2913
2914   /* Set the TIM channels state */
2915   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2916   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2917   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2918   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2919
2920   /* Enable the Capture compare and the Input Capture channels
2921     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2922     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2923     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2924     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2925
2926     No need to enable the counter, it's enabled automatically by hardware
2927     (the counter starts in response to a stimulus and generate a pulse */
2928
2929   /* Enable the TIM Capture/Compare 1 interrupt */
2930   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2931
2932   /* Enable the TIM Capture/Compare 2 interrupt */
2933   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2934
2935   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2936   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2937
2938   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2939   {
2940     /* Enable the main output */
2941     __HAL_TIM_MOE_ENABLE(htim);
2942   }
2943
2944   /* Return function status */
2945   return HAL_OK;
2946 }
2947
2948 /**
2949   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
2950   * @note Though OutputChannel parameter is deprecated and ignored by the function
2951   *        it has been kept to avoid HAL_TIM API compatibility break.
2952   * @note The pulse output channel is determined when calling
2953   *       @ref HAL_TIM_OnePulse_ConfigChannel().
2954   * @param  htim TIM One Pulse handle
2955   * @param  OutputChannel See note above
2956   * @retval HAL status
2957   */
2958 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2959 {
2960   /* Prevent unused argument(s) compilation warning */
2961   UNUSED(OutputChannel);
2962
2963   /* Disable the TIM Capture/Compare 1 interrupt */
2964   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2965
2966   /* Disable the TIM Capture/Compare 2 interrupt */
2967   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2968
2969   /* Disable the Capture compare and the Input Capture channels
2970   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2971   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2972   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2973   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2974   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2975   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2976
2977   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2978   {
2979     /* Disable the Main Output */
2980     __HAL_TIM_MOE_DISABLE(htim);
2981   }
2982
2983   /* Disable the Peripheral */
2984   __HAL_TIM_DISABLE(htim);
2985
2986   /* Set the TIM channels state */
2987   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2988   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2989   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2990   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2991
2992   /* Return function status */
2993   return HAL_OK;
2994 }
2995
2996 /**
2997   * @}
2998   */
2999
3000 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
3001   * @ingroup RTEMSBSPsARMSTM32H7
3002   *  @brief    TIM Encoder functions
3003   *
3004 @verbatim
3005   ==============================================================================
3006                           ##### TIM Encoder functions #####
3007   ==============================================================================
3008   [..]
3009     This section provides functions allowing to:
3010     (+) Initialize and configure the TIM Encoder.
3011     (+) De-initialize the TIM Encoder.
3012     (+) Start the TIM Encoder.
3013     (+) Stop the TIM Encoder.
3014     (+) Start the TIM Encoder and enable interrupt.
3015     (+) Stop the TIM Encoder and disable interrupt.
3016     (+) Start the TIM Encoder and enable DMA transfer.
3017     (+) Stop the TIM Encoder and disable DMA transfer.
3018
3019 @endverbatim
3020   * @{
3021   */
3022 /**
3023   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
3024   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3025   *         requires a timer reset to avoid unexpected direction
3026   *         due to DIR bit readonly in center aligned mode.
3027   *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3028   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
3029   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3030   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3031   * @note   When the timer instance is initialized in Encoder mode, timer
3032   *         channels 1 and channel 2 are reserved and cannot be used for other
3033   *         purpose.
3034   * @param  htim TIM Encoder Interface handle
3035   * @param  sConfig TIM Encoder Interface configuration structure
3036   * @retval HAL status
3037   */
3038 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
3039 {
3040   uint32_t tmpsmcr;
3041   uint32_t tmpccmr1;
3042   uint32_t tmpccer;
3043
3044   /* Check the TIM handle allocation */
3045   if (htim == NULL)
3046   {
3047     return HAL_ERROR;
3048   }
3049
3050   /* Check the parameters */
3051   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3052   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3053   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3054   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3055   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3056   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3057   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3058   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3059   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3060   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3061   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3062   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3063   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3064   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
3065
3066   if (htim->State == HAL_TIM_STATE_RESET)
3067   {
3068     /* Allocate lock resource and initialize it */
3069     htim->Lock = HAL_UNLOCKED;
3070
3071 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3072     /* Reset interrupt callbacks to legacy weak callbacks */
3073     TIM_ResetCallback(htim);
3074
3075     if (htim->Encoder_MspInitCallback == NULL)
3076     {
3077       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3078     }
3079     /* Init the low level hardware : GPIO, CLOCK, NVIC */
3080     htim->Encoder_MspInitCallback(htim);
3081 #else
3082     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3083     HAL_TIM_Encoder_MspInit(htim);
3084 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3085   }
3086
3087   /* Set the TIM state */
3088   htim->State = HAL_TIM_STATE_BUSY;
3089
3090   /* Reset the SMS and ECE bits */
3091   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3092
3093   /* Configure the Time base in the Encoder Mode */
3094   TIM_Base_SetConfig(htim->Instance, &htim->Init);
3095
3096   /* Get the TIMx SMCR register value */
3097   tmpsmcr = htim->Instance->SMCR;
3098
3099   /* Get the TIMx CCMR1 register value */
3100   tmpccmr1 = htim->Instance->CCMR1;
3101
3102   /* Get the TIMx CCER register value */
3103   tmpccer = htim->Instance->CCER;
3104
3105   /* Set the encoder Mode */
3106   tmpsmcr |= sConfig->EncoderMode;
3107
3108   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3109   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3110   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3111
3112   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3113   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3114   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3115   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3116   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3117
3118   /* Set the TI1 and the TI2 Polarities */
3119   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3120   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3121   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3122
3123   /* Write to TIMx SMCR */
3124   htim->Instance->SMCR = tmpsmcr;
3125
3126   /* Write to TIMx CCMR1 */
3127   htim->Instance->CCMR1 = tmpccmr1;
3128
3129   /* Write to TIMx CCER */
3130   htim->Instance->CCER = tmpccer;
3131
3132   /* Initialize the DMA burst operation state */
3133   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3134
3135   /* Set the TIM channels state */
3136   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3137   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3138   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3139   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3140
3141   /* Initialize the TIM state*/
3142   htim->State = HAL_TIM_STATE_READY;
3143
3144   return HAL_OK;
3145 }
3146
3147
3148 /**
3149   * @brief  DeInitializes the TIM Encoder interface
3150   * @param  htim TIM Encoder Interface handle
3151   * @retval HAL status
3152   */
3153 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3154 {
3155   /* Check the parameters */
3156   assert_param(IS_TIM_INSTANCE(htim->Instance));
3157
3158   htim->State = HAL_TIM_STATE_BUSY;
3159
3160   /* Disable the TIM Peripheral Clock */
3161   __HAL_TIM_DISABLE(htim);
3162
3163 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3164   if (htim->Encoder_MspDeInitCallback == NULL)
3165   {
3166     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3167   }
3168   /* DeInit the low level hardware */
3169   htim->Encoder_MspDeInitCallback(htim);
3170 #else
3171   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3172   HAL_TIM_Encoder_MspDeInit(htim);
3173 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3174
3175   /* Change the DMA burst operation state */
3176   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3177
3178   /* Set the TIM channels state */
3179   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3180   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3181   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3182   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3183
3184   /* Change TIM state */
3185   htim->State = HAL_TIM_STATE_RESET;
3186
3187   /* Release Lock */
3188   __HAL_UNLOCK(htim);
3189
3190   return HAL_OK;
3191 }
3192
3193 /**
3194   * @brief  Initializes the TIM Encoder Interface MSP.
3195   * @param  htim TIM Encoder Interface handle
3196   * @retval None
3197   */
3198 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3199 {
3200   /* Prevent unused argument(s) compilation warning */
3201   UNUSED(htim);
3202
3203   /* NOTE : This function should not be modified, when the callback is needed,
3204             the HAL_TIM_Encoder_MspInit could be implemented in the user file
3205    */
3206 }
3207
3208 /**
3209   * @brief  DeInitializes TIM Encoder Interface MSP.
3210   * @param  htim TIM Encoder Interface handle
3211   * @retval None
3212   */
3213 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3214 {
3215   /* Prevent unused argument(s) compilation warning */
3216   UNUSED(htim);
3217
3218   /* NOTE : This function should not be modified, when the callback is needed,
3219             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3220    */
3221 }
3222
3223 /**
3224   * @brief  Starts the TIM Encoder Interface.
3225   * @param  htim TIM Encoder Interface handle
3226   * @param  Channel TIM Channels to be enabled
3227   *          This parameter can be one of the following values:
3228   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3229   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3230   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3231   * @retval HAL status
3232   */
3233 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3234 {
3235   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3236   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3237   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3238   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3239
3240   /* Check the parameters */
3241   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3242
3243   /* Set the TIM channel(s) state */
3244   if (Channel == TIM_CHANNEL_1)
3245   {
3246     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3247         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3248     {
3249       return HAL_ERROR;
3250     }
3251     else
3252     {
3253       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3254       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3255     }
3256   }
3257   else if (Channel == TIM_CHANNEL_2)
3258   {
3259     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3260         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3261     {
3262       return HAL_ERROR;
3263     }
3264     else
3265     {
3266       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3267       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3268     }
3269   }
3270   else
3271   {
3272     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3273         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3274         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3275         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3276     {
3277       return HAL_ERROR;
3278     }
3279     else
3280     {
3281       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3282       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3283       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3284       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3285     }
3286   }
3287
3288   /* Enable the encoder interface channels */
3289   switch (Channel)
3290   {
3291     case TIM_CHANNEL_1:
3292     {
3293       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3294       break;
3295     }
3296
3297     case TIM_CHANNEL_2:
3298     {
3299       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3300       break;
3301     }
3302
3303     default :
3304     {
3305       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3306       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3307       break;
3308     }
3309   }
3310   /* Enable the Peripheral */
3311   __HAL_TIM_ENABLE(htim);
3312
3313   /* Return function status */
3314   return HAL_OK;
3315 }
3316
3317 /**
3318   * @brief  Stops the TIM Encoder Interface.
3319   * @param  htim TIM Encoder Interface handle
3320   * @param  Channel TIM Channels to be disabled
3321   *          This parameter can be one of the following values:
3322   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3323   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3324   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3325   * @retval HAL status
3326   */
3327 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3328 {
3329   /* Check the parameters */
3330   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3331
3332   /* Disable the Input Capture channels 1 and 2
3333     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3334   switch (Channel)
3335   {
3336     case TIM_CHANNEL_1:
3337     {
3338       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3339       break;
3340     }
3341
3342     case TIM_CHANNEL_2:
3343     {
3344       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3345       break;
3346     }
3347
3348     default :
3349     {
3350       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3351       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3352       break;
3353     }
3354   }
3355
3356   /* Disable the Peripheral */
3357   __HAL_TIM_DISABLE(htim);
3358
3359   /* Set the TIM channel(s) state */
3360   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3361   {
3362     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3363     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3364   }
3365   else
3366   {
3367     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3368     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3369     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3370     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3371   }
3372
3373   /* Return function status */
3374   return HAL_OK;
3375 }
3376
3377 /**
3378   * @brief  Starts the TIM Encoder Interface in interrupt mode.
3379   * @param  htim TIM Encoder Interface handle
3380   * @param  Channel TIM Channels to be enabled
3381   *          This parameter can be one of the following values:
3382   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3383   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3384   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3385   * @retval HAL status
3386   */
3387 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3388 {
3389   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3390   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3391   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3392   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3393
3394   /* Check the parameters */
3395   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3396
3397   /* Set the TIM channel(s) state */
3398   if (Channel == TIM_CHANNEL_1)
3399   {
3400     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3401         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3402     {
3403       return HAL_ERROR;
3404     }
3405     else
3406     {
3407       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3408       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3409     }
3410   }
3411   else if (Channel == TIM_CHANNEL_2)
3412   {
3413     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3414         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3415     {
3416       return HAL_ERROR;
3417     }
3418     else
3419     {
3420       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3421       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3422     }
3423   }
3424   else
3425   {
3426     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3427         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3428         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3429         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3430     {
3431       return HAL_ERROR;
3432     }
3433     else
3434     {
3435       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3436       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3437       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3438       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3439     }
3440   }
3441
3442   /* Enable the encoder interface channels */
3443   /* Enable the capture compare Interrupts 1 and/or 2 */
3444   switch (Channel)
3445   {
3446     case TIM_CHANNEL_1:
3447     {
3448       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3449       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3450       break;
3451     }
3452
3453     case TIM_CHANNEL_2:
3454     {
3455       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3456       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3457       break;
3458     }
3459
3460     default :
3461     {
3462       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3463       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3464       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3465       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3466       break;
3467     }
3468   }
3469
3470   /* Enable the Peripheral */
3471   __HAL_TIM_ENABLE(htim);
3472
3473   /* Return function status */
3474   return HAL_OK;
3475 }
3476
3477 /**
3478   * @brief  Stops the TIM Encoder Interface in interrupt mode.
3479   * @param  htim TIM Encoder Interface handle
3480   * @param  Channel TIM Channels to be disabled
3481   *          This parameter can be one of the following values:
3482   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3483   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3484   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3485   * @retval HAL status
3486   */
3487 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3488 {
3489   /* Check the parameters */
3490   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3491
3492   /* Disable the Input Capture channels 1 and 2
3493     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3494   if (Channel == TIM_CHANNEL_1)
3495   {
3496     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3497
3498     /* Disable the capture compare Interrupts 1 */
3499     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3500   }
3501   else if (Channel == TIM_CHANNEL_2)
3502   {
3503     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3504
3505     /* Disable the capture compare Interrupts 2 */
3506     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3507   }
3508   else
3509   {
3510     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3511     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3512
3513     /* Disable the capture compare Interrupts 1 and 2 */
3514     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3515     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3516   }
3517
3518   /* Disable the Peripheral */
3519   __HAL_TIM_DISABLE(htim);
3520
3521   /* Set the TIM channel(s) state */
3522   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3523   {
3524     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3525     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3526   }
3527   else
3528   {
3529     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3530     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3531     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3532     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3533   }
3534
3535   /* Return function status */
3536   return HAL_OK;
3537 }
3538
3539 /**
3540   * @brief  Starts the TIM Encoder Interface in DMA mode.
3541   * @param  htim TIM Encoder Interface handle
3542   * @param  Channel TIM Channels to be enabled
3543   *          This parameter can be one of the following values:
3544   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3545   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3546   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3547   * @param  pData1 The destination Buffer address for IC1.
3548   * @param  pData2 The destination Buffer address for IC2.
3549   * @param  Length The length of data to be transferred from TIM peripheral to memory.
3550   * @retval HAL status
3551   */
3552 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3553                                             uint32_t *pData2, uint16_t Length)
3554 {
3555   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3556   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3557   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3558   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3559
3560   /* Check the parameters */
3561   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3562
3563   /* Set the TIM channel(s) state */
3564   if (Channel == TIM_CHANNEL_1)
3565   {
3566     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3567         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3568     {
3569       return HAL_BUSY;
3570     }
3571     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3572              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3573     {
3574       if ((pData1 == NULL) || (Length == 0U))
3575       {
3576         return HAL_ERROR;
3577       }
3578       else
3579       {
3580         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3581         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3582       }
3583     }
3584     else
3585     {
3586       return HAL_ERROR;
3587     }
3588   }
3589   else if (Channel == TIM_CHANNEL_2)
3590   {
3591     if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3592         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3593     {
3594       return HAL_BUSY;
3595     }
3596     else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3597              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3598     {
3599       if ((pData2 == NULL) || (Length == 0U))
3600       {
3601         return HAL_ERROR;
3602       }
3603       else
3604       {
3605         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3606         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3607       }
3608     }
3609     else
3610     {
3611       return HAL_ERROR;
3612     }
3613   }
3614   else
3615   {
3616     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3617         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3618         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3619         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3620     {
3621       return HAL_BUSY;
3622     }
3623     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3624              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3625              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3626              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3627     {
3628       if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3629       {
3630         return HAL_ERROR;
3631       }
3632       else
3633       {
3634         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3635         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3636         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3637         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3638       }
3639     }
3640     else
3641     {
3642       return HAL_ERROR;
3643     }
3644   }
3645
3646   switch (Channel)
3647   {
3648     case TIM_CHANNEL_1:
3649     {
3650       /* Set the DMA capture callbacks */
3651       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3652       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3653
3654       /* Set the DMA error callback */
3655       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3656
3657       /* Enable the DMA stream */
3658       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3659                            Length) != HAL_OK)
3660       {
3661         /* Return error status */
3662         return HAL_ERROR;
3663       }
3664       /* Enable the TIM Input Capture DMA request */
3665       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3666
3667       /* Enable the Capture compare channel */
3668       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3669
3670       /* Enable the Peripheral */
3671       __HAL_TIM_ENABLE(htim);
3672
3673       break;
3674     }
3675
3676     case TIM_CHANNEL_2:
3677     {
3678       /* Set the DMA capture callbacks */
3679       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3680       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3681
3682       /* Set the DMA error callback */
3683       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3684       /* Enable the DMA stream */
3685       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3686                            Length) != HAL_OK)
3687       {
3688         /* Return error status */
3689         return HAL_ERROR;
3690       }
3691       /* Enable the TIM Input Capture  DMA request */
3692       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3693
3694       /* Enable the Capture compare channel */
3695       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3696
3697       /* Enable the Peripheral */
3698       __HAL_TIM_ENABLE(htim);
3699
3700       break;
3701     }
3702
3703     default:
3704     {
3705       /* Set the DMA capture callbacks */
3706       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3707       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3708
3709       /* Set the DMA error callback */
3710       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3711
3712       /* Enable the DMA stream */
3713       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3714                            Length) != HAL_OK)
3715       {
3716         /* Return error status */
3717         return HAL_ERROR;
3718       }
3719
3720       /* Set the DMA capture callbacks */
3721       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3722       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3723
3724       /* Set the DMA error callback */
3725       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3726
3727       /* Enable the DMA stream */
3728       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3729                            Length) != HAL_OK)
3730       {
3731         /* Return error status */
3732         return HAL_ERROR;
3733       }
3734
3735       /* Enable the TIM Input Capture  DMA request */
3736       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3737       /* Enable the TIM Input Capture  DMA request */
3738       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3739
3740       /* Enable the Capture compare channel */
3741       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3742       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3743
3744       /* Enable the Peripheral */
3745       __HAL_TIM_ENABLE(htim);
3746
3747       break;
3748     }
3749   }
3750
3751   /* Return function status */
3752   return HAL_OK;
3753 }
3754
3755 /**
3756   * @brief  Stops the TIM Encoder Interface in DMA mode.
3757   * @param  htim TIM Encoder Interface handle
3758   * @param  Channel TIM Channels to be enabled
3759   *          This parameter can be one of the following values:
3760   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3761   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3762   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3763   * @retval HAL status
3764   */
3765 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3766 {
3767   /* Check the parameters */
3768   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3769
3770   /* Disable the Input Capture channels 1 and 2
3771     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3772   if (Channel == TIM_CHANNEL_1)
3773   {
3774     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3775
3776     /* Disable the capture compare DMA Request 1 */
3777     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3778     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3779   }
3780   else if (Channel == TIM_CHANNEL_2)
3781   {
3782     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3783
3784     /* Disable the capture compare DMA Request 2 */
3785     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3786     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3787   }
3788   else
3789   {
3790     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3791     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3792
3793     /* Disable the capture compare DMA Request 1 and 2 */
3794     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3795     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3796     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3797     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3798   }
3799
3800   /* Disable the Peripheral */
3801   __HAL_TIM_DISABLE(htim);
3802
3803   /* Set the TIM channel(s) state */
3804   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3805   {
3806     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3807     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3808   }
3809   else
3810   {
3811     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3812     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3813     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3814     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3815   }
3816
3817   /* Return function status */
3818   return HAL_OK;
3819 }
3820
3821 /**
3822   * @}
3823   */
3824 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3825   * @ingroup RTEMSBSPsARMSTM32H7
3826   *  @brief    TIM IRQ handler management
3827   *
3828 @verbatim
3829   ==============================================================================
3830                         ##### IRQ handler management #####
3831   ==============================================================================
3832   [..]
3833     This section provides Timer IRQ handler function.
3834
3835 @endverbatim
3836   * @{
3837   */
3838 /**
3839   * @brief  This function handles TIM interrupts requests.
3840   * @param  htim TIM  handle
3841   * @retval None
3842   */
3843 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3844 {
3845   uint32_t itsource = htim->Instance->DIER;
3846   uint32_t itflag   = htim->Instance->SR;
3847
3848   /* Capture compare 1 event */
3849   if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
3850   {
3851     if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
3852     {
3853       {
3854         __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
3855         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3856
3857         /* Input capture event */
3858         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3859         {
3860 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3861           htim->IC_CaptureCallback(htim);
3862 #else
3863           HAL_TIM_IC_CaptureCallback(htim);
3864 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3865         }
3866         /* Output compare event */
3867         else
3868         {
3869 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3870           htim->OC_DelayElapsedCallback(htim);
3871           htim->PWM_PulseFinishedCallback(htim);
3872 #else
3873           HAL_TIM_OC_DelayElapsedCallback(htim);
3874           HAL_TIM_PWM_PulseFinishedCallback(htim);
3875 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3876         }
3877         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3878       }
3879     }
3880   }
3881   /* Capture compare 2 event */
3882   if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
3883   {
3884     if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
3885     {
3886       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
3887       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3888       /* Input capture event */
3889       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3890       {
3891 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3892         htim->IC_CaptureCallback(htim);
3893 #else
3894         HAL_TIM_IC_CaptureCallback(htim);
3895 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3896       }
3897       /* Output compare event */
3898       else
3899       {
3900 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3901         htim->OC_DelayElapsedCallback(htim);
3902         htim->PWM_PulseFinishedCallback(htim);
3903 #else
3904         HAL_TIM_OC_DelayElapsedCallback(htim);
3905         HAL_TIM_PWM_PulseFinishedCallback(htim);
3906 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3907       }
3908       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3909     }
3910   }
3911   /* Capture compare 3 event */
3912   if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
3913   {
3914     if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
3915     {
3916       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
3917       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3918       /* Input capture event */
3919       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3920       {
3921 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3922         htim->IC_CaptureCallback(htim);
3923 #else
3924         HAL_TIM_IC_CaptureCallback(htim);
3925 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3926       }
3927       /* Output compare event */
3928       else
3929       {
3930 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3931         htim->OC_DelayElapsedCallback(htim);
3932         htim->PWM_PulseFinishedCallback(htim);
3933 #else
3934         HAL_TIM_OC_DelayElapsedCallback(htim);
3935         HAL_TIM_PWM_PulseFinishedCallback(htim);
3936 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3937       }
3938       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3939     }
3940   }
3941   /* Capture compare 4 event */
3942   if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
3943   {
3944     if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
3945     {
3946       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
3947       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3948       /* Input capture event */
3949       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3950       {
3951 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3952         htim->IC_CaptureCallback(htim);
3953 #else
3954         HAL_TIM_IC_CaptureCallback(htim);
3955 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3956       }
3957       /* Output compare event */
3958       else
3959       {
3960 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3961         htim->OC_DelayElapsedCallback(htim);
3962         htim->PWM_PulseFinishedCallback(htim);
3963 #else
3964         HAL_TIM_OC_DelayElapsedCallback(htim);
3965         HAL_TIM_PWM_PulseFinishedCallback(htim);
3966 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3967       }
3968       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3969     }
3970   }
3971   /* TIM Update event */
3972   if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
3973   {
3974     if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
3975     {
3976       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
3977 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3978       htim->PeriodElapsedCallback(htim);
3979 #else
3980       HAL_TIM_PeriodElapsedCallback(htim);
3981 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3982     }
3983   }
3984   /* TIM Break input event */
3985   if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
3986       ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
3987   {
3988     if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
3989     {
3990       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
3991 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3992       htim->BreakCallback(htim);
3993 #else
3994       HAL_TIMEx_BreakCallback(htim);
3995 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3996     }
3997   }
3998   /* TIM Break2 input event */
3999   if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
4000   {
4001     if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
4002     {
4003       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
4004 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4005       htim->Break2Callback(htim);
4006 #else
4007       HAL_TIMEx_Break2Callback(htim);
4008 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4009     }
4010   }
4011   /* TIM Trigger detection event */
4012   if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
4013   {
4014     if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
4015     {
4016       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
4017 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4018       htim->TriggerCallback(htim);
4019 #else
4020       HAL_TIM_TriggerCallback(htim);
4021 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4022     }
4023   }
4024   /* TIM commutation event */
4025   if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
4026   {
4027     if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
4028     {
4029       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
4030 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4031       htim->CommutationCallback(htim);
4032 #else
4033       HAL_TIMEx_CommutCallback(htim);
4034 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4035     }
4036   }
4037 }
4038
4039 /**
4040   * @}
4041   */
4042
4043 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4044   * @ingroup RTEMSBSPsARMSTM32H7
4045   *  @brief    TIM Peripheral Control functions
4046   *
4047 @verbatim
4048   ==============================================================================
4049                    ##### Peripheral Control functions #####
4050   ==============================================================================
4051  [..]
4052    This section provides functions allowing to:
4053       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4054       (+) Configure External Clock source.
4055       (+) Configure Complementary channels, break features and dead time.
4056       (+) Configure Master and the Slave synchronization.
4057       (+) Configure the DMA Burst Mode.
4058
4059 @endverbatim
4060   * @{
4061   */
4062
4063 /**
4064   * @brief  Initializes the TIM Output Compare Channels according to the specified
4065   *         parameters in the TIM_OC_InitTypeDef.
4066   * @param  htim TIM Output Compare handle
4067   * @param  sConfig TIM Output Compare configuration structure
4068   * @param  Channel TIM Channels to configure
4069   *          This parameter can be one of the following values:
4070   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
4071   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
4072   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
4073   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
4074   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
4075   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
4076   * @retval HAL status
4077   */
4078 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4079                                            const TIM_OC_InitTypeDef *sConfig,
4080                                            uint32_t Channel)
4081 {
4082   HAL_StatusTypeDef status = HAL_OK;
4083
4084   /* Check the parameters */
4085   assert_param(IS_TIM_CHANNELS(Channel));
4086   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
4087   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4088
4089   /* Process Locked */
4090   __HAL_LOCK(htim);
4091
4092   switch (Channel)
4093   {
4094     case TIM_CHANNEL_1:
4095     {
4096       /* Check the parameters */
4097       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4098
4099       /* Configure the TIM Channel 1 in Output Compare */
4100       TIM_OC1_SetConfig(htim->Instance, sConfig);
4101       break;
4102     }
4103
4104     case TIM_CHANNEL_2:
4105     {
4106       /* Check the parameters */
4107       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4108
4109       /* Configure the TIM Channel 2 in Output Compare */
4110       TIM_OC2_SetConfig(htim->Instance, sConfig);
4111       break;
4112     }
4113
4114     case TIM_CHANNEL_3:
4115     {
4116       /* Check the parameters */
4117       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4118
4119       /* Configure the TIM Channel 3 in Output Compare */
4120       TIM_OC3_SetConfig(htim->Instance, sConfig);
4121       break;
4122     }
4123
4124     case TIM_CHANNEL_4:
4125     {
4126       /* Check the parameters */
4127       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4128
4129       /* Configure the TIM Channel 4 in Output Compare */
4130       TIM_OC4_SetConfig(htim->Instance, sConfig);
4131       break;
4132     }
4133
4134     case TIM_CHANNEL_5:
4135     {
4136       /* Check the parameters */
4137       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4138
4139       /* Configure the TIM Channel 5 in Output Compare */
4140       TIM_OC5_SetConfig(htim->Instance, sConfig);
4141       break;
4142     }
4143
4144     case TIM_CHANNEL_6:
4145     {
4146       /* Check the parameters */
4147       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4148
4149       /* Configure the TIM Channel 6 in Output Compare */
4150       TIM_OC6_SetConfig(htim->Instance, sConfig);
4151       break;
4152     }
4153
4154     default:
4155       status = HAL_ERROR;
4156       break;
4157   }
4158
4159   __HAL_UNLOCK(htim);
4160
4161   return status;
4162 }
4163
4164 /**
4165   * @brief  Initializes the TIM Input Capture Channels according to the specified
4166   *         parameters in the TIM_IC_InitTypeDef.
4167   * @param  htim TIM IC handle
4168   * @param  sConfig TIM Input Capture configuration structure
4169   * @param  Channel TIM Channel to configure
4170   *          This parameter can be one of the following values:
4171   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
4172   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
4173   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
4174   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
4175   * @retval HAL status
4176   */
4177 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4178 {
4179   HAL_StatusTypeDef status = HAL_OK;
4180
4181   /* Check the parameters */
4182   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4183   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4184   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4185   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4186   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4187
4188   /* Process Locked */
4189   __HAL_LOCK(htim);
4190
4191   if (Channel == TIM_CHANNEL_1)
4192   {
4193     /* TI1 Configuration */
4194     TIM_TI1_SetConfig(htim->Instance,
4195                       sConfig->ICPolarity,
4196                       sConfig->ICSelection,
4197                       sConfig->ICFilter);
4198
4199     /* Reset the IC1PSC Bits */
4200     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4201
4202     /* Set the IC1PSC value */
4203     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4204   }
4205   else if (Channel == TIM_CHANNEL_2)
4206   {
4207     /* TI2 Configuration */
4208     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4209
4210     TIM_TI2_SetConfig(htim->Instance,
4211                       sConfig->ICPolarity,
4212                       sConfig->ICSelection,
4213                       sConfig->ICFilter);
4214
4215     /* Reset the IC2PSC Bits */
4216     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4217
4218     /* Set the IC2PSC value */
4219     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4220   }
4221   else if (Channel == TIM_CHANNEL_3)
4222   {
4223     /* TI3 Configuration */
4224     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4225
4226     TIM_TI3_SetConfig(htim->Instance,
4227                       sConfig->ICPolarity,
4228                       sConfig->ICSelection,
4229                       sConfig->ICFilter);
4230
4231     /* Reset the IC3PSC Bits */
4232     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4233
4234     /* Set the IC3PSC value */
4235     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4236   }
4237   else if (Channel == TIM_CHANNEL_4)
4238   {
4239     /* TI4 Configuration */
4240     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4241
4242     TIM_TI4_SetConfig(htim->Instance,
4243                       sConfig->ICPolarity,
4244                       sConfig->ICSelection,
4245                       sConfig->ICFilter);
4246
4247     /* Reset the IC4PSC Bits */
4248     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4249
4250     /* Set the IC4PSC value */
4251     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4252   }
4253   else
4254   {
4255     status = HAL_ERROR;
4256   }
4257
4258   __HAL_UNLOCK(htim);
4259
4260   return status;
4261 }
4262
4263 /**
4264   * @brief  Initializes the TIM PWM  channels according to the specified
4265   *         parameters in the TIM_OC_InitTypeDef.
4266   * @param  htim TIM PWM handle
4267   * @param  sConfig TIM PWM configuration structure
4268   * @param  Channel TIM Channels to be configured
4269   *          This parameter can be one of the following values:
4270   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
4271   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
4272   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
4273   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
4274   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
4275   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
4276   * @retval HAL status
4277   */
4278 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4279                                             const TIM_OC_InitTypeDef *sConfig,
4280                                             uint32_t Channel)
4281 {
4282   HAL_StatusTypeDef status = HAL_OK;
4283
4284   /* Check the parameters */
4285   assert_param(IS_TIM_CHANNELS(Channel));
4286   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4287   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4288   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4289
4290   /* Process Locked */
4291   __HAL_LOCK(htim);
4292
4293   switch (Channel)
4294   {
4295     case TIM_CHANNEL_1:
4296     {
4297       /* Check the parameters */
4298       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4299
4300       /* Configure the Channel 1 in PWM mode */
4301       TIM_OC1_SetConfig(htim->Instance, sConfig);
4302
4303       /* Set the Preload enable bit for channel1 */
4304       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4305
4306       /* Configure the Output Fast mode */
4307       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4308       htim->Instance->CCMR1 |= sConfig->OCFastMode;
4309       break;
4310     }
4311
4312     case TIM_CHANNEL_2:
4313     {
4314       /* Check the parameters */
4315       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4316
4317       /* Configure the Channel 2 in PWM mode */
4318       TIM_OC2_SetConfig(htim->Instance, sConfig);
4319
4320       /* Set the Preload enable bit for channel2 */
4321       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4322
4323       /* Configure the Output Fast mode */
4324       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4325       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4326       break;
4327     }
4328
4329     case TIM_CHANNEL_3:
4330     {
4331       /* Check the parameters */
4332       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4333
4334       /* Configure the Channel 3 in PWM mode */
4335       TIM_OC3_SetConfig(htim->Instance, sConfig);
4336
4337       /* Set the Preload enable bit for channel3 */
4338       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4339
4340       /* Configure the Output Fast mode */
4341       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4342       htim->Instance->CCMR2 |= sConfig->OCFastMode;
4343       break;
4344     }
4345
4346     case TIM_CHANNEL_4:
4347     {
4348       /* Check the parameters */
4349       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4350
4351       /* Configure the Channel 4 in PWM mode */
4352       TIM_OC4_SetConfig(htim->Instance, sConfig);
4353
4354       /* Set the Preload enable bit for channel4 */
4355       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4356
4357       /* Configure the Output Fast mode */
4358       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4359       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4360       break;
4361     }
4362
4363     case TIM_CHANNEL_5:
4364     {
4365       /* Check the parameters */
4366       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4367
4368       /* Configure the Channel 5 in PWM mode */
4369       TIM_OC5_SetConfig(htim->Instance, sConfig);
4370
4371       /* Set the Preload enable bit for channel5*/
4372       htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
4373
4374       /* Configure the Output Fast mode */
4375       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
4376       htim->Instance->CCMR3 |= sConfig->OCFastMode;
4377       break;
4378     }
4379
4380     case TIM_CHANNEL_6:
4381     {
4382       /* Check the parameters */
4383       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4384
4385       /* Configure the Channel 6 in PWM mode */
4386       TIM_OC6_SetConfig(htim->Instance, sConfig);
4387
4388       /* Set the Preload enable bit for channel6 */
4389       htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
4390
4391       /* Configure the Output Fast mode */
4392       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
4393       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
4394       break;
4395     }
4396
4397     default:
4398       status = HAL_ERROR;
4399       break;
4400   }
4401
4402   __HAL_UNLOCK(htim);
4403
4404   return status;
4405 }
4406
4407 /**
4408   * @brief  Initializes the TIM One Pulse Channels according to the specified
4409   *         parameters in the TIM_OnePulse_InitTypeDef.
4410   * @param  htim TIM One Pulse handle
4411   * @param  sConfig TIM One Pulse configuration structure
4412   * @param  OutputChannel TIM output channel to configure
4413   *          This parameter can be one of the following values:
4414   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
4415   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
4416   * @param  InputChannel TIM input Channel to configure
4417   *          This parameter can be one of the following values:
4418   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
4419   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
4420   * @note  To output a waveform with a minimum delay user can enable the fast
4421   *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4422   *        output is forced in response to the edge detection on TIx input,
4423   *        without taking in account the comparison.
4424   * @retval HAL status
4425   */
4426 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
4427                                                  uint32_t OutputChannel,  uint32_t InputChannel)
4428 {
4429   HAL_StatusTypeDef status = HAL_OK;
4430   TIM_OC_InitTypeDef temp1;
4431
4432   /* Check the parameters */
4433   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4434   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4435
4436   if (OutputChannel != InputChannel)
4437   {
4438     /* Process Locked */
4439     __HAL_LOCK(htim);
4440
4441     htim->State = HAL_TIM_STATE_BUSY;
4442
4443     /* Extract the Output compare configuration from sConfig structure */
4444     temp1.OCMode = sConfig->OCMode;
4445     temp1.Pulse = sConfig->Pulse;
4446     temp1.OCPolarity = sConfig->OCPolarity;
4447     temp1.OCNPolarity = sConfig->OCNPolarity;
4448     temp1.OCIdleState = sConfig->OCIdleState;
4449     temp1.OCNIdleState = sConfig->OCNIdleState;
4450
4451     switch (OutputChannel)
4452     {
4453       case TIM_CHANNEL_1:
4454       {
4455         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4456
4457         TIM_OC1_SetConfig(htim->Instance, &temp1);
4458         break;
4459       }
4460
4461       case TIM_CHANNEL_2:
4462       {
4463         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4464
4465         TIM_OC2_SetConfig(htim->Instance, &temp1);
4466         break;
4467       }
4468
4469       default:
4470         status = HAL_ERROR;
4471         break;
4472     }
4473
4474     if (status == HAL_OK)
4475     {
4476       switch (InputChannel)
4477       {
4478         case TIM_CHANNEL_1:
4479         {
4480           assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4481
4482           TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4483                             sConfig->ICSelection, sConfig->ICFilter);
4484
4485           /* Reset the IC1PSC Bits */
4486           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4487
4488           /* Select the Trigger source */
4489           htim->Instance->SMCR &= ~TIM_SMCR_TS;
4490           htim->Instance->SMCR |= TIM_TS_TI1FP1;
4491
4492           /* Select the Slave Mode */
4493           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4494           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4495           break;
4496         }
4497
4498         case TIM_CHANNEL_2:
4499         {
4500           assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4501
4502           TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4503                             sConfig->ICSelection, sConfig->ICFilter);
4504
4505           /* Reset the IC2PSC Bits */
4506           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4507
4508           /* Select the Trigger source */
4509           htim->Instance->SMCR &= ~TIM_SMCR_TS;
4510           htim->Instance->SMCR |= TIM_TS_TI2FP2;
4511
4512           /* Select the Slave Mode */
4513           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4514           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4515           break;
4516         }
4517
4518         default:
4519           status = HAL_ERROR;
4520           break;
4521       }
4522     }
4523
4524     htim->State = HAL_TIM_STATE_READY;
4525
4526     __HAL_UNLOCK(htim);
4527
4528     return status;
4529   }
4530   else
4531   {
4532     return HAL_ERROR;
4533   }
4534 }
4535
4536 /**
4537   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4538   * @param  htim TIM handle
4539   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
4540   *         This parameter can be one of the following values:
4541   *            @arg TIM_DMABASE_CR1
4542   *            @arg TIM_DMABASE_CR2
4543   *            @arg TIM_DMABASE_SMCR
4544   *            @arg TIM_DMABASE_DIER
4545   *            @arg TIM_DMABASE_SR
4546   *            @arg TIM_DMABASE_EGR
4547   *            @arg TIM_DMABASE_CCMR1
4548   *            @arg TIM_DMABASE_CCMR2
4549   *            @arg TIM_DMABASE_CCER
4550   *            @arg TIM_DMABASE_CNT
4551   *            @arg TIM_DMABASE_PSC
4552   *            @arg TIM_DMABASE_ARR
4553   *            @arg TIM_DMABASE_RCR
4554   *            @arg TIM_DMABASE_CCR1
4555   *            @arg TIM_DMABASE_CCR2
4556   *            @arg TIM_DMABASE_CCR3
4557   *            @arg TIM_DMABASE_CCR4
4558   *            @arg TIM_DMABASE_BDTR
4559   *            @arg TIM_DMABASE_CCMR3
4560   *            @arg TIM_DMABASE_CCR5
4561   *            @arg TIM_DMABASE_CCR6
4562   *            @arg TIM_DMABASE_AF1
4563   *            @arg TIM_DMABASE_AF2
4564   *            @arg TIM_DMABASE_TISEL
4565   *
4566   * @param  BurstRequestSrc TIM DMA Request sources
4567   *         This parameter can be one of the following values:
4568   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
4569   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4570   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4571   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4572   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4573   *            @arg TIM_DMA_COM: TIM Commutation DMA source
4574   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4575   * @param  BurstBuffer The Buffer address.
4576   * @param  BurstLength DMA Burst length. This parameter can be one value
4577   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4578   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
4579   * @retval HAL status
4580   */
4581 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4582                                               uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4583                                               uint32_t  BurstLength)
4584 {
4585   HAL_StatusTypeDef status;
4586
4587   status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4588                                             ((BurstLength) >> 8U) + 1U);
4589
4590
4591
4592   return status;
4593 }
4594
4595 /**
4596   * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4597   * @param  htim TIM handle
4598   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
4599   *         This parameter can be one of the following values:
4600   *            @arg TIM_DMABASE_CR1
4601   *            @arg TIM_DMABASE_CR2
4602   *            @arg TIM_DMABASE_SMCR
4603   *            @arg TIM_DMABASE_DIER
4604   *            @arg TIM_DMABASE_SR
4605   *            @arg TIM_DMABASE_EGR
4606   *            @arg TIM_DMABASE_CCMR1
4607   *            @arg TIM_DMABASE_CCMR2
4608   *            @arg TIM_DMABASE_CCER
4609   *            @arg TIM_DMABASE_CNT
4610   *            @arg TIM_DMABASE_PSC
4611   *            @arg TIM_DMABASE_ARR
4612   *            @arg TIM_DMABASE_RCR
4613   *            @arg TIM_DMABASE_CCR1
4614   *            @arg TIM_DMABASE_CCR2
4615   *            @arg TIM_DMABASE_CCR3
4616   *            @arg TIM_DMABASE_CCR4
4617   *            @arg TIM_DMABASE_BDTR
4618   *            @arg TIM_DMABASE_CCMR3
4619   *            @arg TIM_DMABASE_CCR5
4620   *            @arg TIM_DMABASE_CCR6
4621   *            @arg TIM_DMABASE_AF1
4622   *            @arg TIM_DMABASE_AF2
4623   *            @arg TIM_DMABASE_TISEL
4624   *
4625   * @param  BurstRequestSrc TIM DMA Request sources
4626   *         This parameter can be one of the following values:
4627   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
4628   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4629   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4630   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4631   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4632   *            @arg TIM_DMA_COM: TIM Commutation DMA source
4633   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4634   * @param  BurstBuffer The Buffer address.
4635   * @param  BurstLength DMA Burst length. This parameter can be one value
4636   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4637   * @param  DataLength Data length. This parameter can be one value
4638   *         between 1 and 0xFFFF.
4639   * @retval HAL status
4640   */
4641 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4642                                                    uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4643                                                    uint32_t  BurstLength,  uint32_t  DataLength)
4644 {
4645   HAL_StatusTypeDef status = HAL_OK;
4646
4647   /* Check the parameters */
4648   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4649   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4650   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4651   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4652   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4653
4654   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4655   {
4656     return HAL_BUSY;
4657   }
4658   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4659   {
4660     if ((BurstBuffer == NULL) && (BurstLength > 0U))
4661     {
4662       return HAL_ERROR;
4663     }
4664     else
4665     {
4666       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4667     }
4668   }
4669   else
4670   {
4671     /* nothing to do */
4672   }
4673
4674   switch (BurstRequestSrc)
4675   {
4676     case TIM_DMA_UPDATE:
4677     {
4678       /* Set the DMA Period elapsed callbacks */
4679       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4680       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4681
4682       /* Set the DMA error callback */
4683       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4684
4685       /* Enable the DMA stream */
4686       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4687                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4688       {
4689         /* Return error status */
4690         return HAL_ERROR;
4691       }
4692       break;
4693     }
4694     case TIM_DMA_CC1:
4695     {
4696       /* Set the DMA compare callbacks */
4697       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4698       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4699
4700       /* Set the DMA error callback */
4701       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4702
4703       /* Enable the DMA stream */
4704       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4705                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4706       {
4707         /* Return error status */
4708         return HAL_ERROR;
4709       }
4710       break;
4711     }
4712     case TIM_DMA_CC2:
4713     {
4714       /* Set the DMA compare callbacks */
4715       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4716       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4717
4718       /* Set the DMA error callback */
4719       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4720
4721       /* Enable the DMA stream */
4722       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4723                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4724       {
4725         /* Return error status */
4726         return HAL_ERROR;
4727       }
4728       break;
4729     }
4730     case TIM_DMA_CC3:
4731     {
4732       /* Set the DMA compare callbacks */
4733       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4734       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4735
4736       /* Set the DMA error callback */
4737       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4738
4739       /* Enable the DMA stream */
4740       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4741                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4742       {
4743         /* Return error status */
4744         return HAL_ERROR;
4745       }
4746       break;
4747     }
4748     case TIM_DMA_CC4:
4749     {
4750       /* Set the DMA compare callbacks */
4751       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4752       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4753
4754       /* Set the DMA error callback */
4755       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4756
4757       /* Enable the DMA stream */
4758       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4759                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4760       {
4761         /* Return error status */
4762         return HAL_ERROR;
4763       }
4764       break;
4765     }
4766     case TIM_DMA_COM:
4767     {
4768       /* Set the DMA commutation callbacks */
4769       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
4770       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
4771
4772       /* Set the DMA error callback */
4773       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4774
4775       /* Enable the DMA stream */
4776       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4777                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4778       {
4779         /* Return error status */
4780         return HAL_ERROR;
4781       }
4782       break;
4783     }
4784     case TIM_DMA_TRIGGER:
4785     {
4786       /* Set the DMA trigger callbacks */
4787       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4788       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4789
4790       /* Set the DMA error callback */
4791       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4792
4793       /* Enable the DMA stream */
4794       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4795                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4796       {
4797         /* Return error status */
4798         return HAL_ERROR;
4799       }
4800       break;
4801     }
4802     default:
4803       status = HAL_ERROR;
4804       break;
4805   }
4806
4807   if (status == HAL_OK)
4808   {
4809     /* Configure the DMA Burst Mode */
4810     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4811     /* Enable the TIM DMA Request */
4812     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4813   }
4814
4815   /* Return function status */
4816   return status;
4817 }
4818
4819 /**
4820   * @brief  Stops the TIM DMA Burst mode
4821   * @param  htim TIM handle
4822   * @param  BurstRequestSrc TIM DMA Request sources to disable
4823   * @retval HAL status
4824   */
4825 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4826 {
4827   HAL_StatusTypeDef status = HAL_OK;
4828
4829   /* Check the parameters */
4830   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4831
4832   /* Abort the DMA transfer (at least disable the DMA stream) */
4833   switch (BurstRequestSrc)
4834   {
4835     case TIM_DMA_UPDATE:
4836     {
4837       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4838       break;
4839     }
4840     case TIM_DMA_CC1:
4841     {
4842       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4843       break;
4844     }
4845     case TIM_DMA_CC2:
4846     {
4847       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4848       break;
4849     }
4850     case TIM_DMA_CC3:
4851     {
4852       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4853       break;
4854     }
4855     case TIM_DMA_CC4:
4856     {
4857       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4858       break;
4859     }
4860     case TIM_DMA_COM:
4861     {
4862       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4863       break;
4864     }
4865     case TIM_DMA_TRIGGER:
4866     {
4867       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4868       break;
4869     }
4870     default:
4871       status = HAL_ERROR;
4872       break;
4873   }
4874
4875   if (status == HAL_OK)
4876   {
4877     /* Disable the TIM Update DMA request */
4878     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4879
4880     /* Change the DMA burst operation state */
4881     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4882   }
4883
4884   /* Return function status */
4885   return status;
4886 }
4887
4888 /**
4889   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4890   * @param  htim TIM handle
4891   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
4892   *         This parameter can be one of the following values:
4893   *            @arg TIM_DMABASE_CR1
4894   *            @arg TIM_DMABASE_CR2
4895   *            @arg TIM_DMABASE_SMCR
4896   *            @arg TIM_DMABASE_DIER
4897   *            @arg TIM_DMABASE_SR
4898   *            @arg TIM_DMABASE_EGR
4899   *            @arg TIM_DMABASE_CCMR1
4900   *            @arg TIM_DMABASE_CCMR2
4901   *            @arg TIM_DMABASE_CCER
4902   *            @arg TIM_DMABASE_CNT
4903   *            @arg TIM_DMABASE_PSC
4904   *            @arg TIM_DMABASE_ARR
4905   *            @arg TIM_DMABASE_RCR
4906   *            @arg TIM_DMABASE_CCR1
4907   *            @arg TIM_DMABASE_CCR2
4908   *            @arg TIM_DMABASE_CCR3
4909   *            @arg TIM_DMABASE_CCR4
4910   *            @arg TIM_DMABASE_BDTR
4911   *            @arg TIM_DMABASE_CCMR3
4912   *            @arg TIM_DMABASE_CCR5
4913   *            @arg TIM_DMABASE_CCR6
4914   *            @arg TIM_DMABASE_AF1
4915   *            @arg TIM_DMABASE_AF2
4916   *            @arg TIM_DMABASE_TISEL
4917   *
4918   * @param  BurstRequestSrc TIM DMA Request sources
4919   *         This parameter can be one of the following values:
4920   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
4921   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4922   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4923   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4924   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4925   *            @arg TIM_DMA_COM: TIM Commutation DMA source
4926   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4927   * @param  BurstBuffer The Buffer address.
4928   * @param  BurstLength DMA Burst length. This parameter can be one value
4929   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4930   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
4931   * @retval HAL status
4932   */
4933 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4934                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
4935 {
4936   HAL_StatusTypeDef status;
4937
4938   status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4939                                            ((BurstLength) >> 8U) + 1U);
4940
4941
4942   return status;
4943 }
4944
4945 /**
4946   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4947   * @param  htim TIM handle
4948   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
4949   *         This parameter can be one of the following values:
4950   *            @arg TIM_DMABASE_CR1
4951   *            @arg TIM_DMABASE_CR2
4952   *            @arg TIM_DMABASE_SMCR
4953   *            @arg TIM_DMABASE_DIER
4954   *            @arg TIM_DMABASE_SR
4955   *            @arg TIM_DMABASE_EGR
4956   *            @arg TIM_DMABASE_CCMR1
4957   *            @arg TIM_DMABASE_CCMR2
4958   *            @arg TIM_DMABASE_CCER
4959   *            @arg TIM_DMABASE_CNT
4960   *            @arg TIM_DMABASE_PSC
4961   *            @arg TIM_DMABASE_ARR
4962   *            @arg TIM_DMABASE_RCR
4963   *            @arg TIM_DMABASE_CCR1
4964   *            @arg TIM_DMABASE_CCR2
4965   *            @arg TIM_DMABASE_CCR3
4966   *            @arg TIM_DMABASE_CCR4
4967   *            @arg TIM_DMABASE_BDTR
4968   *            @arg TIM_DMABASE_CCMR3
4969   *            @arg TIM_DMABASE_CCR5
4970   *            @arg TIM_DMABASE_CCR6
4971   *            @arg TIM_DMABASE_AF1
4972   *            @arg TIM_DMABASE_AF2
4973   *            @arg TIM_DMABASE_TISEL
4974   *
4975   * @param  BurstRequestSrc TIM DMA Request sources
4976   *         This parameter can be one of the following values:
4977   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
4978   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4979   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4980   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4981   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4982   *            @arg TIM_DMA_COM: TIM Commutation DMA source
4983   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4984   * @param  BurstBuffer The Buffer address.
4985   * @param  BurstLength DMA Burst length. This parameter can be one value
4986   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4987   * @param  DataLength Data length. This parameter can be one value
4988   *         between 1 and 0xFFFF.
4989   * @retval HAL status
4990   */
4991 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4992                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
4993                                                   uint32_t  BurstLength, uint32_t  DataLength)
4994 {
4995   HAL_StatusTypeDef status = HAL_OK;
4996
4997   /* Check the parameters */
4998   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4999   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
5000   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5001   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
5002   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
5003
5004   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
5005   {
5006     return HAL_BUSY;
5007   }
5008   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
5009   {
5010     if ((BurstBuffer == NULL) && (BurstLength > 0U))
5011     {
5012       return HAL_ERROR;
5013     }
5014     else
5015     {
5016       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
5017     }
5018   }
5019   else
5020   {
5021     /* nothing to do */
5022   }
5023   switch (BurstRequestSrc)
5024   {
5025     case TIM_DMA_UPDATE:
5026     {
5027       /* Set the DMA Period elapsed callbacks */
5028       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
5029       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
5030
5031       /* Set the DMA error callback */
5032       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
5033
5034       /* Enable the DMA stream */
5035       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5036                            DataLength) != HAL_OK)
5037       {
5038         /* Return error status */
5039         return HAL_ERROR;
5040       }
5041       break;
5042     }
5043     case TIM_DMA_CC1:
5044     {
5045       /* Set the DMA capture callbacks */
5046       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
5047       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5048
5049       /* Set the DMA error callback */
5050       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
5051
5052       /* Enable the DMA stream */
5053       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5054                            DataLength) != HAL_OK)
5055       {
5056         /* Return error status */
5057         return HAL_ERROR;
5058       }
5059       break;
5060     }
5061     case TIM_DMA_CC2:
5062     {
5063       /* Set the DMA capture callbacks */
5064       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
5065       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5066
5067       /* Set the DMA error callback */
5068       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
5069
5070       /* Enable the DMA stream */
5071       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5072                            DataLength) != HAL_OK)
5073       {
5074         /* Return error status */
5075         return HAL_ERROR;
5076       }
5077       break;
5078     }
5079     case TIM_DMA_CC3:
5080     {
5081       /* Set the DMA capture callbacks */
5082       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
5083       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5084
5085       /* Set the DMA error callback */
5086       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
5087
5088       /* Enable the DMA stream */
5089       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5090                            DataLength) != HAL_OK)
5091       {
5092         /* Return error status */
5093         return HAL_ERROR;
5094       }
5095       break;
5096     }
5097     case TIM_DMA_CC4:
5098     {
5099       /* Set the DMA capture callbacks */
5100       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
5101       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5102
5103       /* Set the DMA error callback */
5104       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
5105
5106       /* Enable the DMA stream */
5107       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5108                            DataLength) != HAL_OK)
5109       {
5110         /* Return error status */
5111         return HAL_ERROR;
5112       }
5113       break;
5114     }
5115     case TIM_DMA_COM:
5116     {
5117       /* Set the DMA commutation callbacks */
5118       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
5119       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
5120
5121       /* Set the DMA error callback */
5122       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
5123
5124       /* Enable the DMA stream */
5125       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5126                            DataLength) != HAL_OK)
5127       {
5128         /* Return error status */
5129         return HAL_ERROR;
5130       }
5131       break;
5132     }
5133     case TIM_DMA_TRIGGER:
5134     {
5135       /* Set the DMA trigger callbacks */
5136       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
5137       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
5138
5139       /* Set the DMA error callback */
5140       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
5141
5142       /* Enable the DMA stream */
5143       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5144                            DataLength) != HAL_OK)
5145       {
5146         /* Return error status */
5147         return HAL_ERROR;
5148       }
5149       break;
5150     }
5151     default:
5152       status = HAL_ERROR;
5153       break;
5154   }
5155
5156   if (status == HAL_OK)
5157   {
5158     /* Configure the DMA Burst Mode */
5159     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
5160
5161     /* Enable the TIM DMA Request */
5162     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5163   }
5164
5165   /* Return function status */
5166   return status;
5167 }
5168
5169 /**
5170   * @brief  Stop the DMA burst reading
5171   * @param  htim TIM handle
5172   * @param  BurstRequestSrc TIM DMA Request sources to disable.
5173   * @retval HAL status
5174   */
5175 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5176 {
5177   HAL_StatusTypeDef status = HAL_OK;
5178
5179   /* Check the parameters */
5180   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5181
5182   /* Abort the DMA transfer (at least disable the DMA stream) */
5183   switch (BurstRequestSrc)
5184   {
5185     case TIM_DMA_UPDATE:
5186     {
5187       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5188       break;
5189     }
5190     case TIM_DMA_CC1:
5191     {
5192       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5193       break;
5194     }
5195     case TIM_DMA_CC2:
5196     {
5197       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5198       break;
5199     }
5200     case TIM_DMA_CC3:
5201     {
5202       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5203       break;
5204     }
5205     case TIM_DMA_CC4:
5206     {
5207       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5208       break;
5209     }
5210     case TIM_DMA_COM:
5211     {
5212       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5213       break;
5214     }
5215     case TIM_DMA_TRIGGER:
5216     {
5217       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5218       break;
5219     }
5220     default:
5221       status = HAL_ERROR;
5222       break;
5223   }
5224
5225   if (status == HAL_OK)
5226   {
5227     /* Disable the TIM Update DMA request */
5228     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5229
5230     /* Change the DMA burst operation state */
5231     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5232   }
5233
5234   /* Return function status */
5235   return status;
5236 }
5237
5238 /**
5239   * @brief  Generate a software event
5240   * @param  htim TIM handle
5241   * @param  EventSource specifies the event source.
5242   *          This parameter can be one of the following values:
5243   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5244   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5245   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5246   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5247   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5248   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
5249   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5250   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5251   *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
5252   * @note   Basic timers can only generate an update event.
5253   * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5254   * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
5255   *         only for timer instances supporting break input(s).
5256   * @retval HAL status
5257   */
5258
5259 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5260 {
5261   /* Check the parameters */
5262   assert_param(IS_TIM_INSTANCE(htim->Instance));
5263   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5264
5265   /* Process Locked */
5266   __HAL_LOCK(htim);
5267
5268   /* Change the TIM state */
5269   htim->State = HAL_TIM_STATE_BUSY;
5270
5271   /* Set the event sources */
5272   htim->Instance->EGR = EventSource;
5273
5274   /* Change the TIM state */
5275   htim->State = HAL_TIM_STATE_READY;
5276
5277   __HAL_UNLOCK(htim);
5278
5279   /* Return function status */
5280   return HAL_OK;
5281 }
5282
5283 /**
5284   * @brief  Configures the OCRef clear feature
5285   * @param  htim TIM handle
5286   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5287   *         contains the OCREF clear feature and parameters for the TIM peripheral.
5288   * @param  Channel specifies the TIM Channel
5289   *          This parameter can be one of the following values:
5290   *            @arg TIM_CHANNEL_1: TIM Channel 1
5291   *            @arg TIM_CHANNEL_2: TIM Channel 2
5292   *            @arg TIM_CHANNEL_3: TIM Channel 3
5293   *            @arg TIM_CHANNEL_4: TIM Channel 4
5294   *            @arg TIM_CHANNEL_5: TIM Channel 5
5295   *            @arg TIM_CHANNEL_6: TIM Channel 6
5296   * @retval HAL status
5297   */
5298 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5299                                            const TIM_ClearInputConfigTypeDef *sClearInputConfig,
5300                                            uint32_t Channel)
5301 {
5302   HAL_StatusTypeDef status = HAL_OK;
5303
5304   /* Check the parameters */
5305   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5306   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5307
5308   /* Process Locked */
5309   __HAL_LOCK(htim);
5310
5311   htim->State = HAL_TIM_STATE_BUSY;
5312
5313   switch (sClearInputConfig->ClearInputSource)
5314   {
5315     case TIM_CLEARINPUTSOURCE_NONE:
5316     {
5317       /* Clear the OCREF clear selection bit and the the ETR Bits */
5318       CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5319       break;
5320     }
5321
5322     case TIM_CLEARINPUTSOURCE_ETR:
5323     {
5324       /* Check the parameters */
5325       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5326       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5327       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5328
5329       /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5330       if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5331       {
5332         htim->State = HAL_TIM_STATE_READY;
5333         __HAL_UNLOCK(htim);
5334         return HAL_ERROR;
5335       }
5336
5337       TIM_ETR_SetConfig(htim->Instance,
5338                         sClearInputConfig->ClearInputPrescaler,
5339                         sClearInputConfig->ClearInputPolarity,
5340                         sClearInputConfig->ClearInputFilter);
5341       break;
5342     }
5343
5344     default:
5345       status = HAL_ERROR;
5346       break;
5347   }
5348
5349   if (status == HAL_OK)
5350   {
5351     switch (Channel)
5352     {
5353       case TIM_CHANNEL_1:
5354       {
5355         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5356         {
5357           /* Enable the OCREF clear feature for Channel 1 */
5358           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5359         }
5360         else
5361         {
5362           /* Disable the OCREF clear feature for Channel 1 */
5363           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5364         }
5365         break;
5366       }
5367       case TIM_CHANNEL_2:
5368       {
5369         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5370         {
5371           /* Enable the OCREF clear feature for Channel 2 */
5372           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5373         }
5374         else
5375         {
5376           /* Disable the OCREF clear feature for Channel 2 */
5377           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5378         }
5379         break;
5380       }
5381       case TIM_CHANNEL_3:
5382       {
5383         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5384         {
5385           /* Enable the OCREF clear feature for Channel 3 */
5386           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5387         }
5388         else
5389         {
5390           /* Disable the OCREF clear feature for Channel 3 */
5391           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5392         }
5393         break;
5394       }
5395       case TIM_CHANNEL_4:
5396       {
5397         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5398         {
5399           /* Enable the OCREF clear feature for Channel 4 */
5400           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5401         }
5402         else
5403         {
5404           /* Disable the OCREF clear feature for Channel 4 */
5405           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5406         }
5407         break;
5408       }
5409       case TIM_CHANNEL_5:
5410       {
5411         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5412         {
5413           /* Enable the OCREF clear feature for Channel 5 */
5414           SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5415         }
5416         else
5417         {
5418           /* Disable the OCREF clear feature for Channel 5 */
5419           CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5420         }
5421         break;
5422       }
5423       case TIM_CHANNEL_6:
5424       {
5425         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5426         {
5427           /* Enable the OCREF clear feature for Channel 6 */
5428           SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5429         }
5430         else
5431         {
5432           /* Disable the OCREF clear feature for Channel 6 */
5433           CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5434         }
5435         break;
5436       }
5437       default:
5438         break;
5439     }
5440   }
5441
5442   htim->State = HAL_TIM_STATE_READY;
5443
5444   __HAL_UNLOCK(htim);
5445
5446   return status;
5447 }
5448
5449 /**
5450   * @brief   Configures the clock source to be used
5451   * @param  htim TIM handle
5452   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5453   *         contains the clock source information for the TIM peripheral.
5454   * @retval HAL status
5455   */
5456 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5457 {
5458   HAL_StatusTypeDef status = HAL_OK;
5459   uint32_t tmpsmcr;
5460
5461   /* Process Locked */
5462   __HAL_LOCK(htim);
5463
5464   htim->State = HAL_TIM_STATE_BUSY;
5465
5466   /* Check the parameters */
5467   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5468
5469   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5470   tmpsmcr = htim->Instance->SMCR;
5471   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5472   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5473   htim->Instance->SMCR = tmpsmcr;
5474
5475   switch (sClockSourceConfig->ClockSource)
5476   {
5477     case TIM_CLOCKSOURCE_INTERNAL:
5478     {
5479       assert_param(IS_TIM_INSTANCE(htim->Instance));
5480       break;
5481     }
5482
5483     case TIM_CLOCKSOURCE_ETRMODE1:
5484     {
5485       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5486       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5487
5488       /* Check ETR input conditioning related parameters */
5489       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5490       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5491       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5492
5493       /* Configure the ETR Clock source */
5494       TIM_ETR_SetConfig(htim->Instance,
5495                         sClockSourceConfig->ClockPrescaler,
5496                         sClockSourceConfig->ClockPolarity,
5497                         sClockSourceConfig->ClockFilter);
5498
5499       /* Select the External clock mode1 and the ETRF trigger */
5500       tmpsmcr = htim->Instance->SMCR;
5501       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5502       /* Write to TIMx SMCR */
5503       htim->Instance->SMCR = tmpsmcr;
5504       break;
5505     }
5506
5507     case TIM_CLOCKSOURCE_ETRMODE2:
5508     {
5509       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5510       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5511
5512       /* Check ETR input conditioning related parameters */
5513       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5514       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5515       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5516
5517       /* Configure the ETR Clock source */
5518       TIM_ETR_SetConfig(htim->Instance,
5519                         sClockSourceConfig->ClockPrescaler,
5520                         sClockSourceConfig->ClockPolarity,
5521                         sClockSourceConfig->ClockFilter);
5522       /* Enable the External clock mode2 */
5523       htim->Instance->SMCR |= TIM_SMCR_ECE;
5524       break;
5525     }
5526
5527     case TIM_CLOCKSOURCE_TI1:
5528     {
5529       /* Check whether or not the timer instance supports external clock mode 1 */
5530       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5531
5532       /* Check TI1 input conditioning related parameters */
5533       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5534       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5535
5536       TIM_TI1_ConfigInputStage(htim->Instance,
5537                                sClockSourceConfig->ClockPolarity,
5538                                sClockSourceConfig->ClockFilter);
5539       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5540       break;
5541     }
5542
5543     case TIM_CLOCKSOURCE_TI2:
5544     {
5545       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5546       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5547
5548       /* Check TI2 input conditioning related parameters */
5549       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5550       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5551
5552       TIM_TI2_ConfigInputStage(htim->Instance,
5553                                sClockSourceConfig->ClockPolarity,
5554                                sClockSourceConfig->ClockFilter);
5555       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5556       break;
5557     }
5558
5559     case TIM_CLOCKSOURCE_TI1ED:
5560     {
5561       /* Check whether or not the timer instance supports external clock mode 1 */
5562       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5563
5564       /* Check TI1 input conditioning related parameters */
5565       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5566       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5567
5568       TIM_TI1_ConfigInputStage(htim->Instance,
5569                                sClockSourceConfig->ClockPolarity,
5570                                sClockSourceConfig->ClockFilter);
5571       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5572       break;
5573     }
5574
5575     case TIM_CLOCKSOURCE_ITR0:
5576     case TIM_CLOCKSOURCE_ITR1:
5577     case TIM_CLOCKSOURCE_ITR2:
5578     case TIM_CLOCKSOURCE_ITR3:
5579     case TIM_CLOCKSOURCE_ITR4:
5580     case TIM_CLOCKSOURCE_ITR5:
5581     case TIM_CLOCKSOURCE_ITR6:
5582     case TIM_CLOCKSOURCE_ITR7:
5583     case TIM_CLOCKSOURCE_ITR8:
5584     {
5585       /* Check whether or not the timer instance supports internal trigger input */
5586       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
5587
5588       TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5589       break;
5590     }
5591
5592     default:
5593       status = HAL_ERROR;
5594       break;
5595   }
5596   htim->State = HAL_TIM_STATE_READY;
5597
5598   __HAL_UNLOCK(htim);
5599
5600   return status;
5601 }
5602
5603 /**
5604   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
5605   *         or a XOR combination between CH1_input, CH2_input & CH3_input
5606   * @param  htim TIM handle.
5607   * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
5608   *         output of a XOR gate.
5609   *          This parameter can be one of the following values:
5610   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5611   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5612   *            pins are connected to the TI1 input (XOR combination)
5613   * @retval HAL status
5614   */
5615 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5616 {
5617   uint32_t tmpcr2;
5618
5619   /* Check the parameters */
5620   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5621   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5622
5623   /* Get the TIMx CR2 register value */
5624   tmpcr2 = htim->Instance->CR2;
5625
5626   /* Reset the TI1 selection */
5627   tmpcr2 &= ~TIM_CR2_TI1S;
5628
5629   /* Set the TI1 selection */
5630   tmpcr2 |= TI1_Selection;
5631
5632   /* Write to TIMxCR2 */
5633   htim->Instance->CR2 = tmpcr2;
5634
5635   return HAL_OK;
5636 }
5637
5638 /**
5639   * @brief  Configures the TIM in Slave mode
5640   * @param  htim TIM handle.
5641   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5642   *         contains the selected trigger (internal trigger input, filtered
5643   *         timer input or external trigger input) and the Slave mode
5644   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
5645   * @retval HAL status
5646   */
5647 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5648 {
5649   /* Check the parameters */
5650   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5651   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5652   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5653
5654   __HAL_LOCK(htim);
5655
5656   htim->State = HAL_TIM_STATE_BUSY;
5657
5658   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5659   {
5660     htim->State = HAL_TIM_STATE_READY;
5661     __HAL_UNLOCK(htim);
5662     return HAL_ERROR;
5663   }
5664
5665   /* Disable Trigger Interrupt */
5666   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5667
5668   /* Disable Trigger DMA request */
5669   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5670
5671   htim->State = HAL_TIM_STATE_READY;
5672
5673   __HAL_UNLOCK(htim);
5674
5675   return HAL_OK;
5676 }
5677
5678 /**
5679   * @brief  Configures the TIM in Slave mode in interrupt mode
5680   * @param  htim TIM handle.
5681   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5682   *         contains the selected trigger (internal trigger input, filtered
5683   *         timer input or external trigger input) and the Slave mode
5684   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
5685   * @retval HAL status
5686   */
5687 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5688                                                 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5689 {
5690   /* Check the parameters */
5691   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5692   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5693   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5694
5695   __HAL_LOCK(htim);
5696
5697   htim->State = HAL_TIM_STATE_BUSY;
5698
5699   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5700   {
5701     htim->State = HAL_TIM_STATE_READY;
5702     __HAL_UNLOCK(htim);
5703     return HAL_ERROR;
5704   }
5705
5706   /* Enable Trigger Interrupt */
5707   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5708
5709   /* Disable Trigger DMA request */
5710   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5711
5712   htim->State = HAL_TIM_STATE_READY;
5713
5714   __HAL_UNLOCK(htim);
5715
5716   return HAL_OK;
5717 }
5718
5719 /**
5720   * @brief  Read the captured value from Capture Compare unit
5721   * @param  htim TIM handle.
5722   * @param  Channel TIM Channels to be enabled
5723   *          This parameter can be one of the following values:
5724   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
5725   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
5726   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
5727   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
5728   * @retval Captured value
5729   */
5730 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
5731 {
5732   uint32_t tmpreg = 0U;
5733
5734   switch (Channel)
5735   {
5736     case TIM_CHANNEL_1:
5737     {
5738       /* Check the parameters */
5739       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5740
5741       /* Return the capture 1 value */
5742       tmpreg =  htim->Instance->CCR1;
5743
5744       break;
5745     }
5746     case TIM_CHANNEL_2:
5747     {
5748       /* Check the parameters */
5749       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5750
5751       /* Return the capture 2 value */
5752       tmpreg =   htim->Instance->CCR2;
5753
5754       break;
5755     }
5756
5757     case TIM_CHANNEL_3:
5758     {
5759       /* Check the parameters */
5760       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5761
5762       /* Return the capture 3 value */
5763       tmpreg =   htim->Instance->CCR3;
5764
5765       break;
5766     }
5767
5768     case TIM_CHANNEL_4:
5769     {
5770       /* Check the parameters */
5771       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5772
5773       /* Return the capture 4 value */
5774       tmpreg =   htim->Instance->CCR4;
5775
5776       break;
5777     }
5778
5779     default:
5780       break;
5781   }
5782
5783   return tmpreg;
5784 }
5785
5786 /**
5787   * @}
5788   */
5789
5790 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5791   * @ingroup RTEMSBSPsARMSTM32H7
5792   *  @brief    TIM Callbacks functions
5793   *
5794 @verbatim
5795   ==============================================================================
5796                         ##### TIM Callbacks functions #####
5797   ==============================================================================
5798  [..]
5799    This section provides TIM callback functions:
5800    (+) TIM Period elapsed callback
5801    (+) TIM Output Compare callback
5802    (+) TIM Input capture callback
5803    (+) TIM Trigger callback
5804    (+) TIM Error callback
5805
5806 @endverbatim
5807   * @{
5808   */
5809
5810 /**
5811   * @brief  Period elapsed callback in non-blocking mode
5812   * @param  htim TIM handle
5813   * @retval None
5814   */
5815 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5816 {
5817   /* Prevent unused argument(s) compilation warning */
5818   UNUSED(htim);
5819
5820   /* NOTE : This function should not be modified, when the callback is needed,
5821             the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5822    */
5823 }
5824
5825 /**
5826   * @brief  Period elapsed half complete callback in non-blocking mode
5827   * @param  htim TIM handle
5828   * @retval None
5829   */
5830 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5831 {
5832   /* Prevent unused argument(s) compilation warning */
5833   UNUSED(htim);
5834
5835   /* NOTE : This function should not be modified, when the callback is needed,
5836             the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5837    */
5838 }
5839
5840 /**
5841   * @brief  Output Compare callback in non-blocking mode
5842   * @param  htim TIM OC handle
5843   * @retval None
5844   */
5845 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5846 {
5847   /* Prevent unused argument(s) compilation warning */
5848   UNUSED(htim);
5849
5850   /* NOTE : This function should not be modified, when the callback is needed,
5851             the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5852    */
5853 }
5854
5855 /**
5856   * @brief  Input Capture callback in non-blocking mode
5857   * @param  htim TIM IC handle
5858   * @retval None
5859   */
5860 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5861 {
5862   /* Prevent unused argument(s) compilation warning */
5863   UNUSED(htim);
5864
5865   /* NOTE : This function should not be modified, when the callback is needed,
5866             the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5867    */
5868 }
5869
5870 /**
5871   * @brief  Input Capture half complete callback in non-blocking mode
5872   * @param  htim TIM IC handle
5873   * @retval None
5874   */
5875 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5876 {
5877   /* Prevent unused argument(s) compilation warning */
5878   UNUSED(htim);
5879
5880   /* NOTE : This function should not be modified, when the callback is needed,
5881             the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5882    */
5883 }
5884
5885 /**
5886   * @brief  PWM Pulse finished callback in non-blocking mode
5887   * @param  htim TIM handle
5888   * @retval None
5889   */
5890 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5891 {
5892   /* Prevent unused argument(s) compilation warning */
5893   UNUSED(htim);
5894
5895   /* NOTE : This function should not be modified, when the callback is needed,
5896             the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5897    */
5898 }
5899
5900 /**
5901   * @brief  PWM Pulse finished half complete callback in non-blocking mode
5902   * @param  htim TIM handle
5903   * @retval None
5904   */
5905 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5906 {
5907   /* Prevent unused argument(s) compilation warning */
5908   UNUSED(htim);
5909
5910   /* NOTE : This function should not be modified, when the callback is needed,
5911             the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5912    */
5913 }
5914
5915 /**
5916   * @brief  Hall Trigger detection callback in non-blocking mode
5917   * @param  htim TIM handle
5918   * @retval None
5919   */
5920 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5921 {
5922   /* Prevent unused argument(s) compilation warning */
5923   UNUSED(htim);
5924
5925   /* NOTE : This function should not be modified, when the callback is needed,
5926             the HAL_TIM_TriggerCallback could be implemented in the user file
5927    */
5928 }
5929
5930 /**
5931   * @brief  Hall Trigger detection half complete callback in non-blocking mode
5932   * @param  htim TIM handle
5933   * @retval None
5934   */
5935 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5936 {
5937   /* Prevent unused argument(s) compilation warning */
5938   UNUSED(htim);
5939
5940   /* NOTE : This function should not be modified, when the callback is needed,
5941             the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5942    */
5943 }
5944
5945 /**
5946   * @brief  Timer error callback in non-blocking mode
5947   * @param  htim TIM handle
5948   * @retval None
5949   */
5950 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5951 {
5952   /* Prevent unused argument(s) compilation warning */
5953   UNUSED(htim);
5954
5955   /* NOTE : This function should not be modified, when the callback is needed,
5956             the HAL_TIM_ErrorCallback could be implemented in the user file
5957    */
5958 }
5959
5960 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5961 /**
5962   * @brief  Register a User TIM callback to be used instead of the weak predefined callback
5963   * @param htim tim handle
5964   * @param CallbackID ID of the callback to be registered
5965   *        This parameter can be one of the following values:
5966   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5967   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5968   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5969   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5970   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5971   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5972   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5973   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5974   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5975   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5976   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5977   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5978   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5979   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5980   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5981   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5982   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5983   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5984   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5985   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5986   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5987   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5988   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5989   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5990   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5991   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5992   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5993   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
5994   *          @param pCallback pointer to the callback function
5995   *          @retval status
5996   */
5997 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5998                                            pTIM_CallbackTypeDef pCallback)
5999 {
6000   HAL_StatusTypeDef status = HAL_OK;
6001
6002   if (pCallback == NULL)
6003   {
6004     return HAL_ERROR;
6005   }
6006
6007   if (htim->State == HAL_TIM_STATE_READY)
6008   {
6009     switch (CallbackID)
6010     {
6011       case HAL_TIM_BASE_MSPINIT_CB_ID :
6012         htim->Base_MspInitCallback                 = pCallback;
6013         break;
6014
6015       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6016         htim->Base_MspDeInitCallback               = pCallback;
6017         break;
6018
6019       case HAL_TIM_IC_MSPINIT_CB_ID :
6020         htim->IC_MspInitCallback                   = pCallback;
6021         break;
6022
6023       case HAL_TIM_IC_MSPDEINIT_CB_ID :
6024         htim->IC_MspDeInitCallback                 = pCallback;
6025         break;
6026
6027       case HAL_TIM_OC_MSPINIT_CB_ID :
6028         htim->OC_MspInitCallback                   = pCallback;
6029         break;
6030
6031       case HAL_TIM_OC_MSPDEINIT_CB_ID :
6032         htim->OC_MspDeInitCallback                 = pCallback;
6033         break;
6034
6035       case HAL_TIM_PWM_MSPINIT_CB_ID :
6036         htim->PWM_MspInitCallback                  = pCallback;
6037         break;
6038
6039       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6040         htim->PWM_MspDeInitCallback                = pCallback;
6041         break;
6042
6043       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6044         htim->OnePulse_MspInitCallback             = pCallback;
6045         break;
6046
6047       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6048         htim->OnePulse_MspDeInitCallback           = pCallback;
6049         break;
6050
6051       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6052         htim->Encoder_MspInitCallback              = pCallback;
6053         break;
6054
6055       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6056         htim->Encoder_MspDeInitCallback            = pCallback;
6057         break;
6058
6059       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6060         htim->HallSensor_MspInitCallback           = pCallback;
6061         break;
6062
6063       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6064         htim->HallSensor_MspDeInitCallback         = pCallback;
6065         break;
6066
6067       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6068         htim->PeriodElapsedCallback                = pCallback;
6069         break;
6070
6071       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6072         htim->PeriodElapsedHalfCpltCallback        = pCallback;
6073         break;
6074
6075       case HAL_TIM_TRIGGER_CB_ID :
6076         htim->TriggerCallback                      = pCallback;
6077         break;
6078
6079       case HAL_TIM_TRIGGER_HALF_CB_ID :
6080         htim->TriggerHalfCpltCallback              = pCallback;
6081         break;
6082
6083       case HAL_TIM_IC_CAPTURE_CB_ID :
6084         htim->IC_CaptureCallback                   = pCallback;
6085         break;
6086
6087       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6088         htim->IC_CaptureHalfCpltCallback           = pCallback;
6089         break;
6090
6091       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6092         htim->OC_DelayElapsedCallback              = pCallback;
6093         break;
6094
6095       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6096         htim->PWM_PulseFinishedCallback            = pCallback;
6097         break;
6098
6099       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6100         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
6101         break;
6102
6103       case HAL_TIM_ERROR_CB_ID :
6104         htim->ErrorCallback                        = pCallback;
6105         break;
6106
6107       case HAL_TIM_COMMUTATION_CB_ID :
6108         htim->CommutationCallback                  = pCallback;
6109         break;
6110
6111       case HAL_TIM_COMMUTATION_HALF_CB_ID :
6112         htim->CommutationHalfCpltCallback          = pCallback;
6113         break;
6114
6115       case HAL_TIM_BREAK_CB_ID :
6116         htim->BreakCallback                        = pCallback;
6117         break;
6118
6119       case HAL_TIM_BREAK2_CB_ID :
6120         htim->Break2Callback                       = pCallback;
6121         break;
6122
6123       default :
6124         /* Return error status */
6125         status = HAL_ERROR;
6126         break;
6127     }
6128   }
6129   else if (htim->State == HAL_TIM_STATE_RESET)
6130   {
6131     switch (CallbackID)
6132     {
6133       case HAL_TIM_BASE_MSPINIT_CB_ID :
6134         htim->Base_MspInitCallback         = pCallback;
6135         break;
6136
6137       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6138         htim->Base_MspDeInitCallback       = pCallback;
6139         break;
6140
6141       case HAL_TIM_IC_MSPINIT_CB_ID :
6142         htim->IC_MspInitCallback           = pCallback;
6143         break;
6144
6145       case HAL_TIM_IC_MSPDEINIT_CB_ID :
6146         htim->IC_MspDeInitCallback         = pCallback;
6147         break;
6148
6149       case HAL_TIM_OC_MSPINIT_CB_ID :
6150         htim->OC_MspInitCallback           = pCallback;
6151         break;
6152
6153       case HAL_TIM_OC_MSPDEINIT_CB_ID :
6154         htim->OC_MspDeInitCallback         = pCallback;
6155         break;
6156
6157       case HAL_TIM_PWM_MSPINIT_CB_ID :
6158         htim->PWM_MspInitCallback          = pCallback;
6159         break;
6160
6161       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6162         htim->PWM_MspDeInitCallback        = pCallback;
6163         break;
6164
6165       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6166         htim->OnePulse_MspInitCallback     = pCallback;
6167         break;
6168
6169       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6170         htim->OnePulse_MspDeInitCallback   = pCallback;
6171         break;
6172
6173       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6174         htim->Encoder_MspInitCallback      = pCallback;
6175         break;
6176
6177       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6178         htim->Encoder_MspDeInitCallback    = pCallback;
6179         break;
6180
6181       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6182         htim->HallSensor_MspInitCallback   = pCallback;
6183         break;
6184
6185       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6186         htim->HallSensor_MspDeInitCallback = pCallback;
6187         break;
6188
6189       default :
6190         /* Return error status */
6191         status = HAL_ERROR;
6192         break;
6193     }
6194   }
6195   else
6196   {
6197     /* Return error status */
6198     status = HAL_ERROR;
6199   }
6200
6201   return status;
6202 }
6203
6204 /**
6205   * @brief  Unregister a TIM callback
6206   *         TIM callback is redirected to the weak predefined callback
6207   * @param htim tim handle
6208   * @param CallbackID ID of the callback to be unregistered
6209   *        This parameter can be one of the following values:
6210   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6211   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6212   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6213   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6214   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6215   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6216   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6217   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6218   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6219   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6220   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6221   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6222   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6223   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6224   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6225   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6226   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6227   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6228   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6229   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6230   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6231   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6232   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6233   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6234   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6235   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6236   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6237   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6238   *          @retval status
6239   */
6240 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6241 {
6242   HAL_StatusTypeDef status = HAL_OK;
6243
6244   if (htim->State == HAL_TIM_STATE_READY)
6245   {
6246     switch (CallbackID)
6247     {
6248       case HAL_TIM_BASE_MSPINIT_CB_ID :
6249         /* Legacy weak Base MspInit Callback */
6250         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
6251         break;
6252
6253       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6254         /* Legacy weak Base Msp DeInit Callback */
6255         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
6256         break;
6257
6258       case HAL_TIM_IC_MSPINIT_CB_ID :
6259         /* Legacy weak IC Msp Init Callback */
6260         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
6261         break;
6262
6263       case HAL_TIM_IC_MSPDEINIT_CB_ID :
6264         /* Legacy weak IC Msp DeInit Callback */
6265         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
6266         break;
6267
6268       case HAL_TIM_OC_MSPINIT_CB_ID :
6269         /* Legacy weak OC Msp Init Callback */
6270         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
6271         break;
6272
6273       case HAL_TIM_OC_MSPDEINIT_CB_ID :
6274         /* Legacy weak OC Msp DeInit Callback */
6275         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
6276         break;
6277
6278       case HAL_TIM_PWM_MSPINIT_CB_ID :
6279         /* Legacy weak PWM Msp Init Callback */
6280         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
6281         break;
6282
6283       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6284         /* Legacy weak PWM Msp DeInit Callback */
6285         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
6286         break;
6287
6288       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6289         /* Legacy weak One Pulse Msp Init Callback */
6290         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
6291         break;
6292
6293       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6294         /* Legacy weak One Pulse Msp DeInit Callback */
6295         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
6296         break;
6297
6298       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6299         /* Legacy weak Encoder Msp Init Callback */
6300         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
6301         break;
6302
6303       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6304         /* Legacy weak Encoder Msp DeInit Callback */
6305         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
6306         break;
6307
6308       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6309         /* Legacy weak Hall Sensor Msp Init Callback */
6310         htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
6311         break;
6312
6313       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6314         /* Legacy weak Hall Sensor Msp DeInit Callback */
6315         htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
6316         break;
6317
6318       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6319         /* Legacy weak Period Elapsed Callback */
6320         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
6321         break;
6322
6323       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6324         /* Legacy weak Period Elapsed half complete Callback */
6325         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
6326         break;
6327
6328       case HAL_TIM_TRIGGER_CB_ID :
6329         /* Legacy weak Trigger Callback */
6330         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
6331         break;
6332
6333       case HAL_TIM_TRIGGER_HALF_CB_ID :
6334         /* Legacy weak Trigger half complete Callback */
6335         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
6336         break;
6337
6338       case HAL_TIM_IC_CAPTURE_CB_ID :
6339         /* Legacy weak IC Capture Callback */
6340         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
6341         break;
6342
6343       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6344         /* Legacy weak IC Capture half complete Callback */
6345         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
6346         break;
6347
6348       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6349         /* Legacy weak OC Delay Elapsed Callback */
6350         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
6351         break;
6352
6353       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6354         /* Legacy weak PWM Pulse Finished Callback */
6355         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
6356         break;
6357
6358       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6359         /* Legacy weak PWM Pulse Finished half complete Callback */
6360         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6361         break;
6362
6363       case HAL_TIM_ERROR_CB_ID :
6364         /* Legacy weak Error Callback */
6365         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
6366         break;
6367
6368       case HAL_TIM_COMMUTATION_CB_ID :
6369         /* Legacy weak Commutation Callback */
6370         htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
6371         break;
6372
6373       case HAL_TIM_COMMUTATION_HALF_CB_ID :
6374         /* Legacy weak Commutation half complete Callback */
6375         htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
6376         break;
6377
6378       case HAL_TIM_BREAK_CB_ID :
6379         /* Legacy weak Break Callback */
6380         htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
6381         break;
6382
6383       case HAL_TIM_BREAK2_CB_ID :
6384         /* Legacy weak Break2 Callback */
6385         htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
6386         break;
6387
6388       default :
6389         /* Return error status */
6390         status = HAL_ERROR;
6391         break;
6392     }
6393   }
6394   else if (htim->State == HAL_TIM_STATE_RESET)
6395   {
6396     switch (CallbackID)
6397     {
6398       case HAL_TIM_BASE_MSPINIT_CB_ID :
6399         /* Legacy weak Base MspInit Callback */
6400         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
6401         break;
6402
6403       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6404         /* Legacy weak Base Msp DeInit Callback */
6405         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
6406         break;
6407
6408       case HAL_TIM_IC_MSPINIT_CB_ID :
6409         /* Legacy weak IC Msp Init Callback */
6410         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
6411         break;
6412
6413       case HAL_TIM_IC_MSPDEINIT_CB_ID :
6414         /* Legacy weak IC Msp DeInit Callback */
6415         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
6416         break;
6417
6418       case HAL_TIM_OC_MSPINIT_CB_ID :
6419         /* Legacy weak OC Msp Init Callback */
6420         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
6421         break;
6422
6423       case HAL_TIM_OC_MSPDEINIT_CB_ID :
6424         /* Legacy weak OC Msp DeInit Callback */
6425         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
6426         break;
6427
6428       case HAL_TIM_PWM_MSPINIT_CB_ID :
6429         /* Legacy weak PWM Msp Init Callback */
6430         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
6431         break;
6432
6433       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6434         /* Legacy weak PWM Msp DeInit Callback */
6435         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
6436         break;
6437
6438       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6439         /* Legacy weak One Pulse Msp Init Callback */
6440         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
6441         break;
6442
6443       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6444         /* Legacy weak One Pulse Msp DeInit Callback */
6445         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
6446         break;
6447
6448       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6449         /* Legacy weak Encoder Msp Init Callback */
6450         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
6451         break;
6452
6453       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6454         /* Legacy weak Encoder Msp DeInit Callback */
6455         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
6456         break;
6457
6458       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6459         /* Legacy weak Hall Sensor Msp Init Callback */
6460         htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
6461         break;
6462
6463       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6464         /* Legacy weak Hall Sensor Msp DeInit Callback */
6465         htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6466         break;
6467
6468       default :
6469         /* Return error status */
6470         status = HAL_ERROR;
6471         break;
6472     }
6473   }
6474   else
6475   {
6476     /* Return error status */
6477     status = HAL_ERROR;
6478   }
6479
6480   return status;
6481 }
6482 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6483
6484 /**
6485   * @}
6486   */
6487
6488 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6489   * @ingroup RTEMSBSPsARMSTM32H7
6490   *  @brief   TIM Peripheral State functions
6491   *
6492 @verbatim
6493   ==============================================================================
6494                         ##### Peripheral State functions #####
6495   ==============================================================================
6496     [..]
6497     This subsection permits to get in run-time the status of the peripheral
6498     and the data flow.
6499
6500 @endverbatim
6501   * @{
6502   */
6503
6504 /**
6505   * @brief  Return the TIM Base handle state.
6506   * @param  htim TIM Base handle
6507   * @retval HAL state
6508   */
6509 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6510 {
6511   return htim->State;
6512 }
6513
6514 /**
6515   * @brief  Return the TIM OC handle state.
6516   * @param  htim TIM Output Compare handle
6517   * @retval HAL state
6518   */
6519 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6520 {
6521   return htim->State;
6522 }
6523
6524 /**
6525   * @brief  Return the TIM PWM handle state.
6526   * @param  htim TIM handle
6527   * @retval HAL state
6528   */
6529 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6530 {
6531   return htim->State;
6532 }
6533
6534 /**
6535   * @brief  Return the TIM Input Capture handle state.
6536   * @param  htim TIM IC handle
6537   * @retval HAL state
6538   */
6539 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6540 {
6541   return htim->State;
6542 }
6543
6544 /**
6545   * @brief  Return the TIM One Pulse Mode handle state.
6546   * @param  htim TIM OPM handle
6547   * @retval HAL state
6548   */
6549 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6550 {
6551   return htim->State;
6552 }
6553
6554 /**
6555   * @brief  Return the TIM Encoder Mode handle state.
6556   * @param  htim TIM Encoder Interface handle
6557   * @retval HAL state
6558   */
6559 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6560 {
6561   return htim->State;
6562 }
6563
6564 /**
6565   * @brief  Return the TIM Encoder Mode handle state.
6566   * @param  htim TIM handle
6567   * @retval Active channel
6568   */
6569 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6570 {
6571   return htim->Channel;
6572 }
6573
6574 /**
6575   * @brief  Return actual state of the TIM channel.
6576   * @param  htim TIM handle
6577   * @param  Channel TIM Channel
6578   *          This parameter can be one of the following values:
6579   *            @arg TIM_CHANNEL_1: TIM Channel 1
6580   *            @arg TIM_CHANNEL_2: TIM Channel 2
6581   *            @arg TIM_CHANNEL_3: TIM Channel 3
6582   *            @arg TIM_CHANNEL_4: TIM Channel 4
6583   *            @arg TIM_CHANNEL_5: TIM Channel 5
6584   *            @arg TIM_CHANNEL_6: TIM Channel 6
6585   * @retval TIM Channel state
6586   */
6587 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel)
6588 {
6589   HAL_TIM_ChannelStateTypeDef channel_state;
6590
6591   /* Check the parameters */
6592   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6593
6594   channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6595
6596   return channel_state;
6597 }
6598
6599 /**
6600   * @brief  Return actual state of a DMA burst operation.
6601   * @param  htim TIM handle
6602   * @retval DMA burst state
6603   */
6604 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6605 {
6606   /* Check the parameters */
6607   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6608
6609   return htim->DMABurstState;
6610 }
6611
6612 /**
6613   * @}
6614   */
6615
6616 /**
6617   * @}
6618   */
6619
6620 /** @defgroup TIM_Private_Functions TIM Private Functions
6621   * @ingroup RTEMSBSPsARMSTM32H7
6622   * @{
6623   */
6624
6625 /**
6626   * @brief  TIM DMA error callback
6627   * @param  hdma pointer to DMA handle.
6628   * @retval None
6629   */
6630 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6631 {
6632   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6633
6634   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6635   {
6636     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6637     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6638   }
6639   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6640   {
6641     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6642     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6643   }
6644   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6645   {
6646     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6647     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6648   }
6649   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6650   {
6651     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6652     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6653   }
6654   else
6655   {
6656     htim->State = HAL_TIM_STATE_READY;
6657   }
6658
6659 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6660   htim->ErrorCallback(htim);
6661 #else
6662   HAL_TIM_ErrorCallback(htim);
6663 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6664
6665   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6666 }
6667
6668 /**
6669   * @brief  TIM DMA Delay Pulse complete callback.
6670   * @param  hdma pointer to DMA handle.
6671   * @retval None
6672   */
6673 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6674 {
6675   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6676
6677   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6678   {
6679     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6680
6681     if (hdma->Init.Mode == DMA_NORMAL)
6682     {
6683       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6684     }
6685   }
6686   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6687   {
6688     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6689
6690     if (hdma->Init.Mode == DMA_NORMAL)
6691     {
6692       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6693     }
6694   }
6695   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6696   {
6697     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6698
6699     if (hdma->Init.Mode == DMA_NORMAL)
6700     {
6701       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6702     }
6703   }
6704   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6705   {
6706     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6707
6708     if (hdma->Init.Mode == DMA_NORMAL)
6709     {
6710       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6711     }
6712   }
6713   else
6714   {
6715     /* nothing to do */
6716   }
6717
6718 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6719   htim->PWM_PulseFinishedCallback(htim);
6720 #else
6721   HAL_TIM_PWM_PulseFinishedCallback(htim);
6722 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6723
6724   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6725 }
6726
6727 /**
6728   * @brief  TIM DMA Delay Pulse half complete callback.
6729   * @param  hdma pointer to DMA handle.
6730   * @retval None
6731   */
6732 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6733 {
6734   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6735
6736   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6737   {
6738     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6739   }
6740   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6741   {
6742     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6743   }
6744   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6745   {
6746     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6747   }
6748   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6749   {
6750     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6751   }
6752   else
6753   {
6754     /* nothing to do */
6755   }
6756
6757 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6758   htim->PWM_PulseFinishedHalfCpltCallback(htim);
6759 #else
6760   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6761 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6762
6763   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6764 }
6765
6766 /**
6767   * @brief  TIM DMA Capture complete callback.
6768   * @param  hdma pointer to DMA handle.
6769   * @retval None
6770   */
6771 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6772 {
6773   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6774
6775   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6776   {
6777     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6778
6779     if (hdma->Init.Mode == DMA_NORMAL)
6780     {
6781       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6782       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6783     }
6784   }
6785   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6786   {
6787     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6788
6789     if (hdma->Init.Mode == DMA_NORMAL)
6790     {
6791       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6792       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6793     }
6794   }
6795   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6796   {
6797     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6798
6799     if (hdma->Init.Mode == DMA_NORMAL)
6800     {
6801       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6802       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6803     }
6804   }
6805   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6806   {
6807     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6808
6809     if (hdma->Init.Mode == DMA_NORMAL)
6810     {
6811       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6812       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6813     }
6814   }
6815   else
6816   {
6817     /* nothing to do */
6818   }
6819
6820 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6821   htim->IC_CaptureCallback(htim);
6822 #else
6823   HAL_TIM_IC_CaptureCallback(htim);
6824 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6825
6826   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6827 }
6828
6829 /**
6830   * @brief  TIM DMA Capture half complete callback.
6831   * @param  hdma pointer to DMA handle.
6832   * @retval None
6833   */
6834 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6835 {
6836   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6837
6838   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6839   {
6840     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6841   }
6842   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6843   {
6844     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6845   }
6846   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6847   {
6848     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6849   }
6850   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6851   {
6852     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6853   }
6854   else
6855   {
6856     /* nothing to do */
6857   }
6858
6859 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6860   htim->IC_CaptureHalfCpltCallback(htim);
6861 #else
6862   HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6863 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6864
6865   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6866 }
6867
6868 /**
6869   * @brief  TIM DMA Period Elapse complete callback.
6870   * @param  hdma pointer to DMA handle.
6871   * @retval None
6872   */
6873 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6874 {
6875   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6876
6877   if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6878   {
6879     htim->State = HAL_TIM_STATE_READY;
6880   }
6881
6882 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6883   htim->PeriodElapsedCallback(htim);
6884 #else
6885   HAL_TIM_PeriodElapsedCallback(htim);
6886 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6887 }
6888
6889 /**
6890   * @brief  TIM DMA Period Elapse half complete callback.
6891   * @param  hdma pointer to DMA handle.
6892   * @retval None
6893   */
6894 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6895 {
6896   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6897
6898 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6899   htim->PeriodElapsedHalfCpltCallback(htim);
6900 #else
6901   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6902 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6903 }
6904
6905 /**
6906   * @brief  TIM DMA Trigger callback.
6907   * @param  hdma pointer to DMA handle.
6908   * @retval None
6909   */
6910 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6911 {
6912   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6913
6914   if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6915   {
6916     htim->State = HAL_TIM_STATE_READY;
6917   }
6918
6919 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6920   htim->TriggerCallback(htim);
6921 #else
6922   HAL_TIM_TriggerCallback(htim);
6923 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6924 }
6925
6926 /**
6927   * @brief  TIM DMA Trigger half complete callback.
6928   * @param  hdma pointer to DMA handle.
6929   * @retval None
6930   */
6931 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6932 {
6933   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6934
6935 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6936   htim->TriggerHalfCpltCallback(htim);
6937 #else
6938   HAL_TIM_TriggerHalfCpltCallback(htim);
6939 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6940 }
6941
6942 /**
6943   * @brief  Time Base configuration
6944   * @param  TIMx TIM peripheral
6945   * @param  Structure TIM Base configuration structure
6946   * @retval None
6947   */
6948 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
6949 {
6950   uint32_t tmpcr1;
6951   tmpcr1 = TIMx->CR1;
6952
6953   /* Set TIM Time Base Unit parameters ---------------------------------------*/
6954   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6955   {
6956     /* Select the Counter Mode */
6957     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6958     tmpcr1 |= Structure->CounterMode;
6959   }
6960
6961   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6962   {
6963     /* Set the clock division */
6964     tmpcr1 &= ~TIM_CR1_CKD;
6965     tmpcr1 |= (uint32_t)Structure->ClockDivision;
6966   }
6967
6968   /* Set the auto-reload preload */
6969   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6970
6971   TIMx->CR1 = tmpcr1;
6972
6973   /* Set the Autoreload value */
6974   TIMx->ARR = (uint32_t)Structure->Period ;
6975
6976   /* Set the Prescaler value */
6977   TIMx->PSC = Structure->Prescaler;
6978
6979   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6980   {
6981     /* Set the Repetition Counter value */
6982     TIMx->RCR = Structure->RepetitionCounter;
6983   }
6984
6985   /* Generate an update event to reload the Prescaler
6986      and the repetition counter (only for advanced timer) value immediately */
6987   TIMx->EGR = TIM_EGR_UG;
6988
6989   /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
6990   if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
6991   {
6992     /* Clear the update flag */
6993     CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
6994   }
6995 }
6996
6997 /**
6998   * @brief  Timer Output Compare 1 configuration
6999   * @param  TIMx to select the TIM peripheral
7000   * @param  OC_Config The output configuration structure
7001   * @retval None
7002   */
7003 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7004 {
7005   uint32_t tmpccmrx;
7006   uint32_t tmpccer;
7007   uint32_t tmpcr2;
7008
7009   /* Get the TIMx CCER register value */
7010   tmpccer = TIMx->CCER;
7011
7012   /* Disable the Channel 1: Reset the CC1E Bit */
7013   TIMx->CCER &= ~TIM_CCER_CC1E;
7014
7015   /* Get the TIMx CR2 register value */
7016   tmpcr2 =  TIMx->CR2;
7017
7018   /* Get the TIMx CCMR1 register value */
7019   tmpccmrx = TIMx->CCMR1;
7020
7021   /* Reset the Output Compare Mode Bits */
7022   tmpccmrx &= ~TIM_CCMR1_OC1M;
7023   tmpccmrx &= ~TIM_CCMR1_CC1S;
7024   /* Select the Output Compare Mode */
7025   tmpccmrx |= OC_Config->OCMode;
7026
7027   /* Reset the Output Polarity level */
7028   tmpccer &= ~TIM_CCER_CC1P;
7029   /* Set the Output Compare Polarity */
7030   tmpccer |= OC_Config->OCPolarity;
7031
7032   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
7033   {
7034     /* Check parameters */
7035     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7036
7037     /* Reset the Output N Polarity level */
7038     tmpccer &= ~TIM_CCER_CC1NP;
7039     /* Set the Output N Polarity */
7040     tmpccer |= OC_Config->OCNPolarity;
7041     /* Reset the Output N State */
7042     tmpccer &= ~TIM_CCER_CC1NE;
7043   }
7044
7045   if (IS_TIM_BREAK_INSTANCE(TIMx))
7046   {
7047     /* Check parameters */
7048     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7049     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7050
7051     /* Reset the Output Compare and Output Compare N IDLE State */
7052     tmpcr2 &= ~TIM_CR2_OIS1;
7053     tmpcr2 &= ~TIM_CR2_OIS1N;
7054     /* Set the Output Idle state */
7055     tmpcr2 |= OC_Config->OCIdleState;
7056     /* Set the Output N Idle state */
7057     tmpcr2 |= OC_Config->OCNIdleState;
7058   }
7059
7060   /* Write to TIMx CR2 */
7061   TIMx->CR2 = tmpcr2;
7062
7063   /* Write to TIMx CCMR1 */
7064   TIMx->CCMR1 = tmpccmrx;
7065
7066   /* Set the Capture Compare Register value */
7067   TIMx->CCR1 = OC_Config->Pulse;
7068
7069   /* Write to TIMx CCER */
7070   TIMx->CCER = tmpccer;
7071 }
7072
7073 /**
7074   * @brief  Timer Output Compare 2 configuration
7075   * @param  TIMx to select the TIM peripheral
7076   * @param  OC_Config The output configuration structure
7077   * @retval None
7078   */
7079 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7080 {
7081   uint32_t tmpccmrx;
7082   uint32_t tmpccer;
7083   uint32_t tmpcr2;
7084
7085   /* Get the TIMx CCER register value */
7086   tmpccer = TIMx->CCER;
7087
7088   /* Disable the Channel 2: Reset the CC2E Bit */
7089   TIMx->CCER &= ~TIM_CCER_CC2E;
7090
7091   /* Get the TIMx CR2 register value */
7092   tmpcr2 =  TIMx->CR2;
7093
7094   /* Get the TIMx CCMR1 register value */
7095   tmpccmrx = TIMx->CCMR1;
7096
7097   /* Reset the Output Compare mode and Capture/Compare selection Bits */
7098   tmpccmrx &= ~TIM_CCMR1_OC2M;
7099   tmpccmrx &= ~TIM_CCMR1_CC2S;
7100
7101   /* Select the Output Compare Mode */
7102   tmpccmrx |= (OC_Config->OCMode << 8U);
7103
7104   /* Reset the Output Polarity level */
7105   tmpccer &= ~TIM_CCER_CC2P;
7106   /* Set the Output Compare Polarity */
7107   tmpccer |= (OC_Config->OCPolarity << 4U);
7108
7109   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
7110   {
7111     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7112
7113     /* Reset the Output N Polarity level */
7114     tmpccer &= ~TIM_CCER_CC2NP;
7115     /* Set the Output N Polarity */
7116     tmpccer |= (OC_Config->OCNPolarity << 4U);
7117     /* Reset the Output N State */
7118     tmpccer &= ~TIM_CCER_CC2NE;
7119   }
7120
7121   if (IS_TIM_BREAK_INSTANCE(TIMx))
7122   {
7123     /* Check parameters */
7124     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7125     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7126
7127     /* Reset the Output Compare and Output Compare N IDLE State */
7128     tmpcr2 &= ~TIM_CR2_OIS2;
7129     tmpcr2 &= ~TIM_CR2_OIS2N;
7130     /* Set the Output Idle state */
7131     tmpcr2 |= (OC_Config->OCIdleState << 2U);
7132     /* Set the Output N Idle state */
7133     tmpcr2 |= (OC_Config->OCNIdleState << 2U);
7134   }
7135
7136   /* Write to TIMx CR2 */
7137   TIMx->CR2 = tmpcr2;
7138
7139   /* Write to TIMx CCMR1 */
7140   TIMx->CCMR1 = tmpccmrx;
7141
7142   /* Set the Capture Compare Register value */
7143   TIMx->CCR2 = OC_Config->Pulse;
7144
7145   /* Write to TIMx CCER */
7146   TIMx->CCER = tmpccer;
7147 }
7148
7149 /**
7150   * @brief  Timer Output Compare 3 configuration
7151   * @param  TIMx to select the TIM peripheral
7152   * @param  OC_Config The output configuration structure
7153   * @retval None
7154   */
7155 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7156 {
7157   uint32_t tmpccmrx;
7158   uint32_t tmpccer;
7159   uint32_t tmpcr2;
7160
7161   /* Get the TIMx CCER register value */
7162   tmpccer = TIMx->CCER;
7163
7164   /* Disable the Channel 3: Reset the CC2E Bit */
7165   TIMx->CCER &= ~TIM_CCER_CC3E;
7166
7167   /* Get the TIMx CR2 register value */
7168   tmpcr2 =  TIMx->CR2;
7169
7170   /* Get the TIMx CCMR2 register value */
7171   tmpccmrx = TIMx->CCMR2;
7172
7173   /* Reset the Output Compare mode and Capture/Compare selection Bits */
7174   tmpccmrx &= ~TIM_CCMR2_OC3M;
7175   tmpccmrx &= ~TIM_CCMR2_CC3S;
7176   /* Select the Output Compare Mode */
7177   tmpccmrx |= OC_Config->OCMode;
7178
7179   /* Reset the Output Polarity level */
7180   tmpccer &= ~TIM_CCER_CC3P;
7181   /* Set the Output Compare Polarity */
7182   tmpccer |= (OC_Config->OCPolarity << 8U);
7183
7184   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7185   {
7186     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7187
7188     /* Reset the Output N Polarity level */
7189     tmpccer &= ~TIM_CCER_CC3NP;
7190     /* Set the Output N Polarity */
7191     tmpccer |= (OC_Config->OCNPolarity << 8U);
7192     /* Reset the Output N State */
7193     tmpccer &= ~TIM_CCER_CC3NE;
7194   }
7195
7196   if (IS_TIM_BREAK_INSTANCE(TIMx))
7197   {
7198     /* Check parameters */
7199     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7200     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7201
7202     /* Reset the Output Compare and Output Compare N IDLE State */
7203     tmpcr2 &= ~TIM_CR2_OIS3;
7204     tmpcr2 &= ~TIM_CR2_OIS3N;
7205     /* Set the Output Idle state */
7206     tmpcr2 |= (OC_Config->OCIdleState << 4U);
7207     /* Set the Output N Idle state */
7208     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7209   }
7210
7211   /* Write to TIMx CR2 */
7212   TIMx->CR2 = tmpcr2;
7213
7214   /* Write to TIMx CCMR2 */
7215   TIMx->CCMR2 = tmpccmrx;
7216
7217   /* Set the Capture Compare Register value */
7218   TIMx->CCR3 = OC_Config->Pulse;
7219
7220   /* Write to TIMx CCER */
7221   TIMx->CCER = tmpccer;
7222 }
7223
7224 /**
7225   * @brief  Timer Output Compare 4 configuration
7226   * @param  TIMx to select the TIM peripheral
7227   * @param  OC_Config The output configuration structure
7228   * @retval None
7229   */
7230 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7231 {
7232   uint32_t tmpccmrx;
7233   uint32_t tmpccer;
7234   uint32_t tmpcr2;
7235
7236   /* Get the TIMx CCER register value */
7237   tmpccer = TIMx->CCER;
7238
7239   /* Disable the Channel 4: Reset the CC4E Bit */
7240   TIMx->CCER &= ~TIM_CCER_CC4E;
7241
7242   /* Get the TIMx CR2 register value */
7243   tmpcr2 =  TIMx->CR2;
7244
7245   /* Get the TIMx CCMR2 register value */
7246   tmpccmrx = TIMx->CCMR2;
7247
7248   /* Reset the Output Compare mode and Capture/Compare selection Bits */
7249   tmpccmrx &= ~TIM_CCMR2_OC4M;
7250   tmpccmrx &= ~TIM_CCMR2_CC4S;
7251
7252   /* Select the Output Compare Mode */
7253   tmpccmrx |= (OC_Config->OCMode << 8U);
7254
7255   /* Reset the Output Polarity level */
7256   tmpccer &= ~TIM_CCER_CC4P;
7257   /* Set the Output Compare Polarity */
7258   tmpccer |= (OC_Config->OCPolarity << 12U);
7259
7260   if (IS_TIM_BREAK_INSTANCE(TIMx))
7261   {
7262     /* Check parameters */
7263     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7264
7265     /* Reset the Output Compare IDLE State */
7266     tmpcr2 &= ~TIM_CR2_OIS4;
7267
7268     /* Set the Output Idle state */
7269     tmpcr2 |= (OC_Config->OCIdleState << 6U);
7270   }
7271
7272   /* Write to TIMx CR2 */
7273   TIMx->CR2 = tmpcr2;
7274
7275   /* Write to TIMx CCMR2 */
7276   TIMx->CCMR2 = tmpccmrx;
7277
7278   /* Set the Capture Compare Register value */
7279   TIMx->CCR4 = OC_Config->Pulse;
7280
7281   /* Write to TIMx CCER */
7282   TIMx->CCER = tmpccer;
7283 }
7284
7285 /**
7286   * @brief  Timer Output Compare 5 configuration
7287   * @param  TIMx to select the TIM peripheral
7288   * @param  OC_Config The output configuration structure
7289   * @retval None
7290   */
7291 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
7292                               const TIM_OC_InitTypeDef *OC_Config)
7293 {
7294   uint32_t tmpccmrx;
7295   uint32_t tmpccer;
7296   uint32_t tmpcr2;
7297
7298   /* Get the TIMx CCER register value */
7299   tmpccer = TIMx->CCER;
7300
7301   /* Disable the output: Reset the CCxE Bit */
7302   TIMx->CCER &= ~TIM_CCER_CC5E;
7303
7304   /* Get the TIMx CR2 register value */
7305   tmpcr2 =  TIMx->CR2;
7306   /* Get the TIMx CCMR1 register value */
7307   tmpccmrx = TIMx->CCMR3;
7308
7309   /* Reset the Output Compare Mode Bits */
7310   tmpccmrx &= ~(TIM_CCMR3_OC5M);
7311   /* Select the Output Compare Mode */
7312   tmpccmrx |= OC_Config->OCMode;
7313
7314   /* Reset the Output Polarity level */
7315   tmpccer &= ~TIM_CCER_CC5P;
7316   /* Set the Output Compare Polarity */
7317   tmpccer |= (OC_Config->OCPolarity << 16U);
7318
7319   if (IS_TIM_BREAK_INSTANCE(TIMx))
7320   {
7321     /* Reset the Output Compare IDLE State */
7322     tmpcr2 &= ~TIM_CR2_OIS5;
7323     /* Set the Output Idle state */
7324     tmpcr2 |= (OC_Config->OCIdleState << 8U);
7325   }
7326   /* Write to TIMx CR2 */
7327   TIMx->CR2 = tmpcr2;
7328
7329   /* Write to TIMx CCMR3 */
7330   TIMx->CCMR3 = tmpccmrx;
7331
7332   /* Set the Capture Compare Register value */
7333   TIMx->CCR5 = OC_Config->Pulse;
7334
7335   /* Write to TIMx CCER */
7336   TIMx->CCER = tmpccer;
7337 }
7338
7339 /**
7340   * @brief  Timer Output Compare 6 configuration
7341   * @param  TIMx to select the TIM peripheral
7342   * @param  OC_Config The output configuration structure
7343   * @retval None
7344   */
7345 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
7346                               const TIM_OC_InitTypeDef *OC_Config)
7347 {
7348   uint32_t tmpccmrx;
7349   uint32_t tmpccer;
7350   uint32_t tmpcr2;
7351
7352   /* Get the TIMx CCER register value */
7353   tmpccer = TIMx->CCER;
7354
7355   /* Disable the output: Reset the CCxE Bit */
7356   TIMx->CCER &= ~TIM_CCER_CC6E;
7357
7358   /* Get the TIMx CR2 register value */
7359   tmpcr2 =  TIMx->CR2;
7360   /* Get the TIMx CCMR1 register value */
7361   tmpccmrx = TIMx->CCMR3;
7362
7363   /* Reset the Output Compare Mode Bits */
7364   tmpccmrx &= ~(TIM_CCMR3_OC6M);
7365   /* Select the Output Compare Mode */
7366   tmpccmrx |= (OC_Config->OCMode << 8U);
7367
7368   /* Reset the Output Polarity level */
7369   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
7370   /* Set the Output Compare Polarity */
7371   tmpccer |= (OC_Config->OCPolarity << 20U);
7372
7373   if (IS_TIM_BREAK_INSTANCE(TIMx))
7374   {
7375     /* Reset the Output Compare IDLE State */
7376     tmpcr2 &= ~TIM_CR2_OIS6;
7377     /* Set the Output Idle state */
7378     tmpcr2 |= (OC_Config->OCIdleState << 10U);
7379   }
7380
7381   /* Write to TIMx CR2 */
7382   TIMx->CR2 = tmpcr2;
7383
7384   /* Write to TIMx CCMR3 */
7385   TIMx->CCMR3 = tmpccmrx;
7386
7387   /* Set the Capture Compare Register value */
7388   TIMx->CCR6 = OC_Config->Pulse;
7389
7390   /* Write to TIMx CCER */
7391   TIMx->CCER = tmpccer;
7392 }
7393
7394 /**
7395   * @brief  Slave Timer configuration function
7396   * @param  htim TIM handle
7397   * @param  sSlaveConfig Slave timer configuration
7398   * @retval None
7399   */
7400 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7401                                                   const TIM_SlaveConfigTypeDef *sSlaveConfig)
7402 {
7403   HAL_StatusTypeDef status = HAL_OK;
7404   uint32_t tmpsmcr;
7405   uint32_t tmpccmr1;
7406   uint32_t tmpccer;
7407
7408   /* Get the TIMx SMCR register value */
7409   tmpsmcr = htim->Instance->SMCR;
7410
7411   /* Reset the Trigger Selection Bits */
7412   tmpsmcr &= ~TIM_SMCR_TS;
7413   /* Set the Input Trigger source */
7414   tmpsmcr |= sSlaveConfig->InputTrigger;
7415
7416   /* Reset the slave mode Bits */
7417   tmpsmcr &= ~TIM_SMCR_SMS;
7418   /* Set the slave mode */
7419   tmpsmcr |= sSlaveConfig->SlaveMode;
7420
7421   /* Write to TIMx SMCR */
7422   htim->Instance->SMCR = tmpsmcr;
7423
7424   /* Configure the trigger prescaler, filter, and polarity */
7425   switch (sSlaveConfig->InputTrigger)
7426   {
7427     case TIM_TS_ETRF:
7428     {
7429       /* Check the parameters */
7430       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7431       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7432       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7433       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7434       /* Configure the ETR Trigger source */
7435       TIM_ETR_SetConfig(htim->Instance,
7436                         sSlaveConfig->TriggerPrescaler,
7437                         sSlaveConfig->TriggerPolarity,
7438                         sSlaveConfig->TriggerFilter);
7439       break;
7440     }
7441
7442     case TIM_TS_TI1F_ED:
7443     {
7444       /* Check the parameters */
7445       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7446       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7447
7448       if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
7449       {
7450         return HAL_ERROR;
7451       }
7452
7453       /* Disable the Channel 1: Reset the CC1E Bit */
7454       tmpccer = htim->Instance->CCER;
7455       htim->Instance->CCER &= ~TIM_CCER_CC1E;
7456       tmpccmr1 = htim->Instance->CCMR1;
7457
7458       /* Set the filter */
7459       tmpccmr1 &= ~TIM_CCMR1_IC1F;
7460       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7461
7462       /* Write to TIMx CCMR1 and CCER registers */
7463       htim->Instance->CCMR1 = tmpccmr1;
7464       htim->Instance->CCER = tmpccer;
7465       break;
7466     }
7467
7468     case TIM_TS_TI1FP1:
7469     {
7470       /* Check the parameters */
7471       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7472       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7473       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7474
7475       /* Configure TI1 Filter and Polarity */
7476       TIM_TI1_ConfigInputStage(htim->Instance,
7477                                sSlaveConfig->TriggerPolarity,
7478                                sSlaveConfig->TriggerFilter);
7479       break;
7480     }
7481
7482     case TIM_TS_TI2FP2:
7483     {
7484       /* Check the parameters */
7485       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7486       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7487       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7488
7489       /* Configure TI2 Filter and Polarity */
7490       TIM_TI2_ConfigInputStage(htim->Instance,
7491                                sSlaveConfig->TriggerPolarity,
7492                                sSlaveConfig->TriggerFilter);
7493       break;
7494     }
7495
7496     case TIM_TS_ITR0:
7497     case TIM_TS_ITR1:
7498     case TIM_TS_ITR2:
7499     case TIM_TS_ITR3:
7500     case TIM_TS_ITR4:
7501     case TIM_TS_ITR5:
7502     case TIM_TS_ITR6:
7503     case TIM_TS_ITR7:
7504     case TIM_TS_ITR8:
7505     case TIM_TS_ITR9:
7506     case TIM_TS_ITR10:
7507     case TIM_TS_ITR11:
7508     case TIM_TS_ITR12:
7509     case TIM_TS_ITR13:
7510     {
7511       /* Check the parameter */
7512       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7513       break;
7514     }
7515
7516     default:
7517       status = HAL_ERROR;
7518       break;
7519   }
7520
7521   return status;
7522 }
7523
7524 /**
7525   * @brief  Configure the TI1 as Input.
7526   * @param  TIMx to select the TIM peripheral.
7527   * @param  TIM_ICPolarity The Input Polarity.
7528   *          This parameter can be one of the following values:
7529   *            @arg TIM_ICPOLARITY_RISING
7530   *            @arg TIM_ICPOLARITY_FALLING
7531   *            @arg TIM_ICPOLARITY_BOTHEDGE
7532   * @param  TIM_ICSelection specifies the input to be used.
7533   *          This parameter can be one of the following values:
7534   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7535   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7536   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7537   * @param  TIM_ICFilter Specifies the Input Capture Filter.
7538   *          This parameter must be a value between 0x00 and 0x0F.
7539   * @retval None
7540   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7541   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7542   *        protected against un-initialized filter and polarity values.
7543   */
7544 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7545                        uint32_t TIM_ICFilter)
7546 {
7547   uint32_t tmpccmr1;
7548   uint32_t tmpccer;
7549
7550   /* Disable the Channel 1: Reset the CC1E Bit */
7551   tmpccer = TIMx->CCER;
7552   TIMx->CCER &= ~TIM_CCER_CC1E;
7553   tmpccmr1 = TIMx->CCMR1;
7554
7555   /* Select the Input */
7556   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7557   {
7558     tmpccmr1 &= ~TIM_CCMR1_CC1S;
7559     tmpccmr1 |= TIM_ICSelection;
7560   }
7561   else
7562   {
7563     tmpccmr1 |= TIM_CCMR1_CC1S_0;
7564   }
7565
7566   /* Set the filter */
7567   tmpccmr1 &= ~TIM_CCMR1_IC1F;
7568   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7569
7570   /* Select the Polarity and set the CC1E Bit */
7571   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7572   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7573
7574   /* Write to TIMx CCMR1 and CCER registers */
7575   TIMx->CCMR1 = tmpccmr1;
7576   TIMx->CCER = tmpccer;
7577 }
7578
7579 /**
7580   * @brief  Configure the Polarity and Filter for TI1.
7581   * @param  TIMx to select the TIM peripheral.
7582   * @param  TIM_ICPolarity The Input Polarity.
7583   *          This parameter can be one of the following values:
7584   *            @arg TIM_ICPOLARITY_RISING
7585   *            @arg TIM_ICPOLARITY_FALLING
7586   *            @arg TIM_ICPOLARITY_BOTHEDGE
7587   * @param  TIM_ICFilter Specifies the Input Capture Filter.
7588   *          This parameter must be a value between 0x00 and 0x0F.
7589   * @retval None
7590   */
7591 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7592 {
7593   uint32_t tmpccmr1;
7594   uint32_t tmpccer;
7595
7596   /* Disable the Channel 1: Reset the CC1E Bit */
7597   tmpccer = TIMx->CCER;
7598   TIMx->CCER &= ~TIM_CCER_CC1E;
7599   tmpccmr1 = TIMx->CCMR1;
7600
7601   /* Set the filter */
7602   tmpccmr1 &= ~TIM_CCMR1_IC1F;
7603   tmpccmr1 |= (TIM_ICFilter << 4U);
7604
7605   /* Select the Polarity and set the CC1E Bit */
7606   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7607   tmpccer |= TIM_ICPolarity;
7608
7609   /* Write to TIMx CCMR1 and CCER registers */
7610   TIMx->CCMR1 = tmpccmr1;
7611   TIMx->CCER = tmpccer;
7612 }
7613
7614 /**
7615   * @brief  Configure the TI2 as Input.
7616   * @param  TIMx to select the TIM peripheral
7617   * @param  TIM_ICPolarity The Input Polarity.
7618   *          This parameter can be one of the following values:
7619   *            @arg TIM_ICPOLARITY_RISING
7620   *            @arg TIM_ICPOLARITY_FALLING
7621   *            @arg TIM_ICPOLARITY_BOTHEDGE
7622   * @param  TIM_ICSelection specifies the input to be used.
7623   *          This parameter can be one of the following values:
7624   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7625   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7626   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7627   * @param  TIM_ICFilter Specifies the Input Capture Filter.
7628   *          This parameter must be a value between 0x00 and 0x0F.
7629   * @retval None
7630   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7631   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7632   *        protected against un-initialized filter and polarity values.
7633   */
7634 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7635                               uint32_t TIM_ICFilter)
7636 {
7637   uint32_t tmpccmr1;
7638   uint32_t tmpccer;
7639
7640   /* Disable the Channel 2: Reset the CC2E Bit */
7641   tmpccer = TIMx->CCER;
7642   TIMx->CCER &= ~TIM_CCER_CC2E;
7643   tmpccmr1 = TIMx->CCMR1;
7644
7645   /* Select the Input */
7646   tmpccmr1 &= ~TIM_CCMR1_CC2S;
7647   tmpccmr1 |= (TIM_ICSelection << 8U);
7648
7649   /* Set the filter */
7650   tmpccmr1 &= ~TIM_CCMR1_IC2F;
7651   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7652
7653   /* Select the Polarity and set the CC2E Bit */
7654   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7655   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7656
7657   /* Write to TIMx CCMR1 and CCER registers */
7658   TIMx->CCMR1 = tmpccmr1 ;
7659   TIMx->CCER = tmpccer;
7660 }
7661
7662 /**
7663   * @brief  Configure the Polarity and Filter for TI2.
7664   * @param  TIMx to select the TIM peripheral.
7665   * @param  TIM_ICPolarity The Input Polarity.
7666   *          This parameter can be one of the following values:
7667   *            @arg TIM_ICPOLARITY_RISING
7668   *            @arg TIM_ICPOLARITY_FALLING
7669   *            @arg TIM_ICPOLARITY_BOTHEDGE
7670   * @param  TIM_ICFilter Specifies the Input Capture Filter.
7671   *          This parameter must be a value between 0x00 and 0x0F.
7672   * @retval None
7673   */
7674 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7675 {
7676   uint32_t tmpccmr1;
7677   uint32_t tmpccer;
7678
7679   /* Disable the Channel 2: Reset the CC2E Bit */
7680   tmpccer = TIMx->CCER;
7681   TIMx->CCER &= ~TIM_CCER_CC2E;
7682   tmpccmr1 = TIMx->CCMR1;
7683
7684   /* Set the filter */
7685   tmpccmr1 &= ~TIM_CCMR1_IC2F;
7686   tmpccmr1 |= (TIM_ICFilter << 12U);
7687
7688   /* Select the Polarity and set the CC2E Bit */
7689   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7690   tmpccer |= (TIM_ICPolarity << 4U);
7691
7692   /* Write to TIMx CCMR1 and CCER registers */
7693   TIMx->CCMR1 = tmpccmr1 ;
7694   TIMx->CCER = tmpccer;
7695 }
7696
7697 /**
7698   * @brief  Configure the TI3 as Input.
7699   * @param  TIMx to select the TIM peripheral
7700   * @param  TIM_ICPolarity The Input Polarity.
7701   *          This parameter can be one of the following values:
7702   *            @arg TIM_ICPOLARITY_RISING
7703   *            @arg TIM_ICPOLARITY_FALLING
7704   *            @arg TIM_ICPOLARITY_BOTHEDGE
7705   * @param  TIM_ICSelection specifies the input to be used.
7706   *          This parameter can be one of the following values:
7707   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7708   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7709   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7710   * @param  TIM_ICFilter Specifies the Input Capture Filter.
7711   *          This parameter must be a value between 0x00 and 0x0F.
7712   * @retval None
7713   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7714   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7715   *        protected against un-initialized filter and polarity values.
7716   */
7717 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7718                               uint32_t TIM_ICFilter)
7719 {
7720   uint32_t tmpccmr2;
7721   uint32_t tmpccer;
7722
7723   /* Disable the Channel 3: Reset the CC3E Bit */
7724   tmpccer = TIMx->CCER;
7725   TIMx->CCER &= ~TIM_CCER_CC3E;
7726   tmpccmr2 = TIMx->CCMR2;
7727
7728   /* Select the Input */
7729   tmpccmr2 &= ~TIM_CCMR2_CC3S;
7730   tmpccmr2 |= TIM_ICSelection;
7731
7732   /* Set the filter */
7733   tmpccmr2 &= ~TIM_CCMR2_IC3F;
7734   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7735
7736   /* Select the Polarity and set the CC3E Bit */
7737   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
7738   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
7739
7740   /* Write to TIMx CCMR2 and CCER registers */
7741   TIMx->CCMR2 = tmpccmr2;
7742   TIMx->CCER = tmpccer;
7743 }
7744
7745 /**
7746   * @brief  Configure the TI4 as Input.
7747   * @param  TIMx to select the TIM peripheral
7748   * @param  TIM_ICPolarity The Input Polarity.
7749   *          This parameter can be one of the following values:
7750   *            @arg TIM_ICPOLARITY_RISING
7751   *            @arg TIM_ICPOLARITY_FALLING
7752   *            @arg TIM_ICPOLARITY_BOTHEDGE
7753   * @param  TIM_ICSelection specifies the input to be used.
7754   *          This parameter can be one of the following values:
7755   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7756   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7757   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7758   * @param  TIM_ICFilter Specifies the Input Capture Filter.
7759   *          This parameter must be a value between 0x00 and 0x0F.
7760   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7761   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7762   *        protected against un-initialized filter and polarity values.
7763   * @retval None
7764   */
7765 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7766                               uint32_t TIM_ICFilter)
7767 {
7768   uint32_t tmpccmr2;
7769   uint32_t tmpccer;
7770
7771   /* Disable the Channel 4: Reset the CC4E Bit */
7772   tmpccer = TIMx->CCER;
7773   TIMx->CCER &= ~TIM_CCER_CC4E;
7774   tmpccmr2 = TIMx->CCMR2;
7775
7776   /* Select the Input */
7777   tmpccmr2 &= ~TIM_CCMR2_CC4S;
7778   tmpccmr2 |= (TIM_ICSelection << 8U);
7779
7780   /* Set the filter */
7781   tmpccmr2 &= ~TIM_CCMR2_IC4F;
7782   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7783
7784   /* Select the Polarity and set the CC4E Bit */
7785   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7786   tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7787
7788   /* Write to TIMx CCMR2 and CCER registers */
7789   TIMx->CCMR2 = tmpccmr2;
7790   TIMx->CCER = tmpccer ;
7791 }
7792
7793 /**
7794   * @brief  Selects the Input Trigger source
7795   * @param  TIMx to select the TIM peripheral
7796   * @param  InputTriggerSource The Input Trigger source.
7797   *          This parameter can be one of the following values:
7798   *            @arg TIM_TS_ITR0: Internal Trigger 0
7799   *            @arg TIM_TS_ITR1: Internal Trigger 1
7800   *            @arg TIM_TS_ITR2: Internal Trigger 2
7801   *            @arg TIM_TS_ITR3: Internal Trigger 3
7802   *            @arg TIM_TS_ITR4: Internal Trigger 4  (*)
7803   *            @arg TIM_TS_ITR5: Internal Trigger 5
7804   *            @arg TIM_TS_ITR6: Internal Trigger 6
7805   *            @arg TIM_TS_ITR7: Internal Trigger 7
7806   *            @arg TIM_TS_ITR8: Internal Trigger 8  (*)
7807   *            @arg TIM_TS_ITR9: Internal Trigger 9  (*)
7808   *            @arg TIM_TS_ITR10: Internal Trigger 10 (*)
7809   *            @arg TIM_TS_ITR11: Internal Trigger 11 (*)
7810   *            @arg TIM_TS_ITR12: Internal Trigger 12 (*)
7811   *            @arg TIM_TS_ITR13: Internal Trigger 13 (*)
7812   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7813   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7814   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7815   *            @arg TIM_TS_ETRF: External Trigger input
7816   *
7817   *       (*)  Value not defined in all devices.
7818   *
7819   * @retval None
7820   */
7821 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7822 {
7823   uint32_t tmpsmcr;
7824
7825   /* Get the TIMx SMCR register value */
7826   tmpsmcr = TIMx->SMCR;
7827   /* Reset the TS Bits */
7828   tmpsmcr &= ~TIM_SMCR_TS;
7829   /* Set the Input Trigger source and the slave mode*/
7830   tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7831   /* Write to TIMx SMCR */
7832   TIMx->SMCR = tmpsmcr;
7833 }
7834 /**
7835   * @brief  Configures the TIMx External Trigger (ETR).
7836   * @param  TIMx to select the TIM peripheral
7837   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
7838   *          This parameter can be one of the following values:
7839   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7840   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7841   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7842   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7843   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
7844   *          This parameter can be one of the following values:
7845   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7846   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7847   * @param  ExtTRGFilter External Trigger Filter.
7848   *          This parameter must be a value between 0x00 and 0x0F
7849   * @retval None
7850   */
7851 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7852                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7853 {
7854   uint32_t tmpsmcr;
7855
7856   tmpsmcr = TIMx->SMCR;
7857
7858   /* Reset the ETR Bits */
7859   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7860
7861   /* Set the Prescaler, the Filter value and the Polarity */
7862   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7863
7864   /* Write to TIMx SMCR */
7865   TIMx->SMCR = tmpsmcr;
7866 }
7867
7868 /**
7869   * @brief  Enables or disables the TIM Capture Compare Channel x.
7870   * @param  TIMx to select the TIM peripheral
7871   * @param  Channel specifies the TIM Channel
7872   *          This parameter can be one of the following values:
7873   *            @arg TIM_CHANNEL_1: TIM Channel 1
7874   *            @arg TIM_CHANNEL_2: TIM Channel 2
7875   *            @arg TIM_CHANNEL_3: TIM Channel 3
7876   *            @arg TIM_CHANNEL_4: TIM Channel 4
7877   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
7878   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
7879   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
7880   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7881   * @retval None
7882   */
7883 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7884 {
7885   uint32_t tmp;
7886
7887   /* Check the parameters */
7888   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7889   assert_param(IS_TIM_CHANNELS(Channel));
7890
7891   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7892
7893   /* Reset the CCxE Bit */
7894   TIMx->CCER &= ~tmp;
7895
7896   /* Set or reset the CCxE Bit */
7897   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7898 }
7899
7900 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7901 /**
7902   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
7903   * @param  htim pointer to a TIM_HandleTypeDef structure that contains
7904   *                the configuration information for TIM module.
7905   * @retval None
7906   */
7907 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7908 {
7909   /* Reset the TIM callback to the legacy weak callbacks */
7910   htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
7911   htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
7912   htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
7913   htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
7914   htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
7915   htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
7916   htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
7917   htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
7918   htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
7919   htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
7920   htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
7921   htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
7922   htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
7923   htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
7924 }
7925 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7926
7927 /**
7928   * @}
7929   */
7930
7931 #endif /* HAL_TIM_MODULE_ENABLED */
7932 /**
7933   * @}
7934   */
7935
7936 /**
7937   * @}
7938   */