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0171 #include "stm32h7xx_hal.h"
0172
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0181
0182
0183 #ifdef HAL_SWPMI_MODULE_ENABLED
0184
0185
0186
0187
0188
0189
0190
0191 #define SWPMI_TIMEOUT_VALUE 22000U
0192 #define SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE 2000U
0193
0194
0195
0196
0197
0198
0199
0200
0201 static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
0202 static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
0203 static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
0204 static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
0205 static void SWPMI_DMAError(DMA_HandleTypeDef *hdma);
0206 static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
0207 static void SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi);
0208 static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi);
0209 static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi);
0210 static void SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi);
0211 static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi);
0212 static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout);
0213
0214
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0216
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0240
0241
0242 HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi)
0243 {
0244 HAL_StatusTypeDef status = HAL_OK;
0245 uint32_t tickstart = HAL_GetTick();
0246
0247
0248 if (hswpmi == NULL)
0249 {
0250 status = HAL_ERROR;
0251 }
0252 else
0253 {
0254
0255 assert_param(IS_SWPMI_VOLTAGE_CLASS(hswpmi->Init.VoltageClass));
0256 assert_param(IS_SWPMI_BITRATE_VALUE(hswpmi->Init.BitRate));
0257 assert_param(IS_SWPMI_TX_BUFFERING_MODE(hswpmi->Init.TxBufferingMode));
0258 assert_param(IS_SWPMI_RX_BUFFERING_MODE(hswpmi->Init.RxBufferingMode));
0259
0260 if (hswpmi->State == HAL_SWPMI_STATE_RESET)
0261 {
0262
0263 hswpmi->Lock = HAL_UNLOCKED;
0264
0265 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
0266
0267 hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback;
0268 hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback;
0269 hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback;
0270 hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback;
0271 hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback;
0272
0273
0274 if (hswpmi->MspInitCallback == NULL)
0275 {
0276 hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
0277 }
0278 hswpmi->MspInitCallback(hswpmi);
0279 #else
0280
0281 HAL_SWPMI_MspInit(hswpmi);
0282 #endif
0283 }
0284
0285 hswpmi->State = HAL_SWPMI_STATE_BUSY;
0286
0287
0288 CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
0289
0290
0291 WRITE_REG(hswpmi->Instance->ICR, 0x099F);
0292
0293
0294 MODIFY_REG(hswpmi->Instance->OR, SWPMI_OR_CLASS, hswpmi->Init.VoltageClass);
0295
0296
0297
0298 WRITE_REG(hswpmi->Instance->BRR, hswpmi->Init.BitRate);
0299
0300
0301 MODIFY_REG(hswpmi->Instance->CR, \
0302 SWPMI_CR_RXDMA | SWPMI_CR_TXDMA | SWPMI_CR_RXMODE | SWPMI_CR_TXMODE, \
0303 hswpmi->Init.TxBufferingMode | hswpmi->Init.RxBufferingMode);
0304
0305
0306 SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPEN);
0307
0308 if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK)
0309 {
0310 status = HAL_TIMEOUT;
0311 }
0312
0313 if (status == HAL_OK)
0314 {
0315 hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
0316 hswpmi->State = HAL_SWPMI_STATE_READY;
0317
0318
0319 SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
0320 }
0321 else
0322 {
0323 hswpmi->ErrorCode = HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY;
0324 hswpmi->State = HAL_SWPMI_STATE_ERROR;
0325 }
0326 }
0327
0328 return status;
0329 }
0330
0331
0332
0333
0334
0335
0336 HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi)
0337 {
0338 HAL_StatusTypeDef status = HAL_OK;
0339
0340
0341 if (hswpmi == NULL)
0342 {
0343 status = HAL_ERROR;
0344 }
0345 else
0346 {
0347
0348 assert_param(IS_SWPMI_INSTANCE(hswpmi->Instance));
0349
0350 hswpmi->State = HAL_SWPMI_STATE_BUSY;
0351
0352
0353 CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
0354
0355
0356 CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
0357
0358
0359 CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPEN);
0360
0361
0362
0363 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
0364 if (hswpmi->MspDeInitCallback == NULL)
0365 {
0366 hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
0367 }
0368 hswpmi->MspDeInitCallback(hswpmi);
0369 #else
0370 HAL_SWPMI_MspDeInit(hswpmi);
0371 #endif
0372
0373 hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
0374 hswpmi->State = HAL_SWPMI_STATE_RESET;
0375
0376
0377 __HAL_UNLOCK(hswpmi);
0378 }
0379
0380 return status;
0381 }
0382
0383
0384
0385
0386
0387
0388 __weak void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi)
0389 {
0390
0391 UNUSED(hswpmi);
0392
0393
0394
0395
0396 }
0397
0398
0399
0400
0401
0402
0403 __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi)
0404 {
0405
0406 UNUSED(hswpmi);
0407
0408
0409
0410
0411 }
0412
0413 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
0414
0415
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0429
0430 HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi,
0431 HAL_SWPMI_CallbackIDTypeDef CallbackID,
0432 pSWPMI_CallbackTypeDef pCallback)
0433 {
0434 HAL_StatusTypeDef status = HAL_OK;
0435
0436 if (pCallback == NULL)
0437 {
0438
0439 hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
0440
0441 status = HAL_ERROR;
0442 }
0443 else
0444 {
0445 if (hswpmi->State == HAL_SWPMI_STATE_READY)
0446 {
0447 switch (CallbackID)
0448 {
0449 case HAL_SWPMI_RX_COMPLETE_CB_ID :
0450 hswpmi->RxCpltCallback = pCallback;
0451 break;
0452 case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
0453 hswpmi->RxHalfCpltCallback = pCallback;
0454 break;
0455 case HAL_SWPMI_TX_COMPLETE_CB_ID :
0456 hswpmi->TxCpltCallback = pCallback;
0457 break;
0458 case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
0459 hswpmi->TxHalfCpltCallback = pCallback;
0460 break;
0461 case HAL_SWPMI_ERROR_CB_ID :
0462 hswpmi->ErrorCallback = pCallback;
0463 break;
0464 case HAL_SWPMI_MSPINIT_CB_ID :
0465 hswpmi->MspInitCallback = pCallback;
0466 break;
0467 case HAL_SWPMI_MSPDEINIT_CB_ID :
0468 hswpmi->MspDeInitCallback = pCallback;
0469 break;
0470 default :
0471
0472 hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
0473
0474 status = HAL_ERROR;
0475 break;
0476 }
0477 }
0478 else if (hswpmi->State == HAL_SWPMI_STATE_RESET)
0479 {
0480 switch (CallbackID)
0481 {
0482 case HAL_SWPMI_MSPINIT_CB_ID :
0483 hswpmi->MspInitCallback = pCallback;
0484 break;
0485 case HAL_SWPMI_MSPDEINIT_CB_ID :
0486 hswpmi->MspDeInitCallback = pCallback;
0487 break;
0488 default :
0489
0490 hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
0491
0492 status = HAL_ERROR;
0493 break;
0494 }
0495 }
0496 else
0497 {
0498
0499 hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
0500
0501 status = HAL_ERROR;
0502 }
0503 }
0504 return status;
0505 }
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0507
0508
0509
0510
0511
0512
0513
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0516
0517
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0520
0521
0522 HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpmi,
0523 HAL_SWPMI_CallbackIDTypeDef CallbackID)
0524 {
0525 HAL_StatusTypeDef status = HAL_OK;
0526
0527 if (hswpmi->State == HAL_SWPMI_STATE_READY)
0528 {
0529 switch (CallbackID)
0530 {
0531 case HAL_SWPMI_RX_COMPLETE_CB_ID :
0532 hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback;
0533 break;
0534 case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
0535 hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback;
0536 break;
0537 case HAL_SWPMI_TX_COMPLETE_CB_ID :
0538 hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback;
0539 break;
0540 case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
0541 hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback;
0542 break;
0543 case HAL_SWPMI_ERROR_CB_ID :
0544 hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback;
0545 break;
0546 case HAL_SWPMI_MSPINIT_CB_ID :
0547 hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
0548 break;
0549 case HAL_SWPMI_MSPDEINIT_CB_ID :
0550 hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
0551 break;
0552 default :
0553
0554 hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
0555
0556 status = HAL_ERROR;
0557 break;
0558 }
0559 }
0560 else if (hswpmi->State == HAL_SWPMI_STATE_RESET)
0561 {
0562 switch (CallbackID)
0563 {
0564 case HAL_SWPMI_MSPINIT_CB_ID :
0565 hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
0566 break;
0567 case HAL_SWPMI_MSPDEINIT_CB_ID :
0568 hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
0569 break;
0570 default :
0571
0572 hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
0573
0574 status = HAL_ERROR;
0575 break;
0576 }
0577 }
0578 else
0579 {
0580
0581 hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
0582
0583 status = HAL_ERROR;
0584 }
0585 return status;
0586 }
0587 #endif
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0657
0658 HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
0659 {
0660 uint32_t tickstart = HAL_GetTick();
0661 HAL_StatusTypeDef status = HAL_OK;
0662 HAL_SWPMI_StateTypeDef tmp_state;
0663 uint32_t *ptmp_data;
0664 uint32_t tmp_size;
0665
0666 if ((pData == NULL) || (Size == 0U))
0667 {
0668 status = HAL_ERROR;
0669 }
0670 else
0671 {
0672
0673 __HAL_LOCK(hswpmi);
0674
0675 tmp_state = hswpmi->State;
0676 if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
0677 {
0678
0679 if (tmp_state == HAL_SWPMI_STATE_READY)
0680 {
0681 hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
0682
0683
0684 __HAL_SWPMI_DISABLE_IT(hswpmi, SWPMI_IT_TCIE | SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
0685
0686
0687 __HAL_SWPMI_CLEAR_FLAG(hswpmi, SWPMI_FLAG_TXBEF | SWPMI_FLAG_TXUNRF | SWPMI_FLAG_TCF);
0688
0689
0690 SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
0691 }
0692 else
0693 {
0694 hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
0695 }
0696
0697 ptmp_data = pData;
0698 tmp_size = Size;
0699 do
0700 {
0701
0702 if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE))
0703 {
0704 hswpmi->Instance->TDR = *ptmp_data;
0705 ptmp_data++;
0706 tmp_size--;
0707 }
0708 else
0709 {
0710
0711 if (Timeout != HAL_MAX_DELAY)
0712 {
0713 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
0714 {
0715 status = HAL_TIMEOUT;
0716 break;
0717 }
0718 }
0719 }
0720 }
0721 while (tmp_size != 0U);
0722
0723
0724 if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK)
0725 {
0726
0727 hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT;
0728
0729 status = HAL_TIMEOUT;
0730 }
0731
0732 if (status == HAL_OK)
0733 {
0734
0735 if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
0736 {
0737 hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
0738 }
0739 else
0740 {
0741 hswpmi->State = HAL_SWPMI_STATE_READY;
0742 }
0743 }
0744 }
0745 else
0746 {
0747 status = HAL_BUSY;
0748 }
0749 }
0750
0751 if ((status != HAL_OK) && (status != HAL_BUSY))
0752 {
0753 hswpmi->State = HAL_SWPMI_STATE_READY;
0754 }
0755
0756 __HAL_UNLOCK(hswpmi);
0757
0758 return status;
0759 }
0760
0761
0762
0763
0764
0765
0766
0767
0768
0769
0770 HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
0771 {
0772 uint32_t tickstart = HAL_GetTick();
0773 HAL_StatusTypeDef status = HAL_OK;
0774 HAL_SWPMI_StateTypeDef tmp_state;
0775 uint32_t *ptmp_data;
0776 uint32_t tmp_size;
0777
0778 if ((pData == NULL) || (Size == 0U))
0779 {
0780 status = HAL_ERROR;
0781 }
0782 else
0783 {
0784
0785 __HAL_LOCK(hswpmi);
0786
0787 tmp_state = hswpmi->State;
0788 if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
0789 {
0790
0791 if (tmp_state == HAL_SWPMI_STATE_READY)
0792 {
0793 hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
0794
0795
0796 CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_SRIE | SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
0797
0798
0799 SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
0800 }
0801 else
0802 {
0803 hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
0804 }
0805
0806 ptmp_data = pData;
0807 tmp_size = Size;
0808 do
0809 {
0810
0811 if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE))
0812 {
0813 *ptmp_data = hswpmi->Instance->RDR;
0814 ptmp_data++;
0815 tmp_size--;
0816 }
0817 else
0818 {
0819
0820 if (Timeout != HAL_MAX_DELAY)
0821 {
0822 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
0823 {
0824 status = HAL_TIMEOUT;
0825 break;
0826 }
0827 }
0828 }
0829 }
0830 while (tmp_size != 0U);
0831
0832 if (status == HAL_OK)
0833 {
0834 if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF))
0835 {
0836
0837 WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
0838 }
0839
0840
0841 if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
0842 {
0843 hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
0844 }
0845 else
0846 {
0847 hswpmi->State = HAL_SWPMI_STATE_READY;
0848 }
0849 }
0850 }
0851 else
0852 {
0853 status = HAL_BUSY;
0854 }
0855 }
0856
0857 if ((status != HAL_OK) && (status != HAL_BUSY))
0858 {
0859 hswpmi->State = HAL_SWPMI_STATE_READY;
0860 }
0861
0862 __HAL_UNLOCK(hswpmi);
0863
0864 return status;
0865 }
0866
0867
0868
0869
0870
0871
0872
0873
0874
0875 HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
0876 {
0877 HAL_StatusTypeDef status = HAL_OK;
0878 HAL_SWPMI_StateTypeDef tmp_state;
0879
0880 if ((pData == NULL) || (Size == 0U))
0881 {
0882 status = HAL_ERROR;
0883 }
0884 else
0885 {
0886
0887 __HAL_LOCK(hswpmi);
0888
0889 tmp_state = hswpmi->State;
0890 if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
0891 {
0892
0893 hswpmi->pTxBuffPtr = pData;
0894 hswpmi->TxXferSize = Size;
0895 hswpmi->TxXferCount = Size;
0896 hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
0897
0898
0899 if (tmp_state == HAL_SWPMI_STATE_READY)
0900 {
0901 hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
0902
0903
0904 SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
0905 }
0906 else
0907 {
0908 hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
0909 }
0910
0911
0912 __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE);
0913
0914
0915 __HAL_UNLOCK(hswpmi);
0916
0917
0918
0919
0920
0921 __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TIE | SWPMI_IT_TXBEIE | SWPMI_IT_TCIE);
0922 }
0923 else
0924 {
0925 status = HAL_BUSY;
0926
0927
0928 __HAL_UNLOCK(hswpmi);
0929 }
0930 }
0931
0932 return status;
0933 }
0934
0935
0936
0937
0938
0939
0940
0941
0942 HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
0943 {
0944 HAL_StatusTypeDef status = HAL_OK;
0945 HAL_SWPMI_StateTypeDef tmp_state;
0946
0947 if ((pData == NULL) || (Size == 0U))
0948 {
0949 status = HAL_ERROR;
0950 }
0951 else
0952 {
0953
0954 __HAL_LOCK(hswpmi);
0955
0956 tmp_state = hswpmi->State;
0957 if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
0958 {
0959
0960 hswpmi->pRxBuffPtr = pData;
0961 hswpmi->RxXferSize = Size;
0962 hswpmi->RxXferCount = Size;
0963 hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
0964
0965
0966 if (tmp_state == HAL_SWPMI_STATE_READY)
0967 {
0968 hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
0969
0970
0971 SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
0972 }
0973 else
0974 {
0975 hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
0976 }
0977
0978
0979 __HAL_UNLOCK(hswpmi);
0980
0981
0982
0983
0984 __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
0985 }
0986 else
0987 {
0988 status = HAL_BUSY;
0989
0990
0991 __HAL_UNLOCK(hswpmi);
0992 }
0993 }
0994
0995 return status;
0996 }
0997
0998
0999
1000
1001
1002
1003
1004
1005 HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
1006 {
1007 HAL_StatusTypeDef status = HAL_OK;
1008 HAL_SWPMI_StateTypeDef tmp_state;
1009
1010 if ((pData == NULL) || (Size == 0U))
1011 {
1012 status = HAL_ERROR;
1013 }
1014 else
1015 {
1016
1017 __HAL_LOCK(hswpmi);
1018
1019 tmp_state = hswpmi->State;
1020 if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
1021 {
1022
1023 hswpmi->pTxBuffPtr = pData;
1024 hswpmi->TxXferSize = Size;
1025 hswpmi->TxXferCount = Size;
1026 hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
1027
1028
1029 if (tmp_state == HAL_SWPMI_STATE_READY)
1030 {
1031 hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
1032
1033
1034 SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
1035 }
1036 else
1037 {
1038 hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
1039 }
1040
1041
1042 hswpmi->hdmatx->XferCpltCallback = SWPMI_DMATransmitCplt;
1043
1044
1045 hswpmi->hdmatx->XferHalfCpltCallback = SWPMI_DMATxHalfCplt;
1046
1047
1048 hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError;
1049
1050
1051 if (HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK)
1052 {
1053 hswpmi->State = tmp_state;
1054 hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA;
1055 status = HAL_ERROR;
1056
1057
1058 __HAL_UNLOCK(hswpmi);
1059 }
1060 else
1061 {
1062
1063 __HAL_UNLOCK(hswpmi);
1064
1065
1066 __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE);
1067
1068
1069
1070 SET_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
1071 }
1072 }
1073 else
1074 {
1075 status = HAL_BUSY;
1076
1077
1078 __HAL_UNLOCK(hswpmi);
1079 }
1080 }
1081
1082 return status;
1083 }
1084
1085
1086
1087
1088
1089
1090
1091
1092 HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
1093 {
1094 HAL_StatusTypeDef status = HAL_OK;
1095 HAL_SWPMI_StateTypeDef tmp_state;
1096
1097 if ((pData == NULL) || (Size == 0U))
1098 {
1099 status = HAL_ERROR;
1100 }
1101 else
1102 {
1103
1104 __HAL_LOCK(hswpmi);
1105
1106 tmp_state = hswpmi->State;
1107 if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
1108 {
1109
1110 hswpmi->pRxBuffPtr = pData;
1111 hswpmi->RxXferSize = Size;
1112 hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
1113
1114
1115 if (tmp_state == HAL_SWPMI_STATE_READY)
1116 {
1117 hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
1118
1119
1120 SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
1121 }
1122 else
1123 {
1124 hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
1125 }
1126
1127
1128 hswpmi->hdmarx->XferCpltCallback = SWPMI_DMAReceiveCplt;
1129
1130
1131 hswpmi->hdmarx->XferHalfCpltCallback = SWPMI_DMARxHalfCplt;
1132
1133
1134 hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError;
1135
1136
1137 if (HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK)
1138 {
1139 hswpmi->State = tmp_state;
1140 hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA;
1141 status = HAL_ERROR;
1142
1143
1144 __HAL_UNLOCK(hswpmi);
1145 }
1146 else
1147 {
1148
1149 __HAL_UNLOCK(hswpmi);
1150
1151
1152 __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE);
1153
1154
1155
1156 SET_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
1157 }
1158 }
1159 else
1160 {
1161 status = HAL_BUSY;
1162
1163
1164 __HAL_UNLOCK(hswpmi);
1165 }
1166 }
1167
1168 return status;
1169 }
1170
1171
1172
1173
1174
1175
1176 HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi)
1177 {
1178 HAL_StatusTypeDef status = HAL_OK;
1179
1180
1181 __HAL_LOCK(hswpmi);
1182
1183
1184 CLEAR_BIT(hswpmi->Instance->CR, (SWPMI_CR_TXDMA | SWPMI_CR_RXDMA));
1185
1186
1187 if (hswpmi->hdmatx != NULL)
1188 {
1189 if (HAL_DMA_Abort(hswpmi->hdmatx) != HAL_OK)
1190 {
1191 hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
1192 status = HAL_ERROR;
1193 }
1194 }
1195
1196 if (hswpmi->hdmarx != NULL)
1197 {
1198 if (HAL_DMA_Abort(hswpmi->hdmarx) != HAL_OK)
1199 {
1200 hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
1201 status = HAL_ERROR;
1202 }
1203 }
1204
1205
1206 CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
1207
1208 hswpmi->State = HAL_SWPMI_STATE_READY;
1209
1210
1211 __HAL_UNLOCK(hswpmi);
1212
1213 return status;
1214 }
1215
1216
1217
1218
1219
1220
1221
1222
1223 HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi)
1224 {
1225 HAL_StatusTypeDef status = HAL_OK;
1226
1227
1228 __HAL_LOCK(hswpmi);
1229
1230
1231 CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
1232
1233
1234 SET_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
1235
1236
1237 SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
1238
1239
1240 __HAL_UNLOCK(hswpmi);
1241
1242 return status;
1243 }
1244
1245
1246
1247
1248
1249
1250
1251 HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi)
1252 {
1253 HAL_StatusTypeDef status = HAL_OK;
1254
1255
1256 __HAL_LOCK(hswpmi);
1257
1258
1259 CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
1260
1261
1262 CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
1263
1264
1265 SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
1266
1267
1268 __HAL_UNLOCK(hswpmi);
1269
1270 return status;
1271 }
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297 void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi)
1298 {
1299 uint32_t regisr = READ_REG(hswpmi->Instance->ISR);
1300 uint32_t regier = READ_REG(hswpmi->Instance->IER);
1301 uint32_t errcode = HAL_SWPMI_ERROR_NONE;
1302
1303
1304 if (((regisr & SWPMI_FLAG_RXBERF) != 0U) && ((regier & SWPMI_IT_RXBERIE) != 0U))
1305 {
1306
1307 CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXBERIE | SWPMI_IT_RXBFIE);
1308
1309 WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBERF | SWPMI_FLAG_RXBFF);
1310
1311 errcode |= HAL_SWPMI_ERROR_CRC;
1312 }
1313
1314
1315 if (((regisr & SWPMI_FLAG_RXOVRF) != 0U) && ((regier & SWPMI_IT_RXOVRIE) != 0U))
1316 {
1317
1318 CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXOVRIE);
1319
1320 WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXOVRF);
1321
1322 errcode |= HAL_SWPMI_ERROR_OVR;
1323 }
1324
1325
1326 if (((regisr & SWPMI_FLAG_TXUNRF) != 0U) && ((regier & SWPMI_IT_TXUNRIE) != 0U))
1327 {
1328
1329 CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TXUNRIE);
1330
1331 WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXUNRF);
1332
1333 errcode |= HAL_SWPMI_ERROR_UDR;
1334 }
1335
1336
1337 if (errcode != HAL_SWPMI_ERROR_NONE)
1338 {
1339 hswpmi->ErrorCode |= errcode;
1340
1341 if ((errcode & HAL_SWPMI_ERROR_UDR) != 0U)
1342 {
1343
1344 if (HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA))
1345 {
1346
1347 CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
1348
1349
1350 if (hswpmi->hdmatx != NULL)
1351 {
1352
1353
1354 hswpmi->hdmatx->XferAbortCallback = SWPMI_DMAAbortOnError;
1355
1356 if (HAL_DMA_Abort_IT(hswpmi->hdmatx) != HAL_OK)
1357 {
1358
1359 hswpmi->hdmatx->XferAbortCallback(hswpmi->hdmatx);
1360 }
1361 }
1362 else
1363 {
1364
1365 hswpmi->State = HAL_SWPMI_STATE_READY;
1366
1367 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1368 hswpmi->ErrorCallback(hswpmi);
1369 #else
1370 HAL_SWPMI_ErrorCallback(hswpmi);
1371 #endif
1372 }
1373 }
1374 else
1375 {
1376
1377 hswpmi->State = HAL_SWPMI_STATE_READY;
1378
1379 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1380 hswpmi->ErrorCallback(hswpmi);
1381 #else
1382 HAL_SWPMI_ErrorCallback(hswpmi);
1383 #endif
1384 }
1385 }
1386 else
1387 {
1388
1389 if (HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_RXDMA))
1390 {
1391
1392 CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
1393
1394
1395 if (hswpmi->hdmarx != NULL)
1396 {
1397
1398
1399 hswpmi->hdmarx->XferAbortCallback = SWPMI_DMAAbortOnError;
1400
1401 if (HAL_DMA_Abort_IT(hswpmi->hdmarx) != HAL_OK)
1402 {
1403
1404 hswpmi->hdmarx->XferAbortCallback(hswpmi->hdmarx);
1405 }
1406 }
1407 else
1408 {
1409
1410 hswpmi->State = HAL_SWPMI_STATE_READY;
1411
1412 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1413 hswpmi->ErrorCallback(hswpmi);
1414 #else
1415 HAL_SWPMI_ErrorCallback(hswpmi);
1416 #endif
1417 }
1418 }
1419 else
1420 {
1421
1422 hswpmi->State = HAL_SWPMI_STATE_READY;
1423
1424 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1425 hswpmi->ErrorCallback(hswpmi);
1426 #else
1427 HAL_SWPMI_ErrorCallback(hswpmi);
1428 #endif
1429 }
1430 }
1431 }
1432
1433
1434 if (((regisr & SWPMI_FLAG_RXNE) != 0U) && ((regier & SWPMI_IT_RIE) != 0U))
1435 {
1436 SWPMI_Receive_IT(hswpmi);
1437 }
1438
1439
1440 if (((regisr & SWPMI_FLAG_TXE) != 0U) && ((regier & SWPMI_IT_TIE) != 0U))
1441 {
1442 SWPMI_Transmit_IT(hswpmi);
1443 }
1444
1445
1446 if (((regisr & SWPMI_FLAG_TXBEF) != 0U) && ((regier & SWPMI_IT_TXBEIE) != 0U))
1447 {
1448 SWPMI_EndTransmit_IT(hswpmi);
1449 }
1450
1451
1452 if (((regisr & SWPMI_FLAG_RXBFF) != 0U) && ((regier & SWPMI_IT_RXBFIE) != 0U))
1453 {
1454 SWPMI_EndReceive_IT(hswpmi);
1455 }
1456
1457
1458 if (((regisr & SWPMI_FLAG_TCF) != 0U) && ((regier & SWPMI_IT_TCIE) != 0U))
1459 {
1460 SWPMI_EndTransmitReceive_IT(hswpmi);
1461 }
1462 }
1463
1464
1465
1466
1467
1468
1469 __weak void HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi)
1470 {
1471
1472 UNUSED(hswpmi);
1473
1474
1475
1476
1477 }
1478
1479
1480
1481
1482
1483
1484 __weak void HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi)
1485 {
1486
1487 UNUSED(hswpmi);
1488
1489
1490
1491
1492 }
1493
1494
1495
1496
1497
1498
1499 __weak void HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi)
1500 {
1501
1502 UNUSED(hswpmi);
1503
1504
1505
1506
1507 }
1508
1509
1510
1511
1512
1513
1514 __weak void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi)
1515 {
1516
1517 UNUSED(hswpmi);
1518
1519
1520
1521
1522 }
1523
1524
1525
1526
1527
1528
1529 __weak void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi)
1530 {
1531
1532 UNUSED(hswpmi);
1533
1534
1535
1536
1537 }
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564 HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi)
1565 {
1566
1567 return hswpmi->State;
1568 }
1569
1570
1571
1572
1573
1574
1575
1576 uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi)
1577 {
1578 return hswpmi->ErrorCode;
1579 }
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602 static void SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi)
1603 {
1604 HAL_SWPMI_StateTypeDef tmp_state = hswpmi->State;
1605
1606 if ((tmp_state == HAL_SWPMI_STATE_BUSY_TX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX))
1607 {
1608 if (hswpmi->TxXferCount == 0U)
1609 {
1610
1611 CLEAR_BIT(hswpmi->Instance->IER, (SWPMI_IT_TIE | SWPMI_IT_TXUNRIE));
1612 }
1613 else
1614 {
1615 hswpmi->Instance->TDR = (uint32_t) * hswpmi->pTxBuffPtr;
1616 hswpmi->pTxBuffPtr++;
1617 hswpmi->TxXferCount--;
1618 }
1619 }
1620 else
1621 {
1622
1623 }
1624 }
1625
1626
1627
1628
1629
1630
1631 static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi)
1632 {
1633
1634 WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXBEF);
1635
1636 CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
1637
1638
1639 if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
1640 {
1641 hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
1642 }
1643 else
1644 {
1645 hswpmi->State = HAL_SWPMI_STATE_READY;
1646 }
1647
1648 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1649 hswpmi->TxCpltCallback(hswpmi);
1650 #else
1651 HAL_SWPMI_TxCpltCallback(hswpmi);
1652 #endif
1653 }
1654
1655
1656
1657
1658
1659
1660
1661 static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi)
1662 {
1663 HAL_SWPMI_StateTypeDef tmp_state = hswpmi->State;
1664
1665 if ((tmp_state == HAL_SWPMI_STATE_BUSY_RX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX))
1666 {
1667 *hswpmi->pRxBuffPtr = (uint32_t)(hswpmi->Instance->RDR);
1668 hswpmi->pRxBuffPtr++;
1669
1670 --hswpmi->RxXferCount;
1671 if (hswpmi->RxXferCount == 0U)
1672 {
1673
1674 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1675 hswpmi->RxCpltCallback(hswpmi);
1676 #else
1677 HAL_SWPMI_RxCpltCallback(hswpmi);
1678 #endif
1679 }
1680 }
1681 else
1682 {
1683
1684 }
1685 }
1686
1687
1688
1689
1690
1691
1692 static void SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi)
1693 {
1694
1695 WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
1696
1697 CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
1698
1699
1700 if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
1701 {
1702 hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
1703 }
1704 else
1705 {
1706 hswpmi->State = HAL_SWPMI_STATE_READY;
1707 }
1708 }
1709
1710
1711
1712
1713
1714
1715 static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi)
1716 {
1717
1718 WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TCF);
1719
1720 CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TCIE);
1721
1722
1723 if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
1724 {
1725 hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
1726 }
1727 else if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)
1728 {
1729 hswpmi->State = HAL_SWPMI_STATE_READY;
1730 }
1731 else
1732 {
1733
1734 }
1735 }
1736
1737
1738
1739
1740
1741
1742 static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
1743 {
1744 SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1745 uint32_t tickstart;
1746
1747
1748 if (((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
1749 {
1750 hswpmi->TxXferCount = 0U;
1751
1752
1753
1754 CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
1755
1756
1757 tickstart = HAL_GetTick();
1758
1759
1760 if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
1761 {
1762
1763 hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT;
1764
1765 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1766 hswpmi->ErrorCallback(hswpmi);
1767 #else
1768 HAL_SWPMI_ErrorCallback(hswpmi);
1769 #endif
1770 }
1771 else
1772 {
1773
1774
1775 if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
1776 {
1777 hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
1778 }
1779 else
1780 {
1781 hswpmi->State = HAL_SWPMI_STATE_READY;
1782 }
1783
1784 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1785 hswpmi->TxCpltCallback(hswpmi);
1786 #else
1787 HAL_SWPMI_TxCpltCallback(hswpmi);
1788 #endif
1789 }
1790 }
1791
1792 else
1793 {
1794 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1795 hswpmi->TxCpltCallback(hswpmi);
1796 #else
1797 HAL_SWPMI_TxCpltCallback(hswpmi);
1798 #endif
1799 }
1800 }
1801
1802
1803
1804
1805
1806
1807 static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
1808 {
1809 SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1810
1811 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1812 hswpmi->TxHalfCpltCallback(hswpmi);
1813 #else
1814 HAL_SWPMI_TxHalfCpltCallback(hswpmi);
1815 #endif
1816 }
1817
1818
1819
1820
1821
1822
1823
1824 static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
1825 {
1826 SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1827
1828
1829 if (((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
1830 {
1831 hswpmi->RxXferCount = 0U;
1832
1833
1834
1835 CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
1836
1837
1838 if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
1839 {
1840 hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
1841 }
1842 else
1843 {
1844 hswpmi->State = HAL_SWPMI_STATE_READY;
1845 }
1846 }
1847 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1848 hswpmi->RxCpltCallback(hswpmi);
1849 #else
1850 HAL_SWPMI_RxCpltCallback(hswpmi);
1851 #endif
1852 }
1853
1854
1855
1856
1857
1858
1859 static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
1860 {
1861 SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1862
1863 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1864 hswpmi->RxHalfCpltCallback(hswpmi);
1865 #else
1866 HAL_SWPMI_RxHalfCpltCallback(hswpmi);
1867 #endif
1868 }
1869
1870
1871
1872
1873
1874
1875 static void SWPMI_DMAError(DMA_HandleTypeDef *hdma)
1876 {
1877 SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1878
1879
1880 hswpmi->RxXferCount = 0U;
1881 hswpmi->TxXferCount = 0U;
1882 hswpmi->State = HAL_SWPMI_STATE_READY;
1883 hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
1884
1885 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1886 hswpmi->ErrorCallback(hswpmi);
1887 #else
1888 HAL_SWPMI_ErrorCallback(hswpmi);
1889 #endif
1890 }
1891
1892
1893
1894
1895
1896
1897 static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
1898 {
1899 SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1900
1901
1902 hswpmi->RxXferCount = 0U;
1903 hswpmi->TxXferCount = 0U;
1904 hswpmi->State = HAL_SWPMI_STATE_READY;
1905
1906 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
1907 hswpmi->ErrorCallback(hswpmi);
1908 #else
1909 HAL_SWPMI_ErrorCallback(hswpmi);
1910 #endif
1911 }
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921 static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout)
1922 {
1923 HAL_StatusTypeDef status = HAL_OK;
1924
1925
1926 while (!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag)))
1927 {
1928
1929 if ((((HAL_GetTick() - Tickstart) > Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1930 {
1931
1932 hswpmi->State = HAL_SWPMI_STATE_READY;
1933
1934 status = HAL_TIMEOUT;
1935 break;
1936 }
1937 }
1938
1939 return status;
1940 }
1941
1942
1943
1944
1945
1946 #endif
1947
1948
1949
1950
1951
1952
1953
1954
1955