stm32h7/hal/stm32h7xx_hal_spi_ex.c

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_spi_ex.c
0004   * @author  MCD Application Team
0005   * @brief   Extended SPI HAL module driver.
0006   *          This file provides firmware functions to manage the following
0007   *          SPI peripheral extended functionalities :
0008   *           + IO operation functions
0009   *           + Peripheral Control functions
0010   *
0011   ******************************************************************************
0012   * @attention
0013   *
0014   * Copyright (c) 2017 STMicroelectronics.
0015   * All rights reserved.
0016   *
0017   * This software is licensed under terms that can be found in the LICENSE file
0018   * in the root directory of this software component.
0019   * If no LICENSE file comes with this software, it is provided AS-IS.
0020   *
0021   ******************************************************************************
0022   */
0023
0024 /* Includes ------------------------------------------------------------------*/
0025 #include "stm32h7xx_hal.h"
0026
0027 /** @addtogroup STM32H7xx_HAL_Driver
0028   * @{
0029   */
0030
0031 /** @defgroup SPIEx SPIEx
0032   * @ingroup RTEMSBSPsARMSTM32H7
0033   * @brief SPI Extended HAL module driver
0034   * @{
0035   */
0036 #ifdef HAL_SPI_MODULE_ENABLED
0037
0038 /* Private typedef -----------------------------------------------------------*/
0039 /* Private defines -----------------------------------------------------------*/
0040 /* Private macros ------------------------------------------------------------*/
0041 /* Private variables ---------------------------------------------------------*/
0042 /* Private function prototypes -----------------------------------------------*/
0043 /* Exported functions --------------------------------------------------------*/
0044
0045 /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
0046   * @ingroup RTEMSBSPsARMSTM32H7
0047   * @{
0048   */
0049
0050 /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
0051   * @ingroup RTEMSBSPsARMSTM32H7
0052   *  @brief   Data transfers functions
0053   *
0054 @verbatim
0055   ==============================================================================
0056                       ##### IO operation functions #####
0057  ===============================================================================
0058  [..]
0059     This subsection provides a set of extended functions to manage the SPI
0060     data transfers.
0061
0062     (#) SPIEx function:
0063         (++) HAL_SPIEx_FlushRxFifo()
0064         (++) HAL_SPIEx_FlushRxFifo()
0065         (++) HAL_SPIEx_EnableLockConfiguration()
0066         (++) HAL_SPIEx_ConfigureUnderrun()
0067
0068 @endverbatim
0069   * @{
0070   */
0071
0072 /**
0073   * @brief Flush the RX fifo.
0074   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
0075   *               the configuration information for the specified SPI module.
0076   * @retval HAL status
0077   */
0078 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
0079 {
0080   uint8_t  count  = 0;
0081   uint32_t itflag = hspi->Instance->SR;
0082   __IO uint32_t tmpreg;
0083
0084   while (((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_RX_FIFO_0PACKET) || ((itflag & SPI_FLAG_RXWNE) !=  0UL))
0085   {
0086     count += (uint8_t)4UL;
0087     tmpreg = hspi->Instance->RXDR;
0088     UNUSED(tmpreg); /* To avoid GCC warning */
0089
0090     if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
0091     {
0092       if (count > SPI_HIGHEND_FIFO_SIZE)
0093       {
0094         return HAL_TIMEOUT;
0095       }
0096     }
0097     else
0098     {
0099       if (count > SPI_LOWEND_FIFO_SIZE)
0100       {
0101         return HAL_TIMEOUT;
0102       }
0103     }
0104   }
0105   return HAL_OK;
0106 }
0107
0108
0109 /**
0110   * @brief  Enable the Lock for the AF configuration of associated IOs
0111   *         and write protect the Content of Configuration register 2
0112   *         when SPI is enabled
0113   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
0114   *               the configuration information for SPI module.
0115   * @retval None
0116   */
0117 HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi)
0118 {
0119   HAL_StatusTypeDef errorcode = HAL_OK;
0120
0121   /* Process Locked */
0122   __HAL_LOCK(hspi);
0123
0124   if (hspi->State != HAL_SPI_STATE_READY)
0125   {
0126     errorcode = HAL_BUSY;
0127     hspi->State = HAL_SPI_STATE_READY;
0128     /* Process Unlocked */
0129     __HAL_UNLOCK(hspi);
0130     return errorcode;
0131   }
0132
0133   /* Check if the SPI is disabled to edit IOLOCK bit */
0134   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
0135   {
0136     SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
0137   }
0138   else
0139   {
0140     /* Disable SPI peripheral */
0141     __HAL_SPI_DISABLE(hspi);
0142
0143     SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
0144
0145     /* Enable SPI peripheral */
0146     __HAL_SPI_ENABLE(hspi);
0147   }
0148
0149   hspi->State = HAL_SPI_STATE_READY;
0150   /* Process Unlocked */
0151   __HAL_UNLOCK(hspi);
0152   return errorcode;
0153 }
0154
0155 /**
0156   * @brief  Configure the UNDERRUN condition and behavior of slave transmitter.
0157   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
0158   *               the configuration information for SPI module.
0159   * @param  UnderrunDetection : Detection of underrun condition at slave transmitter
0160   *                             This parameter can be a value of @ref SPI_Underrun_Detection.
0161   * @param  UnderrunBehaviour : Behavior of slave transmitter at underrun condition
0162   *                             This parameter can be a value of @ref SPI_Underrun_Behaviour.
0163   * @retval None
0164   */
0165 HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection,
0166                                               uint32_t UnderrunBehaviour)
0167 {
0168   HAL_StatusTypeDef errorcode = HAL_OK;
0169
0170   /* Process Locked */
0171   __HAL_LOCK(hspi);
0172
0173   /* Check State and Insure that Underrun configuration is managed only by Salve */
0174   if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE))
0175   {
0176     errorcode = HAL_BUSY;
0177     hspi->State = HAL_SPI_STATE_READY;
0178     /* Process Unlocked */
0179     __HAL_UNLOCK(hspi);
0180     return errorcode;
0181   }
0182
0183   /* Check the parameters */
0184   assert_param(IS_SPI_UNDERRUN_DETECTION(UnderrunDetection));
0185   assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour));
0186
0187   /* Check if the SPI is disabled to edit CFG1 register */
0188   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
0189   {
0190     /* Configure Underrun fields */
0191     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
0192     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
0193   }
0194   else
0195   {
0196     /* Disable SPI peripheral */
0197     __HAL_SPI_DISABLE(hspi);
0198
0199     /* Configure Underrun fields */
0200     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
0201     MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
0202
0203     /* Enable SPI peripheral */
0204     __HAL_SPI_ENABLE(hspi);
0205   }
0206
0207
0208   hspi->State = HAL_SPI_STATE_READY;
0209   /* Process Unlocked */
0210   __HAL_UNLOCK(hspi);
0211   return errorcode;
0212 }
0213
0214 /**
0215   * @}
0216   */
0217
0218 /**
0219   * @}
0220   */
0221
0222 #endif /* HAL_SPI_MODULE_ENABLED */
0223
0224 /**
0225   * @}
0226   */
0227
0228 /**
0229   * @}
0230   */