File indexing completed on 2025-05-11 08:23:09
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0115 #include "stm32h7xx_hal.h"
0116
0117
0118
0119
0120
0121
0122 #ifdef HAL_SDRAM_MODULE_ENABLED
0123
0124
0125
0126
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0137
0138 static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma);
0139 static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma);
0140 static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma);
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
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0154
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0164
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0166
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0168
0169
0170
0171
0172
0173
0174 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
0175 {
0176
0177 if (hsdram == NULL)
0178 {
0179 return HAL_ERROR;
0180 }
0181
0182 if (hsdram->State == HAL_SDRAM_STATE_RESET)
0183 {
0184
0185 hsdram->Lock = HAL_UNLOCKED;
0186 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
0187 if (hsdram->MspInitCallback == NULL)
0188 {
0189 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
0190 }
0191 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
0192 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
0193 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
0194
0195
0196 hsdram->MspInitCallback(hsdram);
0197 #else
0198
0199 HAL_SDRAM_MspInit(hsdram);
0200 #endif
0201 }
0202
0203
0204 hsdram->State = HAL_SDRAM_STATE_BUSY;
0205
0206
0207 (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
0208
0209
0210 (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
0211
0212
0213 __FMC_ENABLE();
0214
0215 hsdram->State = HAL_SDRAM_STATE_READY;
0216
0217 return HAL_OK;
0218 }
0219
0220
0221
0222
0223
0224
0225
0226 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
0227 {
0228 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
0229 if (hsdram->MspDeInitCallback == NULL)
0230 {
0231 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
0232 }
0233
0234
0235 hsdram->MspDeInitCallback(hsdram);
0236 #else
0237
0238 HAL_SDRAM_MspDeInit(hsdram);
0239 #endif
0240
0241
0242 (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
0243
0244
0245 hsdram->State = HAL_SDRAM_STATE_RESET;
0246
0247
0248 __HAL_UNLOCK(hsdram);
0249
0250 return HAL_OK;
0251 }
0252
0253
0254
0255
0256
0257
0258
0259 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
0260 {
0261
0262 UNUSED(hsdram);
0263
0264
0265
0266
0267 }
0268
0269
0270
0271
0272
0273
0274
0275 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
0276 {
0277
0278 UNUSED(hsdram);
0279
0280
0281
0282
0283 }
0284
0285
0286
0287
0288
0289
0290
0291 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
0292 {
0293
0294 if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
0295 {
0296
0297 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
0298 hsdram->RefreshErrorCallback(hsdram);
0299 #else
0300 HAL_SDRAM_RefreshErrorCallback(hsdram);
0301 #endif
0302
0303
0304 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
0305 }
0306 }
0307
0308
0309
0310
0311
0312
0313
0314 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
0315 {
0316
0317 UNUSED(hsdram);
0318
0319
0320
0321
0322 }
0323
0324
0325
0326
0327
0328
0329
0330 __weak void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma)
0331 {
0332
0333 UNUSED(hmdma);
0334
0335
0336
0337
0338 }
0339
0340
0341
0342
0343
0344
0345 __weak void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma)
0346 {
0347
0348 UNUSED(hmdma);
0349
0350
0351
0352
0353 }
0354
0355
0356
0357
0358
0359
0360
0361
0362
0363
0364
0365
0366
0367
0368
0369
0370
0371
0372
0373
0374
0375
0376
0377
0378
0379
0380
0381
0382
0383 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
0384 uint32_t BufferSize)
0385 {
0386 uint32_t size;
0387 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
0388 uint8_t *pdestbuff = pDstBuffer;
0389 HAL_SDRAM_StateTypeDef state = hsdram->State;
0390
0391
0392 if (state == HAL_SDRAM_STATE_BUSY)
0393 {
0394 return HAL_BUSY;
0395 }
0396 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0397 {
0398
0399 __HAL_LOCK(hsdram);
0400
0401
0402 hsdram->State = HAL_SDRAM_STATE_BUSY;
0403
0404
0405 for (size = BufferSize; size != 0U; size--)
0406 {
0407 *pdestbuff = *(__IO uint8_t *)pSdramAddress;
0408 pdestbuff++;
0409 pSdramAddress++;
0410 }
0411
0412
0413 hsdram->State = state;
0414
0415
0416 __HAL_UNLOCK(hsdram);
0417 }
0418 else
0419 {
0420 return HAL_ERROR;
0421 }
0422
0423 return HAL_OK;
0424 }
0425
0426
0427
0428
0429
0430
0431
0432
0433
0434
0435 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
0436 uint32_t BufferSize)
0437 {
0438 uint32_t size;
0439 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
0440 uint8_t *psrcbuff = pSrcBuffer;
0441
0442
0443 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
0444 {
0445 return HAL_BUSY;
0446 }
0447 else if (hsdram->State == HAL_SDRAM_STATE_READY)
0448 {
0449
0450 __HAL_LOCK(hsdram);
0451
0452
0453 hsdram->State = HAL_SDRAM_STATE_BUSY;
0454
0455
0456 for (size = BufferSize; size != 0U; size--)
0457 {
0458 *(__IO uint8_t *)pSdramAddress = *psrcbuff;
0459 psrcbuff++;
0460 pSdramAddress++;
0461 }
0462
0463
0464 hsdram->State = HAL_SDRAM_STATE_READY;
0465
0466
0467 __HAL_UNLOCK(hsdram);
0468 }
0469 else
0470 {
0471 return HAL_ERROR;
0472 }
0473
0474 return HAL_OK;
0475 }
0476
0477
0478
0479
0480
0481
0482
0483
0484
0485
0486 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
0487 uint32_t BufferSize)
0488 {
0489 uint32_t size;
0490 __IO uint32_t *pSdramAddress = pAddress;
0491 uint16_t *pdestbuff = pDstBuffer;
0492 HAL_SDRAM_StateTypeDef state = hsdram->State;
0493
0494
0495 if (state == HAL_SDRAM_STATE_BUSY)
0496 {
0497 return HAL_BUSY;
0498 }
0499 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0500 {
0501
0502 __HAL_LOCK(hsdram);
0503
0504
0505 hsdram->State = HAL_SDRAM_STATE_BUSY;
0506
0507
0508 for (size = BufferSize; size >= 2U ; size -= 2U)
0509 {
0510 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
0511 pdestbuff++;
0512 *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
0513 pdestbuff++;
0514 pSdramAddress++;
0515 }
0516
0517
0518 if ((BufferSize % 2U) != 0U)
0519 {
0520 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
0521 }
0522
0523
0524 hsdram->State = state;
0525
0526
0527 __HAL_UNLOCK(hsdram);
0528 }
0529 else
0530 {
0531 return HAL_ERROR;
0532 }
0533
0534 return HAL_OK;
0535 }
0536
0537
0538
0539
0540
0541
0542
0543
0544
0545
0546 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
0547 uint32_t BufferSize)
0548 {
0549 uint32_t size;
0550 __IO uint32_t *psdramaddress = pAddress;
0551 uint16_t *psrcbuff = pSrcBuffer;
0552
0553
0554 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
0555 {
0556 return HAL_BUSY;
0557 }
0558 else if (hsdram->State == HAL_SDRAM_STATE_READY)
0559 {
0560
0561 __HAL_LOCK(hsdram);
0562
0563
0564 hsdram->State = HAL_SDRAM_STATE_BUSY;
0565
0566
0567 for (size = BufferSize; size >= 2U ; size -= 2U)
0568 {
0569 *psdramaddress = (uint32_t)(*psrcbuff);
0570 psrcbuff++;
0571 *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
0572 psrcbuff++;
0573 psdramaddress++;
0574 }
0575
0576
0577 if ((BufferSize % 2U) != 0U)
0578 {
0579 *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
0580 }
0581
0582
0583 hsdram->State = HAL_SDRAM_STATE_READY;
0584
0585
0586 __HAL_UNLOCK(hsdram);
0587 }
0588 else
0589 {
0590 return HAL_ERROR;
0591 }
0592
0593 return HAL_OK;
0594 }
0595
0596
0597
0598
0599
0600
0601
0602
0603
0604
0605 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
0606 uint32_t BufferSize)
0607 {
0608 uint32_t size;
0609 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
0610 uint32_t *pdestbuff = pDstBuffer;
0611 HAL_SDRAM_StateTypeDef state = hsdram->State;
0612
0613
0614 if (state == HAL_SDRAM_STATE_BUSY)
0615 {
0616 return HAL_BUSY;
0617 }
0618 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0619 {
0620
0621 __HAL_LOCK(hsdram);
0622
0623
0624 hsdram->State = HAL_SDRAM_STATE_BUSY;
0625
0626
0627 for (size = BufferSize; size != 0U; size--)
0628 {
0629 *pdestbuff = *(__IO uint32_t *)pSdramAddress;
0630 pdestbuff++;
0631 pSdramAddress++;
0632 }
0633
0634
0635 hsdram->State = state;
0636
0637
0638 __HAL_UNLOCK(hsdram);
0639 }
0640 else
0641 {
0642 return HAL_ERROR;
0643 }
0644
0645 return HAL_OK;
0646 }
0647
0648
0649
0650
0651
0652
0653
0654
0655
0656
0657 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
0658 uint32_t BufferSize)
0659 {
0660 uint32_t size;
0661 __IO uint32_t *pSdramAddress = pAddress;
0662 uint32_t *psrcbuff = pSrcBuffer;
0663
0664
0665 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
0666 {
0667 return HAL_BUSY;
0668 }
0669 else if (hsdram->State == HAL_SDRAM_STATE_READY)
0670 {
0671
0672 __HAL_LOCK(hsdram);
0673
0674
0675 hsdram->State = HAL_SDRAM_STATE_BUSY;
0676
0677
0678 for (size = BufferSize; size != 0U; size--)
0679 {
0680 *pSdramAddress = *psrcbuff;
0681 psrcbuff++;
0682 pSdramAddress++;
0683 }
0684
0685
0686 hsdram->State = HAL_SDRAM_STATE_READY;
0687
0688
0689 __HAL_UNLOCK(hsdram);
0690 }
0691 else
0692 {
0693 return HAL_ERROR;
0694 }
0695
0696 return HAL_OK;
0697 }
0698
0699
0700
0701
0702
0703
0704
0705
0706
0707
0708 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
0709 uint32_t BufferSize)
0710 {
0711 HAL_StatusTypeDef status;
0712 HAL_SDRAM_StateTypeDef state = hsdram->State;
0713
0714
0715 if (state == HAL_SDRAM_STATE_BUSY)
0716 {
0717 status = HAL_BUSY;
0718 }
0719 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0720 {
0721
0722 __HAL_LOCK(hsdram);
0723
0724
0725 hsdram->State = HAL_SDRAM_STATE_BUSY;
0726
0727
0728 if (state == HAL_SDRAM_STATE_READY)
0729 {
0730 hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt;
0731 }
0732 else
0733 {
0734 hsdram->hmdma->XferCpltCallback = SDRAM_DMACpltProt;
0735 }
0736 hsdram->hmdma->XferErrorCallback = SDRAM_DMAError;
0737
0738
0739 status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1);
0740
0741
0742 __HAL_UNLOCK(hsdram);
0743 }
0744 else
0745 {
0746 status = HAL_ERROR;
0747 }
0748
0749 return status;
0750 }
0751
0752
0753
0754
0755
0756
0757
0758
0759
0760
0761 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
0762 uint32_t BufferSize)
0763 {
0764 HAL_StatusTypeDef status;
0765
0766
0767 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
0768 {
0769 status = HAL_BUSY;
0770 }
0771 else if (hsdram->State == HAL_SDRAM_STATE_READY)
0772 {
0773
0774 __HAL_LOCK(hsdram);
0775
0776
0777 hsdram->State = HAL_SDRAM_STATE_BUSY;
0778
0779
0780 hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt;
0781 hsdram->hmdma->XferErrorCallback = SDRAM_DMAError;
0782
0783
0784 status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1);
0785
0786
0787 __HAL_UNLOCK(hsdram);
0788 }
0789 else
0790 {
0791 status = HAL_ERROR;
0792 }
0793
0794 return status;
0795 }
0796
0797 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
0798
0799
0800
0801
0802
0803
0804
0805
0806
0807
0808
0809
0810 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
0811 pSDRAM_CallbackTypeDef pCallback)
0812 {
0813 HAL_StatusTypeDef status = HAL_OK;
0814 HAL_SDRAM_StateTypeDef state;
0815
0816 if (pCallback == NULL)
0817 {
0818 return HAL_ERROR;
0819 }
0820
0821 state = hsdram->State;
0822 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0823 {
0824 switch (CallbackId)
0825 {
0826 case HAL_SDRAM_MSP_INIT_CB_ID :
0827 hsdram->MspInitCallback = pCallback;
0828 break;
0829 case HAL_SDRAM_MSP_DEINIT_CB_ID :
0830 hsdram->MspDeInitCallback = pCallback;
0831 break;
0832 case HAL_SDRAM_REFRESH_ERR_CB_ID :
0833 hsdram->RefreshErrorCallback = pCallback;
0834 break;
0835 default :
0836
0837 status = HAL_ERROR;
0838 break;
0839 }
0840 }
0841 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
0842 {
0843 switch (CallbackId)
0844 {
0845 case HAL_SDRAM_MSP_INIT_CB_ID :
0846 hsdram->MspInitCallback = pCallback;
0847 break;
0848 case HAL_SDRAM_MSP_DEINIT_CB_ID :
0849 hsdram->MspDeInitCallback = pCallback;
0850 break;
0851 default :
0852
0853 status = HAL_ERROR;
0854 break;
0855 }
0856 }
0857 else
0858 {
0859
0860 status = HAL_ERROR;
0861 }
0862
0863 return status;
0864 }
0865
0866
0867
0868
0869
0870
0871
0872
0873
0874
0875
0876
0877
0878
0879 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
0880 {
0881 HAL_StatusTypeDef status = HAL_OK;
0882 HAL_SDRAM_StateTypeDef state;
0883
0884 state = hsdram->State;
0885 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0886 {
0887 switch (CallbackId)
0888 {
0889 case HAL_SDRAM_MSP_INIT_CB_ID :
0890 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
0891 break;
0892 case HAL_SDRAM_MSP_DEINIT_CB_ID :
0893 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
0894 break;
0895 case HAL_SDRAM_REFRESH_ERR_CB_ID :
0896 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
0897 break;
0898 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
0899 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
0900 break;
0901 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
0902 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
0903 break;
0904 default :
0905
0906 status = HAL_ERROR;
0907 break;
0908 }
0909 }
0910 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
0911 {
0912 switch (CallbackId)
0913 {
0914 case HAL_SDRAM_MSP_INIT_CB_ID :
0915 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
0916 break;
0917 case HAL_SDRAM_MSP_DEINIT_CB_ID :
0918 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
0919 break;
0920 default :
0921
0922 status = HAL_ERROR;
0923 break;
0924 }
0925 }
0926 else
0927 {
0928
0929 status = HAL_ERROR;
0930 }
0931
0932 return status;
0933 }
0934
0935
0936
0937
0938
0939
0940
0941
0942
0943
0944
0945
0946 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
0947 pSDRAM_DmaCallbackTypeDef pCallback)
0948 {
0949 HAL_StatusTypeDef status = HAL_OK;
0950 HAL_SDRAM_StateTypeDef state;
0951
0952 if (pCallback == NULL)
0953 {
0954 return HAL_ERROR;
0955 }
0956
0957
0958 __HAL_LOCK(hsdram);
0959
0960 state = hsdram->State;
0961 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0962 {
0963 switch (CallbackId)
0964 {
0965 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
0966 hsdram->DmaXferCpltCallback = pCallback;
0967 break;
0968 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
0969 hsdram->DmaXferErrorCallback = pCallback;
0970 break;
0971 default :
0972
0973 status = HAL_ERROR;
0974 break;
0975 }
0976 }
0977 else
0978 {
0979
0980 status = HAL_ERROR;
0981 }
0982
0983
0984 __HAL_UNLOCK(hsdram);
0985 return status;
0986 }
0987 #endif
0988
0989
0990
0991
0992
0993
0994
0995
0996
0997
0998
0999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
1016 {
1017
1018 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1019 {
1020 return HAL_BUSY;
1021 }
1022 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1023 {
1024
1025 hsdram->State = HAL_SDRAM_STATE_BUSY;
1026
1027
1028 (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
1029
1030
1031 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1032 }
1033 else
1034 {
1035 return HAL_ERROR;
1036 }
1037
1038 return HAL_OK;
1039 }
1040
1041
1042
1043
1044
1045
1046
1047 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
1048 {
1049 HAL_SDRAM_StateTypeDef state = hsdram->State;
1050
1051
1052 if (state == HAL_SDRAM_STATE_BUSY)
1053 {
1054 return HAL_BUSY;
1055 }
1056 else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
1057 {
1058
1059 hsdram->State = HAL_SDRAM_STATE_BUSY;
1060
1061
1062 (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
1063
1064
1065 hsdram->State = HAL_SDRAM_STATE_READY;
1066 }
1067 else
1068 {
1069 return HAL_ERROR;
1070 }
1071
1072 return HAL_OK;
1073 }
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
1084 uint32_t Timeout)
1085 {
1086 HAL_SDRAM_StateTypeDef state = hsdram->State;
1087
1088
1089 if (state == HAL_SDRAM_STATE_BUSY)
1090 {
1091 return HAL_BUSY;
1092 }
1093 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
1094 {
1095
1096 hsdram->State = HAL_SDRAM_STATE_BUSY;
1097
1098
1099 (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
1100
1101
1102 if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
1103 {
1104 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
1105 }
1106 else
1107 {
1108 hsdram->State = HAL_SDRAM_STATE_READY;
1109 }
1110 }
1111 else
1112 {
1113 return HAL_ERROR;
1114 }
1115
1116 return HAL_OK;
1117 }
1118
1119
1120
1121
1122
1123
1124
1125
1126 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
1127 {
1128
1129 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1130 {
1131 return HAL_BUSY;
1132 }
1133 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1134 {
1135
1136 hsdram->State = HAL_SDRAM_STATE_BUSY;
1137
1138
1139 (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
1140
1141
1142 hsdram->State = HAL_SDRAM_STATE_READY;
1143 }
1144 else
1145 {
1146 return HAL_ERROR;
1147 }
1148
1149 return HAL_OK;
1150 }
1151
1152
1153
1154
1155
1156
1157
1158
1159 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
1160 {
1161
1162 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1163 {
1164 return HAL_BUSY;
1165 }
1166 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1167 {
1168
1169 hsdram->State = HAL_SDRAM_STATE_BUSY;
1170
1171
1172 (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
1173
1174
1175 hsdram->State = HAL_SDRAM_STATE_READY;
1176 }
1177 else
1178 {
1179 return HAL_ERROR;
1180 }
1181
1182 return HAL_OK;
1183 }
1184
1185
1186
1187
1188
1189
1190
1191 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
1192 {
1193
1194 return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
1195 }
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
1224 {
1225 return hsdram->State;
1226 }
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244 static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma)
1245 {
1246 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent);
1247
1248
1249 __HAL_MDMA_DISABLE(hmdma);
1250
1251
1252 hsdram->State = HAL_SDRAM_STATE_READY;
1253
1254 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1255 hsdram->DmaXferCpltCallback(hmdma);
1256 #else
1257 HAL_SDRAM_DMA_XferCpltCallback(hmdma);
1258 #endif
1259 }
1260
1261
1262
1263
1264
1265
1266 static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma)
1267 {
1268 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent);
1269
1270
1271 __HAL_MDMA_DISABLE(hmdma);
1272
1273
1274 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1275
1276 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1277 hsdram->DmaXferCpltCallback(hmdma);
1278 #else
1279 HAL_SDRAM_DMA_XferCpltCallback(hmdma);
1280 #endif
1281 }
1282
1283
1284
1285
1286
1287
1288 static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma)
1289 {
1290 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent);
1291
1292
1293 __HAL_MDMA_DISABLE(hmdma);
1294
1295
1296 hsdram->State = HAL_SDRAM_STATE_ERROR;
1297
1298 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1299 hsdram->DmaXferErrorCallback(hmdma);
1300 #else
1301 HAL_SDRAM_DMA_XferErrorCallback(hmdma);
1302 #endif
1303 }
1304
1305
1306
1307
1308
1309
1310
1311
1312 #endif
1313
1314
1315
1316
1317