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File indexing completed on 2025-05-11 08:23:09

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_sdram.c
0004   * @author  MCD Application Team
0005   * @brief   SDRAM HAL module driver.
0006   *          This file provides a generic firmware to drive SDRAM memories mounted
0007   *          as external device.
0008   *
0009   ******************************************************************************
0010   * @attention
0011   *
0012   * Copyright (c) 2017 STMicroelectronics.
0013   * All rights reserved.
0014   *
0015   * This software is licensed under terms that can be found in the LICENSE file
0016   * in the root directory of this software component.
0017   * If no LICENSE file comes with this software, it is provided AS-IS.
0018   *
0019   ******************************************************************************
0020   @verbatim
0021   ==============================================================================
0022                        ##### How to use this driver #####
0023   ==============================================================================
0024   [..]
0025     This driver is a generic layered driver which contains a set of APIs used to
0026     control SDRAM memories. It uses the FMC layer functions to interface
0027     with SDRAM devices.
0028     The following sequence should be followed to configure the FMC to interface
0029     with SDRAM memories:
0030 
0031    (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
0032           SDRAM_HandleTypeDef  hsdram
0033 
0034        (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
0035             values of the structure member.
0036 
0037        (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
0038             base register instance for NOR or SDRAM device
0039 
0040    (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
0041           FMC_SDRAM_TimingTypeDef  Timing;
0042       and fill its fields with the allowed values of the structure member.
0043 
0044    (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
0045        performs the following sequence:
0046 
0047        (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
0048        (##) Control register configuration using the FMC SDRAM interface function
0049             FMC_SDRAM_Init()
0050        (##) Timing register configuration using the FMC SDRAM interface function
0051             FMC_SDRAM_Timing_Init()
0052        (##) Program the SDRAM external device by applying its initialization sequence
0053             according to the device plugged in your hardware. This step is mandatory
0054             for accessing the SDRAM device.
0055 
0056    (#) At this stage you can perform read/write accesses from/to the memory connected
0057        to the SDRAM Bank. You can perform either polling or DMA transfer using the
0058        following APIs:
0059        (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
0060        (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
0061 
0062    (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
0063        HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
0064        the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
0065        device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
0066        structure.
0067 
0068    (#) You can continuously monitor the SDRAM device HAL state by calling the function
0069        HAL_SDRAM_GetState()
0070 
0071    *** Callback registration ***
0072     =============================================
0073     [..]
0074       The compilation define  USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
0075       allows the user to configure dynamically the driver callbacks.
0076 
0077       Use Functions HAL_SDRAM_RegisterCallback() to register a user callback,
0078       it allows to register following callbacks:
0079         (+) MspInitCallback    : SDRAM MspInit.
0080         (+) MspDeInitCallback  : SDRAM MspDeInit.
0081       This function takes as parameters the HAL peripheral handle, the Callback ID
0082       and a pointer to the user callback function.
0083 
0084       Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
0085       weak (overridden) function. It allows to reset following callbacks:
0086         (+) MspInitCallback    : SDRAM MspInit.
0087         (+) MspDeInitCallback  : SDRAM MspDeInit.
0088       This function) takes as parameters the HAL peripheral handle and the Callback ID.
0089 
0090       By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
0091       all callbacks are reset to the corresponding legacy weak (overridden) functions.
0092       Exception done for MspInit and MspDeInit callbacks that are respectively
0093       reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init
0094       and  HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
0095       If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
0096       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
0097 
0098       Callbacks can be registered/unregistered in READY state only.
0099       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
0100       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
0101       during the Init/DeInit.
0102       In that case first register the MspInit/MspDeInit user callbacks
0103       using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit
0104       or HAL_SDRAM_Init function.
0105 
0106       When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
0107       not defined, the callback registering feature is not available
0108       and weak (overridden) callbacks are used.
0109 
0110   @endverbatim
0111   ******************************************************************************
0112   */
0113 
0114 /* Includes ------------------------------------------------------------------*/
0115 #include "stm32h7xx_hal.h"
0116 
0117 
0118 /** @addtogroup STM32H7xx_HAL_Driver
0119   * @{
0120   */
0121 
0122 #ifdef HAL_SDRAM_MODULE_ENABLED
0123 
0124 /** @defgroup SDRAM SDRAM
0125   * @ingroup RTEMSBSPsARMSTM32H7
0126   * @brief SDRAM driver modules
0127   * @{
0128   */
0129 
0130 /* Private typedef -----------------------------------------------------------*/
0131 /* Private define ------------------------------------------------------------*/
0132 /* Private macro -------------------------------------------------------------*/
0133 /* Private variables ---------------------------------------------------------*/
0134 /* Private function prototypes -----------------------------------------------*/
0135 /** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
0136   * @{
0137   */
0138 static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma);
0139 static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma);
0140 static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma);
0141 /**
0142   * @}
0143   */
0144 
0145 /* Exported functions --------------------------------------------------------*/
0146 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
0147   * @ingroup RTEMSBSPsARMSTM32H7
0148   * @{
0149   */
0150 
0151 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
0152   * @ingroup RTEMSBSPsARMSTM32H7
0153   * @brief    Initialization and Configuration functions
0154   *
0155   @verbatim
0156   ==============================================================================
0157            ##### SDRAM Initialization and de_initialization functions #####
0158   ==============================================================================
0159   [..]
0160     This section provides functions allowing to initialize/de-initialize
0161     the SDRAM memory
0162 
0163 @endverbatim
0164   * @{
0165   */
0166 
0167 /**
0168   * @brief  Performs the SDRAM device initialization sequence.
0169   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0170   *                the configuration information for SDRAM module.
0171   * @param  Timing Pointer to SDRAM control timing structure
0172   * @retval HAL status
0173   */
0174 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
0175 {
0176   /* Check the SDRAM handle parameter */
0177   if (hsdram == NULL)
0178   {
0179     return HAL_ERROR;
0180   }
0181 
0182   if (hsdram->State == HAL_SDRAM_STATE_RESET)
0183   {
0184     /* Allocate lock resource and initialize it */
0185     hsdram->Lock = HAL_UNLOCKED;
0186 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
0187     if (hsdram->MspInitCallback == NULL)
0188     {
0189       hsdram->MspInitCallback = HAL_SDRAM_MspInit;
0190     }
0191     hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
0192     hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
0193     hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
0194 
0195     /* Init the low level hardware */
0196     hsdram->MspInitCallback(hsdram);
0197 #else
0198     /* Initialize the low level hardware (MSP) */
0199     HAL_SDRAM_MspInit(hsdram);
0200 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
0201   }
0202 
0203   /* Initialize the SDRAM controller state */
0204   hsdram->State = HAL_SDRAM_STATE_BUSY;
0205 
0206   /* Initialize SDRAM control Interface */
0207   (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
0208 
0209   /* Initialize SDRAM timing Interface */
0210   (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
0211 
0212   /* Enable FMC Peripheral */
0213   __FMC_ENABLE();
0214   /* Update the SDRAM controller state */
0215   hsdram->State = HAL_SDRAM_STATE_READY;
0216 
0217   return HAL_OK;
0218 }
0219 
0220 /**
0221   * @brief  Perform the SDRAM device initialization sequence.
0222   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0223   *                the configuration information for SDRAM module.
0224   * @retval HAL status
0225   */
0226 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
0227 {
0228 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
0229   if (hsdram->MspDeInitCallback == NULL)
0230   {
0231     hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
0232   }
0233 
0234   /* DeInit the low level hardware */
0235   hsdram->MspDeInitCallback(hsdram);
0236 #else
0237   /* Initialize the low level hardware (MSP) */
0238   HAL_SDRAM_MspDeInit(hsdram);
0239 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
0240 
0241   /* Configure the SDRAM registers with their reset values */
0242   (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
0243 
0244   /* Reset the SDRAM controller state */
0245   hsdram->State = HAL_SDRAM_STATE_RESET;
0246 
0247   /* Release Lock */
0248   __HAL_UNLOCK(hsdram);
0249 
0250   return HAL_OK;
0251 }
0252 
0253 /**
0254   * @brief  SDRAM MSP Init.
0255   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0256   *                the configuration information for SDRAM module.
0257   * @retval None
0258   */
0259 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
0260 {
0261   /* Prevent unused argument(s) compilation warning */
0262   UNUSED(hsdram);
0263 
0264   /* NOTE: This function Should not be modified, when the callback is needed,
0265             the HAL_SDRAM_MspInit could be implemented in the user file
0266    */
0267 }
0268 
0269 /**
0270   * @brief  SDRAM MSP DeInit.
0271   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0272   *                the configuration information for SDRAM module.
0273   * @retval None
0274   */
0275 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
0276 {
0277   /* Prevent unused argument(s) compilation warning */
0278   UNUSED(hsdram);
0279 
0280   /* NOTE: This function Should not be modified, when the callback is needed,
0281             the HAL_SDRAM_MspDeInit could be implemented in the user file
0282    */
0283 }
0284 
0285 /**
0286   * @brief  This function handles SDRAM refresh error interrupt request.
0287   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0288   *                the configuration information for SDRAM module.
0289   * @retval HAL status
0290   */
0291 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
0292 {
0293   /* Check SDRAM interrupt Rising edge flag */
0294   if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
0295   {
0296     /* SDRAM refresh error interrupt callback */
0297 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
0298     hsdram->RefreshErrorCallback(hsdram);
0299 #else
0300     HAL_SDRAM_RefreshErrorCallback(hsdram);
0301 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
0302 
0303     /* Clear SDRAM refresh error interrupt pending bit */
0304     __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
0305   }
0306 }
0307 
0308 /**
0309   * @brief  SDRAM Refresh error callback.
0310   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0311   *                the configuration information for SDRAM module.
0312   * @retval None
0313   */
0314 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
0315 {
0316   /* Prevent unused argument(s) compilation warning */
0317   UNUSED(hsdram);
0318 
0319   /* NOTE: This function Should not be modified, when the callback is needed,
0320             the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
0321    */
0322 }
0323 
0324 /**
0325   * @brief  DMA transfer complete callback.
0326   * @param  hmdma pointer to a DMA_HandleTypeDef structure that contains
0327   *                the configuration information for the specified DMA module.
0328   * @retval None
0329   */
0330 __weak void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma)
0331 {
0332   /* Prevent unused argument(s) compilation warning */
0333   UNUSED(hmdma);
0334 
0335   /* NOTE: This function Should not be modified, when the callback is needed,
0336             the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
0337    */
0338 }
0339 
0340 /**
0341   * @brief  DMA transfer complete error callback.
0342   * @param  hmdma DMA handle
0343   * @retval None
0344   */
0345 __weak void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma)
0346 {
0347   /* Prevent unused argument(s) compilation warning */
0348   UNUSED(hmdma);
0349 
0350   /* NOTE: This function Should not be modified, when the callback is needed,
0351             the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
0352    */
0353 }
0354 
0355 /**
0356   * @}
0357   */
0358 
0359 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
0360   * @ingroup RTEMSBSPsARMSTM32H7
0361   * @brief    Input Output and memory control functions
0362   *
0363   @verbatim
0364   ==============================================================================
0365                     ##### SDRAM Input and Output functions #####
0366   ==============================================================================
0367   [..]
0368     This section provides functions allowing to use and control the SDRAM memory
0369 
0370 @endverbatim
0371   * @{
0372   */
0373 
0374 /**
0375   * @brief  Reads 8-bit data buffer from the SDRAM memory.
0376   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0377   *                the configuration information for SDRAM module.
0378   * @param  pAddress Pointer to read start address
0379   * @param  pDstBuffer Pointer to destination buffer
0380   * @param  BufferSize Size of the buffer to read from memory
0381   * @retval HAL status
0382   */
0383 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
0384                                     uint32_t BufferSize)
0385 {
0386   uint32_t size;
0387   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
0388   uint8_t *pdestbuff = pDstBuffer;
0389   HAL_SDRAM_StateTypeDef state = hsdram->State;
0390 
0391   /* Check the SDRAM controller state */
0392   if (state == HAL_SDRAM_STATE_BUSY)
0393   {
0394     return HAL_BUSY;
0395   }
0396   else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0397   {
0398     /* Process Locked */
0399     __HAL_LOCK(hsdram);
0400 
0401     /* Update the SDRAM controller state */
0402     hsdram->State = HAL_SDRAM_STATE_BUSY;
0403 
0404     /* Read data from source */
0405     for (size = BufferSize; size != 0U; size--)
0406     {
0407       *pdestbuff = *(__IO uint8_t *)pSdramAddress;
0408       pdestbuff++;
0409       pSdramAddress++;
0410     }
0411 
0412     /* Update the SDRAM controller state */
0413     hsdram->State = state;
0414 
0415     /* Process Unlocked */
0416     __HAL_UNLOCK(hsdram);
0417   }
0418   else
0419   {
0420     return  HAL_ERROR;
0421   }
0422 
0423   return HAL_OK;
0424 }
0425 
0426 /**
0427   * @brief  Writes 8-bit data buffer to SDRAM memory.
0428   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0429   *                the configuration information for SDRAM module.
0430   * @param  pAddress Pointer to write start address
0431   * @param  pSrcBuffer Pointer to source buffer to write
0432   * @param  BufferSize Size of the buffer to write to memory
0433   * @retval HAL status
0434   */
0435 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
0436                                      uint32_t BufferSize)
0437 {
0438   uint32_t size;
0439   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
0440   uint8_t *psrcbuff = pSrcBuffer;
0441 
0442   /* Check the SDRAM controller state */
0443   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
0444   {
0445     return HAL_BUSY;
0446   }
0447   else if (hsdram->State == HAL_SDRAM_STATE_READY)
0448   {
0449     /* Process Locked */
0450     __HAL_LOCK(hsdram);
0451 
0452     /* Update the SDRAM controller state */
0453     hsdram->State = HAL_SDRAM_STATE_BUSY;
0454 
0455     /* Write data to memory */
0456     for (size = BufferSize; size != 0U; size--)
0457     {
0458       *(__IO uint8_t *)pSdramAddress = *psrcbuff;
0459       psrcbuff++;
0460       pSdramAddress++;
0461     }
0462 
0463     /* Update the SDRAM controller state */
0464     hsdram->State = HAL_SDRAM_STATE_READY;
0465 
0466     /* Process Unlocked */
0467     __HAL_UNLOCK(hsdram);
0468   }
0469   else
0470   {
0471     return  HAL_ERROR;
0472   }
0473 
0474   return HAL_OK;
0475 }
0476 
0477 /**
0478   * @brief  Reads 16-bit data buffer from the SDRAM memory.
0479   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0480   *                the configuration information for SDRAM module.
0481   * @param  pAddress Pointer to read start address
0482   * @param  pDstBuffer Pointer to destination buffer
0483   * @param  BufferSize Size of the buffer to read from memory
0484   * @retval HAL status
0485   */
0486 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
0487                                      uint32_t BufferSize)
0488 {
0489   uint32_t size;
0490   __IO uint32_t *pSdramAddress = pAddress;
0491   uint16_t *pdestbuff = pDstBuffer;
0492   HAL_SDRAM_StateTypeDef state = hsdram->State;
0493 
0494   /* Check the SDRAM controller state */
0495   if (state == HAL_SDRAM_STATE_BUSY)
0496   {
0497     return HAL_BUSY;
0498   }
0499   else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0500   {
0501     /* Process Locked */
0502     __HAL_LOCK(hsdram);
0503 
0504     /* Update the SDRAM controller state */
0505     hsdram->State = HAL_SDRAM_STATE_BUSY;
0506 
0507     /* Read data from memory */
0508     for (size = BufferSize; size >= 2U ; size -= 2U)
0509     {
0510       *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
0511       pdestbuff++;
0512       *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
0513       pdestbuff++;
0514       pSdramAddress++;
0515     }
0516 
0517     /* Read last 16-bits if size is not 32-bits multiple */
0518     if ((BufferSize % 2U) != 0U)
0519     {
0520       *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
0521     }
0522 
0523     /* Update the SDRAM controller state */
0524     hsdram->State = state;
0525 
0526     /* Process Unlocked */
0527     __HAL_UNLOCK(hsdram);
0528   }
0529   else
0530   {
0531     return  HAL_ERROR;
0532   }
0533 
0534   return HAL_OK;
0535 }
0536 
0537 /**
0538   * @brief  Writes 16-bit data buffer to SDRAM memory.
0539   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0540   *                the configuration information for SDRAM module.
0541   * @param  pAddress Pointer to write start address
0542   * @param  pSrcBuffer Pointer to source buffer to write
0543   * @param  BufferSize Size of the buffer to write to memory
0544   * @retval HAL status
0545   */
0546 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
0547                                       uint32_t BufferSize)
0548 {
0549   uint32_t size;
0550   __IO uint32_t *psdramaddress = pAddress;
0551   uint16_t *psrcbuff = pSrcBuffer;
0552 
0553   /* Check the SDRAM controller state */
0554   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
0555   {
0556     return HAL_BUSY;
0557   }
0558   else if (hsdram->State == HAL_SDRAM_STATE_READY)
0559   {
0560     /* Process Locked */
0561     __HAL_LOCK(hsdram);
0562 
0563     /* Update the SDRAM controller state */
0564     hsdram->State = HAL_SDRAM_STATE_BUSY;
0565 
0566     /* Write data to memory */
0567     for (size = BufferSize; size >= 2U ; size -= 2U)
0568     {
0569       *psdramaddress = (uint32_t)(*psrcbuff);
0570       psrcbuff++;
0571       *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
0572       psrcbuff++;
0573       psdramaddress++;
0574     }
0575 
0576     /* Write last 16-bits if size is not 32-bits multiple */
0577     if ((BufferSize % 2U) != 0U)
0578     {
0579       *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
0580     }
0581 
0582     /* Update the SDRAM controller state */
0583     hsdram->State = HAL_SDRAM_STATE_READY;
0584 
0585     /* Process Unlocked */
0586     __HAL_UNLOCK(hsdram);
0587   }
0588   else
0589   {
0590     return  HAL_ERROR;
0591   }
0592 
0593   return HAL_OK;
0594 }
0595 
0596 /**
0597   * @brief  Reads 32-bit data buffer from the SDRAM memory.
0598   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0599   *                the configuration information for SDRAM module.
0600   * @param  pAddress Pointer to read start address
0601   * @param  pDstBuffer Pointer to destination buffer
0602   * @param  BufferSize Size of the buffer to read from memory
0603   * @retval HAL status
0604   */
0605 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
0606                                      uint32_t BufferSize)
0607 {
0608   uint32_t size;
0609   __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
0610   uint32_t *pdestbuff = pDstBuffer;
0611   HAL_SDRAM_StateTypeDef state = hsdram->State;
0612 
0613   /* Check the SDRAM controller state */
0614   if (state == HAL_SDRAM_STATE_BUSY)
0615   {
0616     return HAL_BUSY;
0617   }
0618   else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0619   {
0620     /* Process Locked */
0621     __HAL_LOCK(hsdram);
0622 
0623     /* Update the SDRAM controller state */
0624     hsdram->State = HAL_SDRAM_STATE_BUSY;
0625 
0626     /* Read data from source */
0627     for (size = BufferSize; size != 0U; size--)
0628     {
0629       *pdestbuff = *(__IO uint32_t *)pSdramAddress;
0630       pdestbuff++;
0631       pSdramAddress++;
0632     }
0633 
0634     /* Update the SDRAM controller state */
0635     hsdram->State = state;
0636 
0637     /* Process Unlocked */
0638     __HAL_UNLOCK(hsdram);
0639   }
0640   else
0641   {
0642     return  HAL_ERROR;
0643   }
0644 
0645   return HAL_OK;
0646 }
0647 
0648 /**
0649   * @brief  Writes 32-bit data buffer to SDRAM memory.
0650   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0651   *                the configuration information for SDRAM module.
0652   * @param  pAddress Pointer to write start address
0653   * @param  pSrcBuffer Pointer to source buffer to write
0654   * @param  BufferSize Size of the buffer to write to memory
0655   * @retval HAL status
0656   */
0657 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
0658                                       uint32_t BufferSize)
0659 {
0660   uint32_t size;
0661   __IO uint32_t *pSdramAddress = pAddress;
0662   uint32_t *psrcbuff = pSrcBuffer;
0663 
0664   /* Check the SDRAM controller state */
0665   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
0666   {
0667     return HAL_BUSY;
0668   }
0669   else if (hsdram->State == HAL_SDRAM_STATE_READY)
0670   {
0671     /* Process Locked */
0672     __HAL_LOCK(hsdram);
0673 
0674     /* Update the SDRAM controller state */
0675     hsdram->State = HAL_SDRAM_STATE_BUSY;
0676 
0677     /* Write data to memory */
0678     for (size = BufferSize; size != 0U; size--)
0679     {
0680       *pSdramAddress = *psrcbuff;
0681       psrcbuff++;
0682       pSdramAddress++;
0683     }
0684 
0685     /* Update the SDRAM controller state */
0686     hsdram->State = HAL_SDRAM_STATE_READY;
0687 
0688     /* Process Unlocked */
0689     __HAL_UNLOCK(hsdram);
0690   }
0691   else
0692   {
0693     return  HAL_ERROR;
0694   }
0695 
0696   return HAL_OK;
0697 }
0698 
0699 /**
0700   * @brief  Reads a Words data from the SDRAM memory using DMA transfer.
0701   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0702   *                the configuration information for SDRAM module.
0703   * @param  pAddress Pointer to read start address
0704   * @param  pDstBuffer Pointer to destination buffer
0705   * @param  BufferSize Size of the buffer to read from memory
0706   * @retval HAL status
0707   */
0708 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
0709                                      uint32_t BufferSize)
0710 {
0711   HAL_StatusTypeDef status;
0712   HAL_SDRAM_StateTypeDef state = hsdram->State;
0713 
0714   /* Check the SDRAM controller state */
0715   if (state == HAL_SDRAM_STATE_BUSY)
0716   {
0717     status = HAL_BUSY;
0718   }
0719   else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0720   {
0721     /* Process Locked */
0722     __HAL_LOCK(hsdram);
0723 
0724     /* Update the SDRAM controller state */
0725     hsdram->State = HAL_SDRAM_STATE_BUSY;
0726 
0727     /* Configure DMA user callbacks */
0728     if (state == HAL_SDRAM_STATE_READY)
0729     {
0730       hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt;
0731     }
0732     else
0733     {
0734       hsdram->hmdma->XferCpltCallback = SDRAM_DMACpltProt;
0735     }
0736     hsdram->hmdma->XferErrorCallback = SDRAM_DMAError;
0737 
0738     /* Enable the DMA Stream */
0739     status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1);
0740 
0741     /* Process Unlocked */
0742     __HAL_UNLOCK(hsdram);
0743   }
0744   else
0745   {
0746     status = HAL_ERROR;
0747   }
0748 
0749   return status;
0750 }
0751 
0752 /**
0753   * @brief  Writes a Words data buffer to SDRAM memory using DMA transfer.
0754   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
0755   *                the configuration information for SDRAM module.
0756   * @param  pAddress Pointer to write start address
0757   * @param  pSrcBuffer Pointer to source buffer to write
0758   * @param  BufferSize Size of the buffer to write to memory
0759   * @retval HAL status
0760   */
0761 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
0762                                       uint32_t BufferSize)
0763 {
0764   HAL_StatusTypeDef status;
0765 
0766   /* Check the SDRAM controller state */
0767   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
0768   {
0769     status = HAL_BUSY;
0770   }
0771   else if (hsdram->State == HAL_SDRAM_STATE_READY)
0772   {
0773     /* Process Locked */
0774     __HAL_LOCK(hsdram);
0775 
0776     /* Update the SDRAM controller state */
0777     hsdram->State = HAL_SDRAM_STATE_BUSY;
0778 
0779     /* Configure DMA user callbacks */
0780     hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt;
0781     hsdram->hmdma->XferErrorCallback = SDRAM_DMAError;
0782 
0783     /* Enable the DMA Stream */
0784     status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1);
0785 
0786     /* Process Unlocked */
0787     __HAL_UNLOCK(hsdram);
0788   }
0789   else
0790   {
0791     status = HAL_ERROR;
0792   }
0793 
0794   return status;
0795 }
0796 
0797 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
0798 /**
0799   * @brief  Register a User SDRAM Callback
0800   *         To be used to override the weak predefined callback
0801   * @param hsdram : SDRAM handle
0802   * @param CallbackId : ID of the callback to be registered
0803   *        This parameter can be one of the following values:
0804   *          @arg @ref HAL_SDRAM_MSP_INIT_CB_ID       SDRAM MspInit callback ID
0805   *          @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID     SDRAM MspDeInit callback ID
0806   *          @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID    SDRAM Refresh Error callback ID
0807   * @param pCallback : pointer to the Callback function
0808   * @retval status
0809   */
0810 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
0811                                              pSDRAM_CallbackTypeDef pCallback)
0812 {
0813   HAL_StatusTypeDef status = HAL_OK;
0814   HAL_SDRAM_StateTypeDef state;
0815 
0816   if (pCallback == NULL)
0817   {
0818     return HAL_ERROR;
0819   }
0820 
0821   state = hsdram->State;
0822   if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0823   {
0824     switch (CallbackId)
0825     {
0826       case HAL_SDRAM_MSP_INIT_CB_ID :
0827         hsdram->MspInitCallback = pCallback;
0828         break;
0829       case HAL_SDRAM_MSP_DEINIT_CB_ID :
0830         hsdram->MspDeInitCallback = pCallback;
0831         break;
0832       case HAL_SDRAM_REFRESH_ERR_CB_ID :
0833         hsdram->RefreshErrorCallback = pCallback;
0834         break;
0835       default :
0836         /* update return status */
0837         status =  HAL_ERROR;
0838         break;
0839     }
0840   }
0841   else if (hsdram->State == HAL_SDRAM_STATE_RESET)
0842   {
0843     switch (CallbackId)
0844     {
0845       case HAL_SDRAM_MSP_INIT_CB_ID :
0846         hsdram->MspInitCallback = pCallback;
0847         break;
0848       case HAL_SDRAM_MSP_DEINIT_CB_ID :
0849         hsdram->MspDeInitCallback = pCallback;
0850         break;
0851       default :
0852         /* update return status */
0853         status =  HAL_ERROR;
0854         break;
0855     }
0856   }
0857   else
0858   {
0859     /* update return status */
0860     status =  HAL_ERROR;
0861   }
0862 
0863   return status;
0864 }
0865 
0866 /**
0867   * @brief  Unregister a User SDRAM Callback
0868   *         SDRAM Callback is redirected to the weak predefined callback
0869   * @param hsdram : SDRAM handle
0870   * @param CallbackId : ID of the callback to be unregistered
0871   *        This parameter can be one of the following values:
0872   *          @arg @ref HAL_SDRAM_MSP_INIT_CB_ID       SDRAM MspInit callback ID
0873   *          @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID     SDRAM MspDeInit callback ID
0874   *          @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID    SDRAM Refresh Error callback ID
0875   *          @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID  SDRAM DMA Xfer Complete callback ID
0876   *          @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID   SDRAM DMA Xfer Error callback ID
0877   * @retval status
0878   */
0879 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
0880 {
0881   HAL_StatusTypeDef status = HAL_OK;
0882   HAL_SDRAM_StateTypeDef state;
0883 
0884   state = hsdram->State;
0885   if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0886   {
0887     switch (CallbackId)
0888     {
0889       case HAL_SDRAM_MSP_INIT_CB_ID :
0890         hsdram->MspInitCallback = HAL_SDRAM_MspInit;
0891         break;
0892       case HAL_SDRAM_MSP_DEINIT_CB_ID :
0893         hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
0894         break;
0895       case HAL_SDRAM_REFRESH_ERR_CB_ID :
0896         hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
0897         break;
0898       case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
0899         hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
0900         break;
0901       case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
0902         hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
0903         break;
0904       default :
0905         /* update return status */
0906         status =  HAL_ERROR;
0907         break;
0908     }
0909   }
0910   else if (hsdram->State == HAL_SDRAM_STATE_RESET)
0911   {
0912     switch (CallbackId)
0913     {
0914       case HAL_SDRAM_MSP_INIT_CB_ID :
0915         hsdram->MspInitCallback = HAL_SDRAM_MspInit;
0916         break;
0917       case HAL_SDRAM_MSP_DEINIT_CB_ID :
0918         hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
0919         break;
0920       default :
0921         /* update return status */
0922         status =  HAL_ERROR;
0923         break;
0924     }
0925   }
0926   else
0927   {
0928     /* update return status */
0929     status =  HAL_ERROR;
0930   }
0931 
0932   return status;
0933 }
0934 
0935 /**
0936   * @brief  Register a User SDRAM Callback for DMA transfers
0937   *         To be used to override the weak predefined callback
0938   * @param hsdram : SDRAM handle
0939   * @param CallbackId : ID of the callback to be registered
0940   *        This parameter can be one of the following values:
0941   *          @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID  SDRAM DMA Xfer Complete callback ID
0942   *          @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID   SDRAM DMA Xfer Error callback ID
0943   * @param pCallback : pointer to the Callback function
0944   * @retval status
0945   */
0946 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
0947                                                 pSDRAM_DmaCallbackTypeDef pCallback)
0948 {
0949   HAL_StatusTypeDef status = HAL_OK;
0950   HAL_SDRAM_StateTypeDef state;
0951 
0952   if (pCallback == NULL)
0953   {
0954     return HAL_ERROR;
0955   }
0956 
0957   /* Process locked */
0958   __HAL_LOCK(hsdram);
0959 
0960   state = hsdram->State;
0961   if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
0962   {
0963     switch (CallbackId)
0964     {
0965       case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
0966         hsdram->DmaXferCpltCallback = pCallback;
0967         break;
0968       case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
0969         hsdram->DmaXferErrorCallback = pCallback;
0970         break;
0971       default :
0972         /* update return status */
0973         status =  HAL_ERROR;
0974         break;
0975     }
0976   }
0977   else
0978   {
0979     /* update return status */
0980     status =  HAL_ERROR;
0981   }
0982 
0983   /* Release Lock */
0984   __HAL_UNLOCK(hsdram);
0985   return status;
0986 }
0987 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
0988 
0989 /**
0990   * @}
0991   */
0992 
0993 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
0994   * @ingroup RTEMSBSPsARMSTM32H7
0995   *  @brief   management functions
0996   *
0997 @verbatim
0998   ==============================================================================
0999                          ##### SDRAM Control functions #####
1000   ==============================================================================
1001   [..]
1002     This subsection provides a set of functions allowing to control dynamically
1003     the SDRAM interface.
1004 
1005 @endverbatim
1006   * @{
1007   */
1008 
1009 /**
1010   * @brief  Enables dynamically SDRAM write protection.
1011   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1012   *                the configuration information for SDRAM module.
1013   * @retval HAL status
1014   */
1015 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
1016 {
1017   /* Check the SDRAM controller state */
1018   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1019   {
1020     return HAL_BUSY;
1021   }
1022   else if (hsdram->State == HAL_SDRAM_STATE_READY)
1023   {
1024     /* Update the SDRAM state */
1025     hsdram->State = HAL_SDRAM_STATE_BUSY;
1026 
1027     /* Enable write protection */
1028     (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
1029 
1030     /* Update the SDRAM state */
1031     hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1032   }
1033   else
1034   {
1035     return HAL_ERROR;
1036   }
1037 
1038   return HAL_OK;
1039 }
1040 
1041 /**
1042   * @brief  Disables dynamically SDRAM write protection.
1043   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1044   *                the configuration information for SDRAM module.
1045   * @retval HAL status
1046   */
1047 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
1048 {
1049   HAL_SDRAM_StateTypeDef state = hsdram->State;
1050 
1051   /* Check the SDRAM controller state */
1052   if (state == HAL_SDRAM_STATE_BUSY)
1053   {
1054     return HAL_BUSY;
1055   }
1056   else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
1057   {
1058     /* Update the SDRAM state */
1059     hsdram->State = HAL_SDRAM_STATE_BUSY;
1060 
1061     /* Disable write protection */
1062     (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
1063 
1064     /* Update the SDRAM state */
1065     hsdram->State = HAL_SDRAM_STATE_READY;
1066   }
1067   else
1068   {
1069     return HAL_ERROR;
1070   }
1071 
1072   return HAL_OK;
1073 }
1074 
1075 /**
1076   * @brief  Sends Command to the SDRAM bank.
1077   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1078   *                the configuration information for SDRAM module.
1079   * @param  Command SDRAM command structure
1080   * @param  Timeout Timeout duration
1081   * @retval HAL status
1082   */
1083 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
1084                                         uint32_t Timeout)
1085 {
1086   HAL_SDRAM_StateTypeDef state = hsdram->State;
1087 
1088   /* Check the SDRAM controller state */
1089   if (state == HAL_SDRAM_STATE_BUSY)
1090   {
1091     return HAL_BUSY;
1092   }
1093   else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
1094   {
1095     /* Update the SDRAM state */
1096     hsdram->State = HAL_SDRAM_STATE_BUSY;
1097 
1098     /* Send SDRAM command */
1099     (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
1100 
1101     /* Update the SDRAM controller state state */
1102     if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
1103     {
1104       hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
1105     }
1106     else
1107     {
1108       hsdram->State = HAL_SDRAM_STATE_READY;
1109     }
1110   }
1111   else
1112   {
1113     return HAL_ERROR;
1114   }
1115 
1116   return HAL_OK;
1117 }
1118 
1119 /**
1120   * @brief  Programs the SDRAM Memory Refresh rate.
1121   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1122   *                the configuration information for SDRAM module.
1123   * @param  RefreshRate The SDRAM refresh rate value
1124   * @retval HAL status
1125   */
1126 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
1127 {
1128   /* Check the SDRAM controller state */
1129   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1130   {
1131     return HAL_BUSY;
1132   }
1133   else if (hsdram->State == HAL_SDRAM_STATE_READY)
1134   {
1135     /* Update the SDRAM state */
1136     hsdram->State = HAL_SDRAM_STATE_BUSY;
1137 
1138     /* Program the refresh rate */
1139     (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
1140 
1141     /* Update the SDRAM state */
1142     hsdram->State = HAL_SDRAM_STATE_READY;
1143   }
1144   else
1145   {
1146     return HAL_ERROR;
1147   }
1148 
1149   return HAL_OK;
1150 }
1151 
1152 /**
1153   * @brief  Sets the Number of consecutive SDRAM Memory auto Refresh commands.
1154   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1155   *                the configuration information for SDRAM module.
1156   * @param  AutoRefreshNumber The SDRAM auto Refresh number
1157   * @retval HAL status
1158   */
1159 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
1160 {
1161   /* Check the SDRAM controller state */
1162   if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1163   {
1164     return HAL_BUSY;
1165   }
1166   else if (hsdram->State == HAL_SDRAM_STATE_READY)
1167   {
1168     /* Update the SDRAM state */
1169     hsdram->State = HAL_SDRAM_STATE_BUSY;
1170 
1171     /* Set the Auto-Refresh number */
1172     (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
1173 
1174     /* Update the SDRAM state */
1175     hsdram->State = HAL_SDRAM_STATE_READY;
1176   }
1177   else
1178   {
1179     return HAL_ERROR;
1180   }
1181 
1182   return HAL_OK;
1183 }
1184 
1185 /**
1186   * @brief  Returns the SDRAM memory current mode.
1187   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1188   *                the configuration information for SDRAM module.
1189   * @retval The SDRAM memory mode.
1190   */
1191 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
1192 {
1193   /* Return the SDRAM memory current mode */
1194   return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
1195 }
1196 
1197 /**
1198   * @}
1199   */
1200 
1201 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
1202   * @ingroup RTEMSBSPsARMSTM32H7
1203   *  @brief   Peripheral State functions
1204   *
1205 @verbatim
1206   ==============================================================================
1207                       ##### SDRAM State functions #####
1208   ==============================================================================
1209   [..]
1210     This subsection permits to get in run-time the status of the SDRAM controller
1211     and the data flow.
1212 
1213 @endverbatim
1214   * @{
1215   */
1216 
1217 /**
1218   * @brief  Returns the SDRAM state.
1219   * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1220   *                the configuration information for SDRAM module.
1221   * @retval HAL state
1222   */
1223 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
1224 {
1225   return hsdram->State;
1226 }
1227 
1228 /**
1229   * @}
1230   */
1231 
1232 /**
1233   * @}
1234   */
1235 
1236 /** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
1237   * @{
1238   */
1239 /**
1240   * @brief  MDMA SDRAM process complete callback.
1241   * @param  hmdma : MDMA handle
1242   * @retval None
1243   */
1244 static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma)
1245 {
1246   SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent);
1247 
1248   /* Disable the MDMA channel */
1249   __HAL_MDMA_DISABLE(hmdma);
1250 
1251   /* Update the SDRAM controller state */
1252   hsdram->State = HAL_SDRAM_STATE_READY;
1253 
1254 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1255   hsdram->DmaXferCpltCallback(hmdma);
1256 #else
1257   HAL_SDRAM_DMA_XferCpltCallback(hmdma);
1258 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1259 }
1260 
1261 /**
1262   * @brief  MDMA SRAM process complete callback.
1263   * @param  hmdma : MDMA handle
1264   * @retval None
1265   */
1266 static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma)
1267 {
1268   SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent);
1269 
1270   /* Disable the MDMA channel */
1271   __HAL_MDMA_DISABLE(hmdma);
1272 
1273   /* Update the SDRAM controller state */
1274   hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1275 
1276 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1277   hsdram->DmaXferCpltCallback(hmdma);
1278 #else
1279   HAL_SDRAM_DMA_XferCpltCallback(hmdma);
1280 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1281 }
1282 
1283 /**
1284   * @brief  MDMA SDRAM error callback.
1285   * @param  hmdma : MDMA handle
1286   * @retval None
1287   */
1288 static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma)
1289 {
1290   SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent);
1291 
1292   /* Disable the MDMA channel */
1293   __HAL_MDMA_DISABLE(hmdma);
1294 
1295   /* Update the SDRAM controller state */
1296   hsdram->State = HAL_SDRAM_STATE_ERROR;
1297 
1298 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1299   hsdram->DmaXferErrorCallback(hmdma);
1300 #else
1301   HAL_SDRAM_DMA_XferErrorCallback(hmdma);
1302 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1303 }
1304 
1305 /**
1306   * @}
1307   */
1308 /**
1309   * @}
1310   */
1311 
1312 #endif /* HAL_SDRAM_MODULE_ENABLED */
1313 
1314 /**
1315   * @}
1316   */
1317