stm32h7/hal/stm32h7xx_hal_rcc_ex.c

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_rcc_ex.c
0004   * @author  MCD Application Team
0005   * @brief   Extended RCC HAL module driver.
0006   *          This file provides firmware functions to manage the following
0007   *          functionalities RCC extension peripheral:
0008   *           + Extended Peripheral Control functions
0009   *
0010   ******************************************************************************
0011   * @attention
0012   *
0013   * Copyright (c) 2017 STMicroelectronics.
0014   * All rights reserved.
0015   *
0016   * This software is licensed under terms that can be found in the LICENSE file in
0017   * the root directory of this software component.
0018   * If no LICENSE file comes with this software, it is provided AS-IS.
0019   ******************************************************************************
0020   */
0021
0022 /* Includes ------------------------------------------------------------------*/
0023 #include "stm32h7xx_hal.h"
0024
0025 /** @addtogroup STM32H7xx_HAL_Driver
0026   * @{
0027   */
0028
0029 /** @defgroup RCCEx  RCCEx
0030   * @ingroup RTEMSBSPsARMSTM32H7
0031   * @brief RCC HAL module driver
0032   * @{
0033   */
0034
0035 #ifdef HAL_RCC_MODULE_ENABLED
0036
0037 /* Private typedef -----------------------------------------------------------*/
0038 /* Private defines -----------------------------------------------------------*/
0039 /** @defgroup RCCEx_Private_defines RCCEx Private Defines
0040   * @ingroup RTEMSBSPsARMSTM32H7
0041  * @{
0042  */
0043 #define PLL2_TIMEOUT_VALUE         PLL_TIMEOUT_VALUE    /* 2 ms */
0044 #define PLL3_TIMEOUT_VALUE         PLL_TIMEOUT_VALUE    /* 2 ms */
0045
0046 #define DIVIDER_P_UPDATE          0U
0047 #define DIVIDER_Q_UPDATE          1U
0048 #define DIVIDER_R_UPDATE          2U
0049 /**
0050   * @}
0051   */
0052
0053 /* Private macros ------------------------------------------------------------*/
0054 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
0055   * @ingroup RTEMSBSPsARMSTM32H7
0056  * @{
0057  */
0058 /**
0059   * @}
0060   */
0061
0062 /* Private variables ---------------------------------------------------------*/
0063 /* Private function prototypes -----------------------------------------------*/
0064 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider);
0065 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider);
0066
0067 /* Exported functions --------------------------------------------------------*/
0068 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
0069   * @ingroup RTEMSBSPsARMSTM32H7
0070   * @{
0071   */
0072
0073 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
0074   * @ingroup RTEMSBSPsARMSTM32H7
0075  *  @brief  Extended Peripheral Control functions
0076  *
0077 @verbatim
0078  ===============================================================================
0079                 ##### Extended Peripheral Control functions  #####
0080  ===============================================================================
0081     [..]
0082     This subsection provides a set of functions allowing to control the RCC Clocks
0083     frequencies.
0084     [..]
0085     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
0086         select the RTC clock source; in this case the Backup domain will be reset in
0087         order to modify the RTC Clock source, as consequence RTC registers (including
0088         the backup registers) and RCC_BDCR register are set to their reset values.
0089
0090 @endverbatim
0091   * @{
0092   */
0093 /**
0094   * @brief  Initializes the RCC extended peripherals clocks according to the specified
0095   *         parameters in the RCC_PeriphCLKInitTypeDef.
0096   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
0097   *         contains the configuration information for the Extended Peripherals
0098   *         clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123,
0099   *         USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
0100   *         SAI4A*, SAI4B*, SPI6, RTC).
0101   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
0102   *         the RTC clock source; in this case the Backup domain will be reset in
0103   *         order to modify the RTC Clock source, as consequence RTC registers (including
0104   *         the backup registers) are set to their reset values.
0105   *
0106   * (*) : Available on some STM32H7 lines only.
0107   *
0108   * @retval HAL status
0109   */
0110 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
0111 {
0112   uint32_t tmpreg;
0113   uint32_t tickstart;
0114   HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
0115   HAL_StatusTypeDef status = HAL_OK;   /* Final status */
0116
0117   /*---------------------------- SPDIFRX configuration -------------------------------*/
0118
0119   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
0120   {
0121
0122     switch (PeriphClkInit->SpdifrxClockSelection)
0123     {
0124       case RCC_SPDIFRXCLKSOURCE_PLL:      /* PLL is used as clock source for SPDIFRX*/
0125         /* Enable PLL1Q Clock output generated form System PLL . */
0126         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
0127
0128         /* SPDIFRX clock source configuration done later after clock selection check */
0129         break;
0130
0131       case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
0132
0133         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
0134
0135         /* SPDIFRX clock source configuration done later after clock selection check */
0136         break;
0137
0138       case RCC_SPDIFRXCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPDIFRX*/
0139         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
0140
0141         /* SPDIFRX clock source configuration done later after clock selection check */
0142         break;
0143
0144       case RCC_SPDIFRXCLKSOURCE_HSI:
0145         /* Internal OSC clock is used as source of SPDIFRX clock*/
0146         /* SPDIFRX clock source configuration done later after clock selection check */
0147         break;
0148
0149       default:
0150         ret = HAL_ERROR;
0151         break;
0152     }
0153
0154     if (ret == HAL_OK)
0155     {
0156       /* Set the source of SPDIFRX clock*/
0157       __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
0158     }
0159     else
0160     {
0161       /* set overall return value */
0162       status = ret;
0163     }
0164   }
0165
0166   /*---------------------------- SAI1 configuration -------------------------------*/
0167   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
0168   {
0169     switch (PeriphClkInit->Sai1ClockSelection)
0170     {
0171       case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
0172         /* Enable SAI Clock output generated form System PLL . */
0173         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
0174
0175         /* SAI1 clock source configuration done later after clock selection check */
0176         break;
0177
0178       case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
0179
0180         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
0181
0182         /* SAI1 clock source configuration done later after clock selection check */
0183         break;
0184
0185       case RCC_SAI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI1*/
0186         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
0187
0188         /* SAI1 clock source configuration done later after clock selection check */
0189         break;
0190
0191       case RCC_SAI1CLKSOURCE_PIN:
0192         /* External clock is used as source of SAI1 clock*/
0193         /* SAI1 clock source configuration done later after clock selection check */
0194         break;
0195
0196       case RCC_SAI1CLKSOURCE_CLKP:
0197         /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
0198         /* SAI1 clock source configuration done later after clock selection check */
0199         break;
0200
0201       default:
0202         ret = HAL_ERROR;
0203         break;
0204     }
0205
0206     if (ret == HAL_OK)
0207     {
0208       /* Set the source of SAI1 clock*/
0209       __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
0210     }
0211     else
0212     {
0213       /* set overall return value */
0214       status = ret;
0215     }
0216   }
0217
0218 #if defined(SAI3)
0219   /*---------------------------- SAI2/3 configuration -------------------------------*/
0220   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
0221   {
0222     switch (PeriphClkInit->Sai23ClockSelection)
0223     {
0224       case RCC_SAI23CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2/3 */
0225         /* Enable SAI Clock output generated form System PLL . */
0226         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
0227
0228         /* SAI2/3 clock source configuration done later after clock selection check */
0229         break;
0230
0231       case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
0232
0233         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
0234
0235         /* SAI2/3 clock source configuration done later after clock selection check */
0236         break;
0237
0238       case RCC_SAI23CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2/3 */
0239         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
0240
0241         /* SAI2/3 clock source configuration done later after clock selection check */
0242         break;
0243
0244       case RCC_SAI23CLKSOURCE_PIN:
0245         /* External clock is used as source of SAI2/3 clock*/
0246         /* SAI2/3 clock source configuration done later after clock selection check */
0247         break;
0248
0249       case RCC_SAI23CLKSOURCE_CLKP:
0250         /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
0251         /* SAI2/3 clock source configuration done later after clock selection check */
0252         break;
0253
0254       default:
0255         ret = HAL_ERROR;
0256         break;
0257     }
0258
0259     if (ret == HAL_OK)
0260     {
0261       /* Set the source of SAI2/3 clock*/
0262       __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
0263     }
0264     else
0265     {
0266       /* set overall return value */
0267       status = ret;
0268     }
0269   }
0270
0271 #endif /* SAI3 */
0272
0273 #if defined(RCC_CDCCIP1R_SAI2ASEL)
0274   /*---------------------------- SAI2A configuration -------------------------------*/
0275   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A)
0276   {
0277     switch (PeriphClkInit->Sai2AClockSelection)
0278     {
0279       case RCC_SAI2ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2A */
0280         /* Enable SAI2A Clock output generated form System PLL . */
0281         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
0282
0283         /* SAI2A clock source configuration done later after clock selection check */
0284         break;
0285
0286       case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */
0287
0288         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
0289
0290         /* SAI2A clock source configuration done later after clock selection check */
0291         break;
0292
0293       case RCC_SAI2ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2A */
0294         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
0295
0296         /* SAI2A clock source configuration done later after clock selection check */
0297         break;
0298
0299       case RCC_SAI2ACLKSOURCE_PIN:
0300         /* External clock is used as source of SAI2A clock*/
0301         /* SAI2A clock source configuration done later after clock selection check */
0302         break;
0303
0304       case RCC_SAI2ACLKSOURCE_CLKP:
0305         /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */
0306         /* SAI2A clock source configuration done later after clock selection check */
0307         break;
0308
0309       case RCC_SAI2ACLKSOURCE_SPDIF:
0310         /* SPDIF clock is used as source of SAI2A clock */
0311         /* SAI2A clock source configuration done later after clock selection check */
0312         break;
0313
0314       default:
0315         ret = HAL_ERROR;
0316         break;
0317     }
0318
0319     if (ret == HAL_OK)
0320     {
0321       /* Set the source of SAI2A clock*/
0322       __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection);
0323     }
0324     else
0325     {
0326       /* set overall return value */
0327       status = ret;
0328     }
0329   }
0330 #endif  /*SAI2A*/
0331
0332 #if defined(RCC_CDCCIP1R_SAI2BSEL)
0333
0334   /*---------------------------- SAI2B configuration -------------------------------*/
0335   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B)
0336   {
0337     switch (PeriphClkInit->Sai2BClockSelection)
0338     {
0339       case RCC_SAI2BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2B */
0340         /* Enable SAI Clock output generated form System PLL . */
0341         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
0342
0343         /* SAI2B clock source configuration done later after clock selection check */
0344         break;
0345
0346       case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */
0347
0348         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
0349
0350         /* SAI2B clock source configuration done later after clock selection check */
0351         break;
0352
0353       case RCC_SAI2BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2B */
0354         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
0355
0356         /* SAI2B clock source configuration done later after clock selection check */
0357         break;
0358
0359       case RCC_SAI2BCLKSOURCE_PIN:
0360         /* External clock is used as source of SAI2B clock*/
0361         /* SAI2B clock source configuration done later after clock selection check */
0362         break;
0363
0364       case RCC_SAI2BCLKSOURCE_CLKP:
0365         /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */
0366         /* SAI2B clock source configuration done later after clock selection check */
0367         break;
0368
0369       case RCC_SAI2BCLKSOURCE_SPDIF:
0370         /* SPDIF clock is used as source of SAI2B clock */
0371         /* SAI2B clock source configuration done later after clock selection check */
0372         break;
0373
0374       default:
0375         ret = HAL_ERROR;
0376         break;
0377     }
0378
0379     if (ret == HAL_OK)
0380     {
0381       /* Set the source of SAI2B clock*/
0382       __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection);
0383     }
0384     else
0385     {
0386       /* set overall return value */
0387       status = ret;
0388     }
0389   }
0390 #endif  /*SAI2B*/
0391
0392 #if defined(SAI4)
0393   /*---------------------------- SAI4A configuration -------------------------------*/
0394   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
0395   {
0396     switch (PeriphClkInit->Sai4AClockSelection)
0397     {
0398       case RCC_SAI4ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
0399         /* Enable SAI Clock output generated form System PLL . */
0400         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
0401
0402         /* SAI1 clock source configuration done later after clock selection check */
0403         break;
0404
0405       case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
0406
0407         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
0408
0409         /* SAI2 clock source configuration done later after clock selection check */
0410         break;
0411
0412       case RCC_SAI4ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
0413         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
0414
0415         /* SAI1 clock source configuration done later after clock selection check */
0416         break;
0417
0418       case RCC_SAI4ACLKSOURCE_PIN:
0419         /* External clock is used as source of SAI2 clock*/
0420         /* SAI2 clock source configuration done later after clock selection check */
0421         break;
0422
0423       case RCC_SAI4ACLKSOURCE_CLKP:
0424         /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
0425         /* SAI1 clock source configuration done later after clock selection check */
0426         break;
0427
0428 #if defined(RCC_VER_3_0)
0429       case RCC_SAI4ACLKSOURCE_SPDIF:
0430         /* SPDIF clock is used as source of SAI4A clock */
0431         /* SAI4A clock source configuration done later after clock selection check */
0432         break;
0433 #endif /* RCC_VER_3_0 */
0434
0435       default:
0436         ret = HAL_ERROR;
0437         break;
0438     }
0439
0440     if (ret == HAL_OK)
0441     {
0442       /* Set the source of SAI4A clock*/
0443       __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
0444     }
0445     else
0446     {
0447       /* set overall return value */
0448       status = ret;
0449     }
0450   }
0451   /*---------------------------- SAI4B configuration -------------------------------*/
0452   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
0453   {
0454     switch (PeriphClkInit->Sai4BClockSelection)
0455     {
0456       case RCC_SAI4BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
0457         /* Enable SAI Clock output generated form System PLL . */
0458         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
0459
0460         /* SAI1 clock source configuration done later after clock selection check */
0461         break;
0462
0463       case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
0464
0465         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
0466
0467         /* SAI2 clock source configuration done later after clock selection check */
0468         break;
0469
0470       case RCC_SAI4BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
0471         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
0472
0473         /* SAI1 clock source configuration done later after clock selection check */
0474         break;
0475
0476       case RCC_SAI4BCLKSOURCE_PIN:
0477         /* External clock is used as source of SAI2 clock*/
0478         /* SAI2 clock source configuration done later after clock selection check */
0479         break;
0480
0481       case RCC_SAI4BCLKSOURCE_CLKP:
0482         /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
0483         /* SAI1 clock source configuration done later after clock selection check */
0484         break;
0485
0486 #if defined(RCC_VER_3_0)
0487       case RCC_SAI4BCLKSOURCE_SPDIF:
0488         /* SPDIF clock is used as source of SAI4B clock */
0489         /* SAI4B clock source configuration done later after clock selection check */
0490         break;
0491 #endif /* RCC_VER_3_0 */
0492
0493       default:
0494         ret = HAL_ERROR;
0495         break;
0496     }
0497
0498     if (ret == HAL_OK)
0499     {
0500       /* Set the source of SAI4B clock*/
0501       __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
0502     }
0503     else
0504     {
0505       /* set overall return value */
0506       status = ret;
0507     }
0508   }
0509 #endif  /*SAI4*/
0510
0511 #if defined(QUADSPI)
0512   /*---------------------------- QSPI configuration -------------------------------*/
0513   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
0514   {
0515     switch (PeriphClkInit->QspiClockSelection)
0516     {
0517       case RCC_QSPICLKSOURCE_PLL:      /* PLL is used as clock source for QSPI*/
0518         /* Enable QSPI Clock output generated form System PLL . */
0519         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
0520
0521         /* QSPI clock source configuration done later after clock selection check */
0522         break;
0523
0524       case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
0525
0526         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
0527
0528         /* QSPI clock source configuration done later after clock selection check */
0529         break;
0530
0531
0532       case RCC_QSPICLKSOURCE_CLKP:
0533         /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
0534         /* QSPI clock source configuration done later after clock selection check */
0535         break;
0536
0537       case RCC_QSPICLKSOURCE_D1HCLK:
0538         /* Domain1 HCLK  clock selected as QSPI kernel peripheral clock */
0539         break;
0540
0541       default:
0542         ret = HAL_ERROR;
0543         break;
0544     }
0545
0546     if (ret == HAL_OK)
0547     {
0548       /* Set the source of QSPI clock*/
0549       __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
0550     }
0551     else
0552     {
0553       /* set overall return value */
0554       status = ret;
0555     }
0556   }
0557 #endif  /*QUADSPI*/
0558
0559 #if defined(OCTOSPI1) || defined(OCTOSPI2)
0560   /*---------------------------- OCTOSPI configuration -------------------------------*/
0561   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
0562   {
0563     switch (PeriphClkInit->OspiClockSelection)
0564     {
0565       case RCC_OSPICLKSOURCE_PLL:      /* PLL is used as clock source for OSPI*/
0566         /* Enable OSPI Clock output generated form System PLL . */
0567         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
0568
0569         /* OSPI clock source configuration done later after clock selection check */
0570         break;
0571
0572       case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/
0573
0574         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
0575
0576         /* OSPI clock source configuration done later after clock selection check */
0577         break;
0578
0579
0580       case RCC_OSPICLKSOURCE_CLKP:
0581         /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */
0582         /* OSPI clock source configuration done later after clock selection check */
0583         break;
0584
0585       case RCC_OSPICLKSOURCE_HCLK:
0586         /* HCLK clock selected as OSPI kernel peripheral clock */
0587         break;
0588
0589       default:
0590         ret = HAL_ERROR;
0591         break;
0592     }
0593
0594     if (ret == HAL_OK)
0595     {
0596       /* Set the source of OSPI clock*/
0597       __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
0598     }
0599     else
0600     {
0601       /* set overall return value */
0602       status = ret;
0603     }
0604   }
0605 #endif  /*OCTOSPI*/
0606
0607   /*---------------------------- SPI1/2/3 configuration -------------------------------*/
0608   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
0609   {
0610     switch (PeriphClkInit->Spi123ClockSelection)
0611     {
0612       case RCC_SPI123CLKSOURCE_PLL:      /* PLL is used as clock source for SPI1/2/3 */
0613         /* Enable SPI Clock output generated form System PLL . */
0614         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
0615
0616         /* SPI1/2/3 clock source configuration done later after clock selection check */
0617         break;
0618
0619       case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
0620         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
0621
0622         /* SPI1/2/3 clock source configuration done later after clock selection check */
0623         break;
0624
0625       case RCC_SPI123CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI1/2/3 */
0626         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
0627
0628         /* SPI1/2/3 clock source configuration done later after clock selection check */
0629         break;
0630
0631       case RCC_SPI123CLKSOURCE_PIN:
0632         /* External clock is used as source of SPI1/2/3 clock*/
0633         /* SPI1/2/3 clock source configuration done later after clock selection check */
0634         break;
0635
0636       case RCC_SPI123CLKSOURCE_CLKP:
0637         /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
0638         /* SPI1/2/3 clock source configuration done later after clock selection check */
0639         break;
0640
0641       default:
0642         ret = HAL_ERROR;
0643         break;
0644     }
0645
0646     if (ret == HAL_OK)
0647     {
0648       /* Set the source of SPI1/2/3 clock*/
0649       __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
0650     }
0651     else
0652     {
0653       /* set overall return value */
0654       status = ret;
0655     }
0656   }
0657
0658   /*---------------------------- SPI4/5 configuration -------------------------------*/
0659   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
0660   {
0661     switch (PeriphClkInit->Spi45ClockSelection)
0662     {
0663       case RCC_SPI45CLKSOURCE_PCLK2:      /* CD/D2 PCLK2 as clock source for SPI4/5 */
0664         /* SPI4/5 clock source configuration done later after clock selection check */
0665         break;
0666
0667       case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
0668
0669         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
0670
0671         /* SPI4/5 clock source configuration done later after clock selection check */
0672         break;
0673       case RCC_SPI45CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI4/5 */
0674         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
0675         /* SPI4/5 clock source configuration done later after clock selection check */
0676         break;
0677
0678       case RCC_SPI45CLKSOURCE_HSI:
0679         /* HSI oscillator clock is used as source of SPI4/5 clock*/
0680         /* SPI4/5 clock source configuration done later after clock selection check */
0681         break;
0682
0683       case RCC_SPI45CLKSOURCE_CSI:
0684         /*  CSI oscillator clock is used as source of SPI4/5 clock */
0685         /* SPI4/5 clock source configuration done later after clock selection check */
0686         break;
0687
0688       case RCC_SPI45CLKSOURCE_HSE:
0689         /* HSE,  oscillator is used as source of SPI4/5 clock */
0690         /* SPI4/5 clock source configuration done later after clock selection check */
0691         break;
0692
0693       default:
0694         ret = HAL_ERROR;
0695         break;
0696     }
0697
0698     if (ret == HAL_OK)
0699     {
0700       /* Set the source of SPI4/5 clock*/
0701       __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
0702     }
0703     else
0704     {
0705       /* set overall return value */
0706       status = ret;
0707     }
0708   }
0709
0710   /*---------------------------- SPI6 configuration -------------------------------*/
0711   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
0712   {
0713     switch (PeriphClkInit->Spi6ClockSelection)
0714     {
0715       case RCC_SPI6CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/
0716         /* SPI6 clock source configuration done later after clock selection check */
0717         break;
0718
0719       case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
0720
0721         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
0722
0723         /* SPI6 clock source configuration done later after clock selection check */
0724         break;
0725       case RCC_SPI6CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI6*/
0726         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
0727         /* SPI6 clock source configuration done later after clock selection check */
0728         break;
0729
0730       case RCC_SPI6CLKSOURCE_HSI:
0731         /* HSI oscillator clock is used as source of SPI6 clock*/
0732         /* SPI6 clock source configuration done later after clock selection check */
0733         break;
0734
0735       case RCC_SPI6CLKSOURCE_CSI:
0736         /*  CSI oscillator clock is used as source of SPI6 clock */
0737         /* SPI6 clock source configuration done later after clock selection check */
0738         break;
0739
0740       case RCC_SPI6CLKSOURCE_HSE:
0741         /* HSE,  oscillator is used as source of SPI6 clock */
0742         /* SPI6 clock source configuration done later after clock selection check */
0743         break;
0744 #if defined(RCC_SPI6CLKSOURCE_PIN)
0745       case RCC_SPI6CLKSOURCE_PIN:
0746         /* 2S_CKIN is used as source of SPI6 clock */
0747         /* SPI6 clock source configuration done later after clock selection check */
0748         break;
0749 #endif
0750
0751       default:
0752         ret = HAL_ERROR;
0753         break;
0754     }
0755
0756     if (ret == HAL_OK)
0757     {
0758       /* Set the source of SPI6 clock*/
0759       __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
0760     }
0761     else
0762     {
0763       /* set overall return value */
0764       status = ret;
0765     }
0766   }
0767
0768 #if defined(DSI)
0769   /*---------------------------- DSI configuration -------------------------------*/
0770   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
0771   {
0772     switch (PeriphClkInit->DsiClockSelection)
0773     {
0774
0775       case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/
0776
0777         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
0778
0779         /* DSI clock source configuration done later after clock selection check */
0780         break;
0781
0782       case RCC_DSICLKSOURCE_PHY:
0783         /* PHY is used as clock source for DSI*/
0784         /* DSI clock source configuration done later after clock selection check */
0785         break;
0786
0787       default:
0788         ret = HAL_ERROR;
0789         break;
0790     }
0791
0792     if (ret == HAL_OK)
0793     {
0794       /* Set the source of DSI clock*/
0795       __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
0796     }
0797     else
0798     {
0799       /* set overall return value */
0800       status = ret;
0801     }
0802   }
0803 #endif /*DSI*/
0804
0805 #if defined(FDCAN1) || defined(FDCAN2)
0806   /*---------------------------- FDCAN configuration -------------------------------*/
0807   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
0808   {
0809     switch (PeriphClkInit->FdcanClockSelection)
0810     {
0811       case RCC_FDCANCLKSOURCE_PLL:      /* PLL is used as clock source for FDCAN*/
0812         /* Enable FDCAN Clock output generated form System PLL . */
0813         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
0814
0815         /* FDCAN clock source configuration done later after clock selection check */
0816         break;
0817
0818       case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
0819
0820         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
0821
0822         /* FDCAN clock source configuration done later after clock selection check */
0823         break;
0824
0825       case RCC_FDCANCLKSOURCE_HSE:
0826         /* HSE is used as clock source for FDCAN*/
0827         /* FDCAN clock source configuration done later after clock selection check */
0828         break;
0829
0830       default:
0831         ret = HAL_ERROR;
0832         break;
0833     }
0834
0835     if (ret == HAL_OK)
0836     {
0837       /* Set the source of FDCAN clock*/
0838       __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
0839     }
0840     else
0841     {
0842       /* set overall return value */
0843       status = ret;
0844     }
0845   }
0846 #endif /*FDCAN1 || FDCAN2*/
0847
0848   /*---------------------------- FMC configuration -------------------------------*/
0849   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
0850   {
0851     switch (PeriphClkInit->FmcClockSelection)
0852     {
0853       case RCC_FMCCLKSOURCE_PLL:      /* PLL is used as clock source for FMC*/
0854         /* Enable FMC Clock output generated form System PLL . */
0855         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
0856
0857         /* FMC clock source configuration done later after clock selection check */
0858         break;
0859
0860       case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
0861
0862         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
0863
0864         /* FMC clock source configuration done later after clock selection check */
0865         break;
0866
0867
0868       case RCC_FMCCLKSOURCE_CLKP:
0869         /* HSI, HSE, or CSI oscillator is used as source of FMC clock */
0870         /* FMC clock source configuration done later after clock selection check */
0871         break;
0872
0873       case RCC_FMCCLKSOURCE_HCLK:
0874         /* D1/CD HCLK  clock selected as FMC kernel peripheral clock */
0875         break;
0876
0877       default:
0878         ret = HAL_ERROR;
0879         break;
0880     }
0881
0882     if (ret == HAL_OK)
0883     {
0884       /* Set the source of FMC clock*/
0885       __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
0886     }
0887     else
0888     {
0889       /* set overall return value */
0890       status = ret;
0891     }
0892   }
0893
0894   /*---------------------------- RTC configuration -------------------------------*/
0895   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
0896   {
0897     /* check for RTC Parameters used to output RTCCLK */
0898     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
0899
0900     /* Enable write access to Backup domain */
0901     SET_BIT(PWR->CR1, PWR_CR1_DBP);
0902
0903     /* Wait for Backup domain Write protection disable */
0904     tickstart = HAL_GetTick();
0905
0906     while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
0907     {
0908       if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
0909       {
0910         ret = HAL_TIMEOUT;
0911         break;
0912       }
0913     }
0914
0915     if (ret == HAL_OK)
0916     {
0917       /* Reset the Backup domain only if the RTC Clock source selection is modified */
0918       if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
0919       {
0920         /* Store the content of BDCR register before the reset of Backup Domain */
0921         tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
0922         /* RTC Clock selection can be changed only if the Backup Domain is reset */
0923         __HAL_RCC_BACKUPRESET_FORCE();
0924         __HAL_RCC_BACKUPRESET_RELEASE();
0925         /* Restore the Content of BDCR register */
0926         RCC->BDCR = tmpreg;
0927       }
0928
0929       /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
0930       if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
0931       {
0932         /* Get Start Tick*/
0933         tickstart = HAL_GetTick();
0934
0935         /* Wait till LSE is ready */
0936         while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
0937         {
0938           if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
0939           {
0940             ret = HAL_TIMEOUT;
0941             break;
0942           }
0943         }
0944       }
0945
0946       if (ret == HAL_OK)
0947       {
0948         __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
0949       }
0950       else
0951       {
0952         /* set overall return value */
0953         status = ret;
0954       }
0955     }
0956     else
0957     {
0958       /* set overall return value */
0959       status = ret;
0960     }
0961   }
0962
0963
0964   /*-------------------------- USART1/6 configuration --------------------------*/
0965   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
0966   {
0967     switch (PeriphClkInit->Usart16ClockSelection)
0968     {
0969       case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
0970         /* USART1/6 clock source configuration done later after clock selection check */
0971         break;
0972
0973       case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
0974         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
0975         /* USART1/6 clock source configuration done later after clock selection check */
0976         break;
0977
0978       case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
0979         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
0980         /* USART1/6 clock source configuration done later after clock selection check */
0981         break;
0982
0983       case RCC_USART16CLKSOURCE_HSI:
0984         /* HSI oscillator clock is used as source of USART1/6 clock */
0985         /* USART1/6 clock source configuration done later after clock selection check */
0986         break;
0987
0988       case RCC_USART16CLKSOURCE_CSI:
0989         /* CSI oscillator clock is used as source of USART1/6 clock */
0990         /* USART1/6 clock source configuration done later after clock selection check */
0991         break;
0992
0993       case RCC_USART16CLKSOURCE_LSE:
0994         /* LSE,  oscillator is used as source of USART1/6 clock */
0995         /* USART1/6 clock source configuration done later after clock selection check */
0996         break;
0997
0998       default:
0999         ret = HAL_ERROR;
1000         break;
1001     }
1002
1003     if (ret == HAL_OK)
1004     {
1005       /* Set the source of USART1/6 clock */
1006       __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
1007     }
1008     else
1009     {
1010       /* set overall return value */
1011       status = ret;
1012     }
1013   }
1014
1015   /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
1016   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
1017   {
1018     switch (PeriphClkInit->Usart234578ClockSelection)
1019     {
1020       case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
1021         /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1022         break;
1023
1024       case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
1025         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
1026         /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1027         break;
1028
1029       case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
1030         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
1031         /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1032         break;
1033
1034       case RCC_USART234578CLKSOURCE_HSI:
1035         /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
1036         /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1037         break;
1038
1039       case RCC_USART234578CLKSOURCE_CSI:
1040         /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
1041         /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1042         break;
1043
1044       case RCC_USART234578CLKSOURCE_LSE:
1045         /* LSE,  oscillator is used as source of USART2/3/4/5/7/8 clock */
1046         /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1047         break;
1048
1049       default:
1050         ret = HAL_ERROR;
1051         break;
1052     }
1053
1054     if (ret == HAL_OK)
1055     {
1056       /* Set the source of USART2/3/4/5/7/8 clock */
1057       __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
1058     }
1059     else
1060     {
1061       /* set overall return value */
1062       status = ret;
1063     }
1064   }
1065
1066   /*-------------------------- LPUART1 Configuration -------------------------*/
1067   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
1068   {
1069     switch (PeriphClkInit->Lpuart1ClockSelection)
1070     {
1071       case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
1072         /* LPUART1 clock source configuration done later after clock selection check */
1073         break;
1074
1075       case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
1076         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
1077         /* LPUART1 clock source configuration done later after clock selection check */
1078         break;
1079
1080       case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
1081         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
1082         /* LPUART1 clock source configuration done later after clock selection check */
1083         break;
1084
1085       case RCC_LPUART1CLKSOURCE_HSI:
1086         /* HSI oscillator clock is used as source of LPUART1 clock */
1087         /* LPUART1 clock source configuration done later after clock selection check */
1088         break;
1089
1090       case RCC_LPUART1CLKSOURCE_CSI:
1091         /* CSI oscillator clock is used as source of LPUART1 clock */
1092         /* LPUART1 clock source configuration done later after clock selection check */
1093         break;
1094
1095       case RCC_LPUART1CLKSOURCE_LSE:
1096         /* LSE,  oscillator is used as source of LPUART1 clock */
1097         /* LPUART1 clock source configuration done later after clock selection check */
1098         break;
1099
1100       default:
1101         ret = HAL_ERROR;
1102         break;
1103     }
1104
1105     if (ret == HAL_OK)
1106     {
1107       /* Set the source of LPUART1 clock */
1108       __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
1109     }
1110     else
1111     {
1112       /* set overall return value */
1113       status = ret;
1114     }
1115   }
1116
1117   /*---------------------------- LPTIM1 configuration -------------------------------*/
1118   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
1119   {
1120     switch (PeriphClkInit->Lptim1ClockSelection)
1121     {
1122       case RCC_LPTIM1CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for LPTIM1*/
1123         /* LPTIM1 clock source configuration done later after clock selection check */
1124         break;
1125
1126       case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
1127
1128         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
1129
1130         /* LPTIM1 clock source configuration done later after clock selection check */
1131         break;
1132
1133       case RCC_LPTIM1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM1*/
1134         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
1135
1136         /* LPTIM1 clock source configuration done later after clock selection check */
1137         break;
1138
1139       case RCC_LPTIM1CLKSOURCE_LSE:
1140         /* External low speed OSC clock is used as source of LPTIM1 clock*/
1141         /* LPTIM1 clock source configuration done later after clock selection check */
1142         break;
1143
1144       case RCC_LPTIM1CLKSOURCE_LSI:
1145         /* Internal  low speed OSC clock is used  as source of LPTIM1 clock*/
1146         /* LPTIM1 clock source configuration done later after clock selection check */
1147         break;
1148       case RCC_LPTIM1CLKSOURCE_CLKP:
1149         /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
1150         /* LPTIM1 clock source configuration done later after clock selection check */
1151         break;
1152
1153       default:
1154         ret = HAL_ERROR;
1155         break;
1156     }
1157
1158     if (ret == HAL_OK)
1159     {
1160       /* Set the source of LPTIM1 clock*/
1161       __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
1162     }
1163     else
1164     {
1165       /* set overall return value */
1166       status = ret;
1167     }
1168   }
1169
1170   /*---------------------------- LPTIM2 configuration -------------------------------*/
1171   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
1172   {
1173     switch (PeriphClkInit->Lptim2ClockSelection)
1174     {
1175       case RCC_LPTIM2CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/
1176         /* LPTIM2 clock source configuration done later after clock selection check */
1177         break;
1178
1179       case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
1180
1181         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
1182
1183         /* LPTIM2 clock source configuration done later after clock selection check */
1184         break;
1185
1186       case RCC_LPTIM2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM2*/
1187         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
1188
1189         /* LPTIM2 clock source configuration done later after clock selection check */
1190         break;
1191
1192       case RCC_LPTIM2CLKSOURCE_LSE:
1193         /* External low speed OSC clock is used as source of LPTIM2 clock*/
1194         /* LPTIM2 clock source configuration done later after clock selection check */
1195         break;
1196
1197       case RCC_LPTIM2CLKSOURCE_LSI:
1198         /* Internal  low speed OSC clock is used  as source of LPTIM2 clock*/
1199         /* LPTIM2 clock source configuration done later after clock selection check */
1200         break;
1201       case RCC_LPTIM2CLKSOURCE_CLKP:
1202         /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
1203         /* LPTIM2 clock source configuration done later after clock selection check */
1204         break;
1205
1206       default:
1207         ret = HAL_ERROR;
1208         break;
1209     }
1210
1211     if (ret == HAL_OK)
1212     {
1213       /* Set the source of LPTIM2 clock*/
1214       __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
1215     }
1216     else
1217     {
1218       /* set overall return value */
1219       status = ret;
1220     }
1221   }
1222
1223   /*---------------------------- LPTIM345 configuration -------------------------------*/
1224   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
1225   {
1226     switch (PeriphClkInit->Lptim345ClockSelection)
1227     {
1228
1229       case RCC_LPTIM345CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
1230         /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1231         break;
1232
1233       case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
1234         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
1235
1236         /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1237         break;
1238
1239       case RCC_LPTIM345CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM3/4/5 */
1240         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
1241
1242         /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1243         break;
1244
1245       case RCC_LPTIM345CLKSOURCE_LSE:
1246         /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */
1247         /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1248         break;
1249
1250       case RCC_LPTIM345CLKSOURCE_LSI:
1251         /* Internal  low speed OSC clock is used  as source of LPTIM3/4/5 clock */
1252         /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1253         break;
1254       case RCC_LPTIM345CLKSOURCE_CLKP:
1255         /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
1256         /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1257         break;
1258
1259       default:
1260         ret = HAL_ERROR;
1261         break;
1262     }
1263
1264     if (ret == HAL_OK)
1265     {
1266       /* Set the source of LPTIM3/4/5 clock */
1267       __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
1268     }
1269     else
1270     {
1271       /* set overall return value */
1272       status = ret;
1273     }
1274   }
1275
1276   /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/
1277 #if defined(I2C5)
1278   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235)
1279   {
1280     /* Check the parameters */
1281     assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection));
1282
1283     if ((PeriphClkInit->I2c1235ClockSelection) == RCC_I2C1235CLKSOURCE_PLL3)
1284     {
1285       if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
1286       {
1287         status = HAL_ERROR;
1288       }
1289     }
1290
1291     __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection);
1292
1293   }
1294 #else
1295   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
1296   {
1297     /* Check the parameters */
1298     assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));
1299
1300     if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3)
1301     {
1302       if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
1303       {
1304         status = HAL_ERROR;
1305       }
1306     }
1307
1308     __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
1309
1310   }
1311 #endif /* I2C5 */
1312
1313   /*------------------------------ I2C4 Configuration ------------------------*/
1314   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
1315   {
1316     /* Check the parameters */
1317     assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
1318
1319     if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3)
1320     {
1321       if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
1322       {
1323         status = HAL_ERROR;
1324       }
1325     }
1326
1327     __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
1328
1329   }
1330
1331   /*---------------------------- ADC configuration -------------------------------*/
1332   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
1333   {
1334     switch (PeriphClkInit->AdcClockSelection)
1335     {
1336
1337       case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
1338
1339         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
1340
1341         /* ADC clock source configuration done later after clock selection check */
1342         break;
1343
1344       case RCC_ADCCLKSOURCE_PLL3:  /* PLL3 is used as clock source for ADC*/
1345         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
1346
1347         /* ADC clock source configuration done later after clock selection check */
1348         break;
1349
1350       case RCC_ADCCLKSOURCE_CLKP:
1351         /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
1352         /* ADC clock source configuration done later after clock selection check */
1353         break;
1354
1355       default:
1356         ret = HAL_ERROR;
1357         break;
1358     }
1359
1360     if (ret == HAL_OK)
1361     {
1362       /* Set the source of ADC clock*/
1363       __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
1364     }
1365     else
1366     {
1367       /* set overall return value */
1368       status = ret;
1369     }
1370   }
1371
1372   /*------------------------------ USB Configuration -------------------------*/
1373   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
1374   {
1375
1376     switch (PeriphClkInit->UsbClockSelection)
1377     {
1378       case RCC_USBCLKSOURCE_PLL:      /* PLL is used as clock source for USB*/
1379         /* Enable USB Clock output generated form System USB . */
1380         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1381
1382         /* USB clock source configuration done later after clock selection check */
1383         break;
1384
1385       case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
1386
1387         ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
1388
1389         /* USB clock source configuration done later after clock selection check */
1390         break;
1391
1392       case RCC_USBCLKSOURCE_HSI48:
1393         /* HSI48 oscillator is used as source of USB clock */
1394         /* USB clock source configuration done later after clock selection check */
1395         break;
1396
1397       default:
1398         ret = HAL_ERROR;
1399         break;
1400     }
1401
1402     if (ret == HAL_OK)
1403     {
1404       /* Set the source of USB clock*/
1405       __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
1406     }
1407     else
1408     {
1409       /* set overall return value */
1410       status = ret;
1411     }
1412
1413   }
1414
1415   /*------------------------------------- SDMMC Configuration ------------------------------------*/
1416   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
1417   {
1418     /* Check the parameters */
1419     assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
1420
1421     switch (PeriphClkInit->SdmmcClockSelection)
1422     {
1423       case RCC_SDMMCCLKSOURCE_PLL:      /* PLL is used as clock source for SDMMC*/
1424         /* Enable SDMMC Clock output generated form System PLL . */
1425         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1426
1427         /* SDMMC clock source configuration done later after clock selection check */
1428         break;
1429
1430       case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
1431
1432         ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
1433
1434         /* SDMMC clock source configuration done later after clock selection check */
1435         break;
1436
1437       default:
1438         ret = HAL_ERROR;
1439         break;
1440     }
1441
1442     if (ret == HAL_OK)
1443     {
1444       /* Set the source of SDMMC clock*/
1445       __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
1446     }
1447     else
1448     {
1449       /* set overall return value */
1450       status = ret;
1451     }
1452   }
1453
1454 #if defined(LTDC)
1455   /*-------------------------------------- LTDC Configuration -----------------------------------*/
1456   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
1457   {
1458     if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
1459     {
1460       status = HAL_ERROR;
1461     }
1462   }
1463 #endif /* LTDC */
1464
1465   /*------------------------------ RNG Configuration -------------------------*/
1466   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
1467   {
1468
1469     switch (PeriphClkInit->RngClockSelection)
1470     {
1471       case RCC_RNGCLKSOURCE_PLL:     /* PLL is used as clock source for RNG*/
1472         /* Enable RNG Clock output generated form System RNG . */
1473         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1474
1475         /* RNG clock source configuration done later after clock selection check */
1476         break;
1477
1478       case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/
1479
1480         /* RNG clock source configuration done later after clock selection check */
1481         break;
1482
1483       case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/
1484
1485         /* RNG clock source configuration done later after clock selection check */
1486         break;
1487       case RCC_RNGCLKSOURCE_HSI48:
1488         /* HSI48 oscillator is used as source of RNG clock */
1489         /* RNG clock source configuration done later after clock selection check */
1490         break;
1491
1492       default:
1493         ret = HAL_ERROR;
1494         break;
1495     }
1496
1497     if (ret == HAL_OK)
1498     {
1499       /* Set the source of RNG clock*/
1500       __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
1501     }
1502     else
1503     {
1504       /* set overall return value */
1505       status = ret;
1506     }
1507
1508   }
1509
1510   /*------------------------------ SWPMI1 Configuration ------------------------*/
1511   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
1512   {
1513     /* Check the parameters */
1514     assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
1515
1516     /* Configure the SWPMI1 interface clock source */
1517     __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
1518   }
1519 #if defined(HRTIM1)
1520   /*------------------------------ HRTIM1 clock Configuration ----------------*/
1521   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
1522   {
1523     /* Check the parameters */
1524     assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
1525
1526     /* Configure the HRTIM1 clock source */
1527     __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
1528   }
1529 #endif  /*HRTIM1*/
1530   /*------------------------------ DFSDM1 Configuration ------------------------*/
1531   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
1532   {
1533     /* Check the parameters */
1534     assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
1535
1536     /* Configure the DFSDM1 interface clock source */
1537     __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
1538   }
1539
1540 #if defined(DFSDM2_BASE)
1541   /*------------------------------ DFSDM2 Configuration ------------------------*/
1542   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
1543   {
1544     /* Check the parameters */
1545     assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
1546
1547     /* Configure the DFSDM2 interface clock source */
1548     __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
1549   }
1550 #endif  /* DFSDM2 */
1551
1552   /*------------------------------------ TIM configuration --------------------------------------*/
1553   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
1554   {
1555     /* Check the parameters */
1556     assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
1557
1558     /* Configure Timer Prescaler */
1559     __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
1560   }
1561
1562   /*------------------------------------ CKPER configuration --------------------------------------*/
1563   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
1564   {
1565     /* Check the parameters */
1566     assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
1567
1568     /* Configure the CKPER clock source */
1569     __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
1570   }
1571
1572   /*------------------------------ CEC Configuration ------------------------*/
1573   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
1574   {
1575     /* Check the parameters */
1576     assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
1577
1578     /* Configure the CEC interface clock source */
1579     __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
1580   }
1581
1582   /*---------------------------- PLL2 configuration -------------------------------*/
1583   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP)
1584   {
1585     ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
1586
1587     if (ret == HAL_OK)
1588     {
1589       /*Nothing to do*/
1590     }
1591     else
1592     {
1593       /* set overall return value */
1594       status = ret;
1595     }
1596   }
1597
1598
1599   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ)
1600   {
1601     ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
1602
1603     if (ret == HAL_OK)
1604     {
1605       /*Nothing to do*/
1606     }
1607     else
1608     {
1609       /* set overall return value */
1610       status = ret;
1611     }
1612   }
1613
1614
1615   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR)
1616   {
1617     ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
1618
1619     if (ret == HAL_OK)
1620     {
1621       /*Nothing to do*/
1622     }
1623     else
1624     {
1625       /* set overall return value */
1626       status = ret;
1627     }
1628   }
1629
1630
1631   /*---------------------------- PLL3 configuration -------------------------------*/
1632   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP)
1633   {
1634     ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
1635
1636     if (ret == HAL_OK)
1637     {
1638       /*Nothing to do*/
1639     }
1640     else
1641     {
1642       /* set overall return value */
1643       status = ret;
1644     }
1645   }
1646
1647
1648   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ)
1649   {
1650     ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
1651
1652     if (ret == HAL_OK)
1653     {
1654       /*Nothing to do*/
1655     }
1656     else
1657     {
1658       /* set overall return value */
1659       status = ret;
1660     }
1661   }
1662
1663
1664   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
1665   {
1666     ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
1667
1668     if (ret == HAL_OK)
1669     {
1670       /*Nothing to do*/
1671     }
1672     else
1673     {
1674       /* set overall return value */
1675       status = ret;
1676     }
1677   }
1678
1679   if (status == HAL_OK)
1680   {
1681     return HAL_OK;
1682   }
1683   return HAL_ERROR;
1684 }
1685
1686 /**
1687   * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
1688   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
1689   *         returns the configuration information for the Extended Peripherals clocks :
1690   *         (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123,
1691   *         USART234578, USART16, RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC.
1692   *         SAI4A*, SAI4B*, SPI6, RTC, TIM).
1693   * @retval None
1694   *
1695   *   (*) : Available on some STM32H7 lines only.
1696   */
1697 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
1698 {
1699   /* Set all possible values for the extended clock type parameter------------*/
1700   PeriphClkInit->PeriphClockSelection =
1701     RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 |
1702     RCC_PERIPHCLK_I2C4    | RCC_PERIPHCLK_LPTIM1      | RCC_PERIPHCLK_LPTIM2  | RCC_PERIPHCLK_LPTIM345 |
1703     RCC_PERIPHCLK_SAI1    | RCC_PERIPHCLK_SPI123      | RCC_PERIPHCLK_SPI45   | RCC_PERIPHCLK_SPI6     |
1704     RCC_PERIPHCLK_FDCAN   | RCC_PERIPHCLK_SDMMC       | RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB      |
1705     RCC_PERIPHCLK_ADC     | RCC_PERIPHCLK_SWPMI1      | RCC_PERIPHCLK_DFSDM1  | RCC_PERIPHCLK_RTC      |
1706     RCC_PERIPHCLK_CEC     | RCC_PERIPHCLK_FMC         | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM      |
1707     RCC_PERIPHCLK_CKPER;
1708
1709 #if defined(I2C5)
1710   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235;
1711 #else
1712   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123;
1713 #endif /*I2C5*/
1714 #if defined(RCC_CDCCIP1R_SAI2ASEL)
1715   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A;
1716 #endif /* RCC_CDCCIP1R_SAI2ASEL */
1717 #if defined(RCC_CDCCIP1R_SAI2BSEL)
1718   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B;
1719 #endif /* RCC_CDCCIP1R_SAI2BSEL */
1720 #if defined(SAI3)
1721   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23;
1722 #endif /* SAI3 */
1723 #if defined(SAI4)
1724   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A;
1725   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B;
1726 #endif /* SAI4 */
1727 #if defined(DFSDM2_BASE)
1728   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2;
1729 #endif /* DFSDM2 */
1730 #if defined(QUADSPI)
1731   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI;
1732 #endif /* QUADSPI */
1733 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1734   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI;
1735 #endif /* OCTOSPI1 || OCTOSPI2 */
1736 #if defined(HRTIM1)
1737   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
1738 #endif /* HRTIM1 */
1739 #if defined(LTDC)
1740   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC;
1741 #endif /* LTDC */
1742 #if defined(DSI)
1743   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI;
1744 #endif /* DSI */
1745
1746   /* Get the PLL3 Clock configuration -----------------------------------------------*/
1747   PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos);
1748   PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1U;
1749   PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1U;
1750   PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1U;
1751   PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1U;
1752   PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos);
1753   PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos);
1754
1755   /* Get the PLL2 Clock configuration -----------------------------------------------*/
1756   PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos);
1757   PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1U;
1758   PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1U;
1759   PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1U;
1760   PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1U;
1761   PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos);
1762   PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos);
1763
1764   /* Get the USART1 configuration --------------------------------------------*/
1765   PeriphClkInit->Usart16ClockSelection      = __HAL_RCC_GET_USART16_SOURCE();
1766   /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/
1767   PeriphClkInit->Usart234578ClockSelection  = __HAL_RCC_GET_USART234578_SOURCE();
1768   /* Get the LPUART1 clock source --------------------------------------------*/
1769   PeriphClkInit->Lpuart1ClockSelection      = __HAL_RCC_GET_LPUART1_SOURCE();
1770 #if defined(I2C5)
1771   /* Get the I2C1/2/3/5 clock source -----------------------------------------*/
1772   PeriphClkInit->I2c1235ClockSelection       = __HAL_RCC_GET_I2C1_SOURCE();
1773 #else
1774   /* Get the I2C1/2/3 clock source -------------------------------------------*/
1775   PeriphClkInit->I2c123ClockSelection       = __HAL_RCC_GET_I2C1_SOURCE();
1776 #endif /*I2C5*/
1777   /* Get the LPTIM1 clock source ---------------------------------------------*/
1778   PeriphClkInit->Lptim1ClockSelection       = __HAL_RCC_GET_LPTIM1_SOURCE();
1779   /* Get the LPTIM2 clock source ---------------------------------------------*/
1780   PeriphClkInit->Lptim2ClockSelection       = __HAL_RCC_GET_LPTIM2_SOURCE();
1781   /* Get the LPTIM3/4/5 clock source -----------------------------------------*/
1782   PeriphClkInit->Lptim345ClockSelection     = __HAL_RCC_GET_LPTIM345_SOURCE();
1783   /* Get the SAI1 clock source -----------------------------------------------*/
1784   PeriphClkInit->Sai1ClockSelection         = __HAL_RCC_GET_SAI1_SOURCE();
1785 #if defined(SAI3)
1786   /* Get the SAI2/3 clock source ---------------------------------------------*/
1787   PeriphClkInit->Sai23ClockSelection        = __HAL_RCC_GET_SAI23_SOURCE();
1788 #endif  /*SAI3*/
1789 #if defined(RCC_CDCCIP1R_SAI2ASEL_0)
1790   /* Get the SAI2A clock source ---------------------------------------------*/
1791   PeriphClkInit->Sai2AClockSelection        = __HAL_RCC_GET_SAI2A_SOURCE();
1792 #endif  /*SAI2A*/
1793 #if defined(RCC_CDCCIP1R_SAI2BSEL_0)
1794   /* Get the SAI2B clock source ---------------------------------------------*/
1795   PeriphClkInit->Sai2BClockSelection        = __HAL_RCC_GET_SAI2B_SOURCE();
1796 #endif  /*SAI2B*/
1797 #if defined(SAI4)
1798   /* Get the SAI4A clock source ----------------------------------------------*/
1799   PeriphClkInit->Sai4AClockSelection        = __HAL_RCC_GET_SAI4A_SOURCE();
1800   /* Get the SAI4B clock source ----------------------------------------------*/
1801   PeriphClkInit->Sai4BClockSelection        = __HAL_RCC_GET_SAI4B_SOURCE();
1802 #endif  /*SAI4*/
1803   /* Get the RTC clock source ------------------------------------------------*/
1804   PeriphClkInit->RTCClockSelection          = __HAL_RCC_GET_RTC_SOURCE();
1805   /* Get the USB clock source ------------------------------------------------*/
1806   PeriphClkInit->UsbClockSelection          = __HAL_RCC_GET_USB_SOURCE();
1807   /* Get the SDMMC clock source ----------------------------------------------*/
1808   PeriphClkInit->SdmmcClockSelection        = __HAL_RCC_GET_SDMMC_SOURCE();
1809   /* Get the RNG clock source ------------------------------------------------*/
1810   PeriphClkInit->RngClockSelection          = __HAL_RCC_GET_RNG_SOURCE();
1811 #if defined(HRTIM1)
1812   /* Get the HRTIM1 clock source ---------------------------------------------*/
1813   PeriphClkInit->Hrtim1ClockSelection       = __HAL_RCC_GET_HRTIM1_SOURCE();
1814 #endif /* HRTIM1 */
1815   /* Get the ADC clock source ------------------------------------------------*/
1816   PeriphClkInit->AdcClockSelection          = __HAL_RCC_GET_ADC_SOURCE();
1817   /* Get the SWPMI1 clock source ---------------------------------------------*/
1818   PeriphClkInit->Swpmi1ClockSelection       = __HAL_RCC_GET_SWPMI1_SOURCE();
1819   /* Get the DFSDM1 clock source ---------------------------------------------*/
1820   PeriphClkInit->Dfsdm1ClockSelection       = __HAL_RCC_GET_DFSDM1_SOURCE();
1821 #if defined(DFSDM2_BASE)
1822   /* Get the DFSDM2 clock source ---------------------------------------------*/
1823   PeriphClkInit->Dfsdm2ClockSelection       = __HAL_RCC_GET_DFSDM2_SOURCE();
1824 #endif /* DFSDM2 */
1825   /* Get the SPDIFRX clock source --------------------------------------------*/
1826   PeriphClkInit->SpdifrxClockSelection      = __HAL_RCC_GET_SPDIFRX_SOURCE();
1827   /* Get the SPI1/2/3 clock source -------------------------------------------*/
1828   PeriphClkInit->Spi123ClockSelection       = __HAL_RCC_GET_SPI123_SOURCE();
1829   /* Get the SPI4/5 clock source ---------------------------------------------*/
1830   PeriphClkInit->Spi45ClockSelection        = __HAL_RCC_GET_SPI45_SOURCE();
1831   /* Get the SPI6 clock source -----------------------------------------------*/
1832   PeriphClkInit->Spi6ClockSelection         = __HAL_RCC_GET_SPI6_SOURCE();
1833   /* Get the FDCAN clock source ----------------------------------------------*/
1834   PeriphClkInit->FdcanClockSelection        = __HAL_RCC_GET_FDCAN_SOURCE();
1835   /* Get the CEC clock source ------------------------------------------------*/
1836   PeriphClkInit->CecClockSelection          = __HAL_RCC_GET_CEC_SOURCE();
1837   /* Get the FMC clock source ------------------------------------------------*/
1838   PeriphClkInit->FmcClockSelection          = __HAL_RCC_GET_FMC_SOURCE();
1839 #if defined(QUADSPI)
1840   /* Get the QSPI clock source -----------------------------------------------*/
1841   PeriphClkInit->QspiClockSelection         = __HAL_RCC_GET_QSPI_SOURCE();
1842 #endif /* QUADSPI */
1843 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1844   /* Get the OSPI clock source -----------------------------------------------*/
1845   PeriphClkInit->OspiClockSelection         = __HAL_RCC_GET_OSPI_SOURCE();
1846 #endif /* OCTOSPI1 || OCTOSPI2 */
1847
1848 #if defined(DSI)
1849   /* Get the DSI clock source ------------------------------------------------*/
1850   PeriphClkInit->DsiClockSelection          = __HAL_RCC_GET_DSI_SOURCE();
1851 #endif /*DSI*/
1852
1853   /* Get the CKPER clock source ----------------------------------------------*/
1854   PeriphClkInit->CkperClockSelection        = __HAL_RCC_GET_CLKP_SOURCE();
1855
1856   /* Get the TIM Prescaler configuration -------------------------------------*/
1857   if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U)
1858   {
1859     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
1860   }
1861   else
1862   {
1863     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
1864   }
1865 }
1866
1867 /**
1868   * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
1869   * @note   Return 0 if peripheral clock identifier not managed by this API
1870   * @param  PeriphClk: Peripheral clock identifier
1871   *         This parameter can be one of the following values:
1872   *            @arg RCC_PERIPHCLK_SAI1  : SAI1 peripheral clock
1873   *            @arg RCC_PERIPHCLK_SAI23 : SAI2/3  peripheral clock (*)
1874   *            @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*)
1875   *            @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*)
1876   *            @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*)
1877   *            @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*)
1878   *            @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock
1879   *            @arg RCC_PERIPHCLK_ADC   : ADC peripheral clock
1880   *            @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock
1881   *            @arg RCC_PERIPHCLK_SPI6  : SPI6 peripheral clock
1882   * @retval Frequency in KHz
1883   *
1884   *  (*) : Available on some STM32H7 lines only.
1885   */
1886 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
1887 {
1888   PLL1_ClocksTypeDef pll1_clocks;
1889   PLL2_ClocksTypeDef pll2_clocks;
1890   PLL3_ClocksTypeDef pll3_clocks;
1891
1892   /* This variable is used to store the clock frequency (value in Hz) */
1893   uint32_t frequency;
1894   /* This variable is used to store the SAI and CKP clock source */
1895   uint32_t saiclocksource;
1896   uint32_t ckpclocksource;
1897   uint32_t srcclk;
1898
1899   if (PeriphClk == RCC_PERIPHCLK_SAI1)
1900   {
1901
1902     saiclocksource = __HAL_RCC_GET_SAI1_SOURCE();
1903
1904     switch (saiclocksource)
1905     {
1906       case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
1907       {
1908         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
1909         {
1910           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1911           frequency = pll1_clocks.PLL1_Q_Frequency;
1912         }
1913         else
1914         {
1915           frequency = 0;
1916         }
1917         break;
1918       }
1919       case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
1920       {
1921         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
1922         {
1923           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1924           frequency = pll2_clocks.PLL2_P_Frequency;
1925         }
1926         else
1927         {
1928           frequency = 0;
1929         }
1930         break;
1931       }
1932
1933       case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
1934       {
1935         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
1936         {
1937           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
1938           frequency = pll3_clocks.PLL3_P_Frequency;
1939         }
1940         else
1941         {
1942           frequency = 0;
1943         }
1944         break;
1945       }
1946
1947       case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
1948       {
1949
1950         ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
1951
1952         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
1953         {
1954           /* In Case the CKPER Source is HSI */
1955           frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
1956         }
1957
1958         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
1959         {
1960           /* In Case the CKPER Source is CSI */
1961           frequency = CSI_VALUE;
1962         }
1963
1964         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
1965         {
1966           /* In Case the CKPER Source is HSE */
1967           frequency = HSE_VALUE;
1968         }
1969
1970         else
1971         {
1972           /* In Case the CKPER is disabled*/
1973           frequency = 0;
1974         }
1975
1976         break;
1977       }
1978
1979       case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
1980       {
1981         frequency = EXTERNAL_CLOCK_VALUE;
1982         break;
1983       }
1984       default :
1985       {
1986         frequency = 0;
1987         break;
1988       }
1989     }
1990   }
1991
1992 #if defined(SAI3)
1993   else if (PeriphClk == RCC_PERIPHCLK_SAI23)
1994   {
1995
1996     saiclocksource = __HAL_RCC_GET_SAI23_SOURCE();
1997
1998     switch (saiclocksource)
1999     {
2000       case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */
2001       {
2002         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2003         {
2004           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2005           frequency = pll1_clocks.PLL1_Q_Frequency;
2006         }
2007         else
2008         {
2009           frequency = 0;
2010         }
2011         break;
2012       }
2013       case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
2014       {
2015         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2016         {
2017           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2018           frequency = pll2_clocks.PLL2_P_Frequency;
2019         }
2020         else
2021         {
2022           frequency = 0;
2023         }
2024         break;
2025       }
2026
2027       case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
2028       {
2029         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2030         {
2031           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2032           frequency = pll3_clocks.PLL3_P_Frequency;
2033         }
2034         else
2035         {
2036           frequency = 0;
2037         }
2038         break;
2039       }
2040
2041       case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */
2042       {
2043
2044         ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2045
2046         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2047         {
2048           /* In Case the CKPER Source is HSI */
2049           frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2050         }
2051
2052         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2053         {
2054           /* In Case the CKPER Source is CSI */
2055           frequency = CSI_VALUE;
2056         }
2057
2058         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2059         {
2060           /* In Case the CKPER Source is HSE */
2061           frequency = HSE_VALUE;
2062         }
2063
2064         else
2065         {
2066           /* In Case the CKPER is disabled*/
2067           frequency = 0;
2068         }
2069
2070         break;
2071       }
2072
2073       case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */
2074       {
2075         frequency = EXTERNAL_CLOCK_VALUE;
2076         break;
2077       }
2078       default :
2079       {
2080         frequency = 0;
2081         break;
2082       }
2083     }
2084   }
2085 #endif /* SAI3 */
2086
2087 #if  defined(RCC_CDCCIP1R_SAI2ASEL)
2088
2089   else if (PeriphClk == RCC_PERIPHCLK_SAI2A)
2090   {
2091     saiclocksource = __HAL_RCC_GET_SAI2A_SOURCE();
2092
2093     switch (saiclocksource)
2094     {
2095       case RCC_SAI2ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI2A */
2096       {
2097         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2098         {
2099           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2100           frequency = pll1_clocks.PLL1_Q_Frequency;
2101         }
2102         else
2103         {
2104           frequency = 0;
2105         }
2106         break;
2107       }
2108       case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */
2109       {
2110         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2111         {
2112           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2113           frequency = pll2_clocks.PLL2_P_Frequency;
2114         }
2115         else
2116         {
2117           frequency = 0;
2118         }
2119         break;
2120       }
2121
2122       case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A  */
2123       {
2124         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2125         {
2126           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2127           frequency = pll3_clocks.PLL3_P_Frequency;
2128         }
2129         else
2130         {
2131           frequency = 0;
2132         }
2133         break;
2134       }
2135
2136       case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A  */
2137       {
2138
2139         ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2140
2141         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2142         {
2143           /* In Case the CKPER Source is HSI */
2144           frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2145         }
2146
2147         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2148         {
2149           /* In Case the CKPER Source is CSI */
2150           frequency = CSI_VALUE;
2151         }
2152
2153         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2154         {
2155           /* In Case the CKPER Source is HSE */
2156           frequency = HSE_VALUE;
2157         }
2158
2159         else
2160         {
2161           /* In Case the CKPER is disabled*/
2162           frequency = 0;
2163         }
2164
2165         break;
2166       }
2167
2168       case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */
2169       {
2170         frequency = EXTERNAL_CLOCK_VALUE;
2171         break;
2172       }
2173
2174       default :
2175       {
2176         frequency = 0;
2177         break;
2178       }
2179     }
2180
2181   }
2182 #endif
2183
2184 #if  defined(RCC_CDCCIP1R_SAI2BSEL_0)
2185   else if (PeriphClk == RCC_PERIPHCLK_SAI2B)
2186   {
2187
2188     saiclocksource = __HAL_RCC_GET_SAI2B_SOURCE();
2189
2190     switch (saiclocksource)
2191     {
2192       case RCC_SAI2BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI2B */
2193       {
2194         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2195         {
2196           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2197           frequency = pll1_clocks.PLL1_Q_Frequency;
2198         }
2199         else
2200         {
2201           frequency = 0;
2202         }
2203         break;
2204       }
2205       case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */
2206       {
2207         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2208         {
2209           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2210           frequency = pll2_clocks.PLL2_P_Frequency;
2211         }
2212         else
2213         {
2214           frequency = 0;
2215         }
2216         break;
2217       }
2218
2219       case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */
2220       {
2221         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2222         {
2223           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2224           frequency = pll3_clocks.PLL3_P_Frequency;
2225         }
2226         else
2227         {
2228           frequency = 0;
2229         }
2230         break;
2231       }
2232
2233       case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/
2234       {
2235
2236         ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2237
2238         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2239         {
2240           /* In Case the CKPER Source is HSI */
2241           frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2242         }
2243
2244         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2245         {
2246           /* In Case the CKPER Source is CSI */
2247           frequency = CSI_VALUE;
2248         }
2249
2250         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2251         {
2252           /* In Case the CKPER Source is HSE */
2253           frequency = HSE_VALUE;
2254         }
2255
2256         else
2257         {
2258           /* In Case the CKPER is disabled*/
2259           frequency = 0;
2260         }
2261         break;
2262       }
2263
2264       case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */
2265       {
2266         frequency = EXTERNAL_CLOCK_VALUE;
2267         break;
2268       }
2269
2270       default :
2271       {
2272         frequency = 0;
2273         break;
2274       }
2275     }
2276   }
2277 #endif
2278
2279 #if defined(SAI4)
2280   else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
2281   {
2282
2283     saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE();
2284
2285     switch (saiclocksource)
2286     {
2287       case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */
2288       {
2289         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2290         {
2291           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2292           frequency = pll1_clocks.PLL1_Q_Frequency;
2293         }
2294         else
2295         {
2296           frequency = 0;
2297         }
2298         break;
2299       }
2300       case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */
2301       {
2302         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2303         {
2304           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2305           frequency = pll2_clocks.PLL2_P_Frequency;
2306         }
2307         else
2308         {
2309           frequency = 0;
2310         }
2311         break;
2312       }
2313
2314       case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */
2315       {
2316         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2317         {
2318           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2319           frequency = pll3_clocks.PLL3_P_Frequency;
2320         }
2321         else
2322         {
2323           frequency = 0;
2324         }
2325         break;
2326       }
2327
2328       case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/
2329       {
2330
2331         ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2332
2333         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2334         {
2335           /* In Case the CKPER Source is HSI */
2336           frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2337         }
2338
2339         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2340         {
2341           /* In Case the CKPER Source is CSI */
2342           frequency = CSI_VALUE;
2343         }
2344
2345         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2346         {
2347           /* In Case the CKPER Source is HSE */
2348           frequency = HSE_VALUE;
2349         }
2350
2351         else
2352         {
2353           /* In Case the CKPER is disabled*/
2354           frequency = 0;
2355         }
2356
2357         break;
2358       }
2359
2360       case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */
2361       {
2362         frequency = EXTERNAL_CLOCK_VALUE;
2363         break;
2364       }
2365
2366       default :
2367       {
2368         frequency = 0;
2369         break;
2370       }
2371     }
2372   }
2373
2374   else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
2375   {
2376
2377     saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE();
2378
2379     switch (saiclocksource)
2380     {
2381       case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */
2382       {
2383         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2384         {
2385           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2386           frequency = pll1_clocks.PLL1_Q_Frequency;
2387         }
2388         else
2389         {
2390           frequency = 0;
2391         }
2392         break;
2393       }
2394       case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */
2395       {
2396         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2397         {
2398           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2399           frequency = pll2_clocks.PLL2_P_Frequency;
2400         }
2401         else
2402         {
2403           frequency = 0;
2404         }
2405         break;
2406       }
2407
2408       case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */
2409       {
2410         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2411         {
2412           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2413           frequency = pll3_clocks.PLL3_P_Frequency;
2414         }
2415         else
2416         {
2417           frequency = 0;
2418         }
2419         break;
2420       }
2421
2422       case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/
2423       {
2424
2425         ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2426
2427         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2428         {
2429           /* In Case the CKPER Source is HSI */
2430           frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2431         }
2432
2433         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2434         {
2435           /* In Case the CKPER Source is CSI */
2436           frequency = CSI_VALUE;
2437         }
2438
2439         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2440         {
2441           /* In Case the CKPER Source is HSE */
2442           frequency = HSE_VALUE;
2443         }
2444
2445         else
2446         {
2447           /* In Case the CKPER is disabled*/
2448           frequency = 0;
2449         }
2450
2451         break;
2452       }
2453
2454       case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */
2455       {
2456         frequency = EXTERNAL_CLOCK_VALUE;
2457         break;
2458       }
2459
2460       default :
2461       {
2462         frequency = 0;
2463         break;
2464       }
2465     }
2466   }
2467 #endif /*SAI4*/
2468   else if (PeriphClk == RCC_PERIPHCLK_SPI123)
2469   {
2470     /* Get SPI1/2/3 clock source */
2471     srcclk = __HAL_RCC_GET_SPI123_SOURCE();
2472
2473     switch (srcclk)
2474     {
2475       case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */
2476       {
2477         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2478         {
2479           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2480           frequency = pll1_clocks.PLL1_Q_Frequency;
2481         }
2482         else
2483         {
2484           frequency = 0;
2485         }
2486         break;
2487       }
2488       case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */
2489       {
2490         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2491         {
2492           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2493           frequency = pll2_clocks.PLL2_P_Frequency;
2494         }
2495         else
2496         {
2497           frequency = 0;
2498         }
2499         break;
2500       }
2501
2502       case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */
2503       {
2504         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2505         {
2506           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2507           frequency = pll3_clocks.PLL3_P_Frequency;
2508         }
2509         else
2510         {
2511           frequency = 0;
2512         }
2513         break;
2514       }
2515
2516       case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */
2517       {
2518
2519         ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2520
2521         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2522         {
2523           /* In Case the CKPER Source is HSI */
2524           frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2525         }
2526
2527         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2528         {
2529           /* In Case the CKPER Source is CSI */
2530           frequency = CSI_VALUE;
2531         }
2532
2533         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2534         {
2535           /* In Case the CKPER Source is HSE */
2536           frequency = HSE_VALUE;
2537         }
2538
2539         else
2540         {
2541           /* In Case the CKPER is disabled*/
2542           frequency = 0;
2543         }
2544
2545         break;
2546       }
2547
2548       case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */
2549       {
2550         frequency = EXTERNAL_CLOCK_VALUE;
2551         break;
2552       }
2553       default :
2554       {
2555         frequency = 0;
2556         break;
2557       }
2558     }
2559   }
2560   else if (PeriphClk == RCC_PERIPHCLK_SPI45)
2561   {
2562     /* Get SPI45 clock source */
2563     srcclk = __HAL_RCC_GET_SPI45_SOURCE();
2564     switch (srcclk)
2565     {
2566       case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */
2567       {
2568         frequency = HAL_RCC_GetPCLK1Freq();
2569         break;
2570       }
2571       case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */
2572       {
2573         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2574         {
2575           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2576           frequency = pll2_clocks.PLL2_Q_Frequency;
2577         }
2578         else
2579         {
2580           frequency = 0;
2581         }
2582         break;
2583       }
2584       case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */
2585       {
2586         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2587         {
2588           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2589           frequency = pll3_clocks.PLL3_Q_Frequency;
2590         }
2591         else
2592         {
2593           frequency = 0;
2594         }
2595         break;
2596       }
2597       case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */
2598       {
2599         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2600         {
2601           frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2602         }
2603         else
2604         {
2605           frequency = 0;
2606         }
2607         break;
2608       }
2609       case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */
2610       {
2611         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
2612         {
2613           frequency = CSI_VALUE;
2614         }
2615         else
2616         {
2617           frequency = 0;
2618         }
2619         break;
2620       }
2621       case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */
2622       {
2623         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
2624         {
2625           frequency = HSE_VALUE;
2626         }
2627         else
2628         {
2629           frequency = 0;
2630         }
2631         break;
2632       }
2633       default :
2634       {
2635         frequency = 0;
2636         break;
2637       }
2638     }
2639   }
2640   else if (PeriphClk == RCC_PERIPHCLK_ADC)
2641   {
2642     /* Get ADC clock source */
2643     srcclk = __HAL_RCC_GET_ADC_SOURCE();
2644
2645     switch (srcclk)
2646     {
2647       case RCC_ADCCLKSOURCE_PLL2:
2648       {
2649         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2650         {
2651           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2652           frequency = pll2_clocks.PLL2_P_Frequency;
2653         }
2654         else
2655         {
2656           frequency = 0;
2657         }
2658         break;
2659       }
2660       case RCC_ADCCLKSOURCE_PLL3:
2661       {
2662         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2663         {
2664           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2665           frequency = pll3_clocks.PLL3_R_Frequency;
2666         }
2667         else
2668         {
2669           frequency = 0;
2670         }
2671         break;
2672       }
2673
2674       case RCC_ADCCLKSOURCE_CLKP:
2675       {
2676
2677         ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2678
2679         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2680         {
2681           /* In Case the CKPER Source is HSI */
2682           frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2683         }
2684
2685         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2686         {
2687           /* In Case the CKPER Source is CSI */
2688           frequency = CSI_VALUE;
2689         }
2690
2691         else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2692         {
2693           /* In Case the CKPER Source is HSE */
2694           frequency = HSE_VALUE;
2695         }
2696
2697         else
2698         {
2699           /* In Case the CKPER is disabled*/
2700           frequency = 0;
2701         }
2702
2703         break;
2704       }
2705
2706       default :
2707       {
2708         frequency = 0;
2709         break;
2710       }
2711     }
2712   }
2713   else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
2714   {
2715     /* Get SDMMC clock source */
2716     srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
2717
2718     switch (srcclk)
2719     {
2720       case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
2721       {
2722         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2723         {
2724           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2725           frequency = pll1_clocks.PLL1_Q_Frequency;
2726         }
2727         else
2728         {
2729           frequency = 0;
2730         }
2731         break;
2732       }
2733       case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
2734       {
2735         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2736         {
2737           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2738           frequency = pll2_clocks.PLL2_R_Frequency;
2739         }
2740         else
2741         {
2742           frequency = 0;
2743         }
2744         break;
2745       }
2746
2747       default :
2748       {
2749         frequency = 0;
2750         break;
2751       }
2752     }
2753   }
2754   else if (PeriphClk == RCC_PERIPHCLK_SPI6)
2755   {
2756     /* Get SPI6 clock source */
2757     srcclk = __HAL_RCC_GET_SPI6_SOURCE();
2758
2759     switch (srcclk)
2760     {
2761       case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
2762       {
2763         frequency = HAL_RCCEx_GetD3PCLK1Freq();
2764         break;
2765       }
2766       case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
2767       {
2768         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2769         {
2770           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2771           frequency = pll2_clocks.PLL2_Q_Frequency;
2772         }
2773         else
2774         {
2775           frequency = 0;
2776         }
2777         break;
2778       }
2779       case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
2780       {
2781         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2782         {
2783           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2784           frequency = pll3_clocks.PLL3_Q_Frequency;
2785         }
2786         else
2787         {
2788           frequency = 0;
2789         }
2790         break;
2791       }
2792       case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
2793       {
2794         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2795         {
2796           frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2797         }
2798         else
2799         {
2800           frequency = 0;
2801         }
2802         break;
2803       }
2804       case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
2805       {
2806         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
2807         {
2808           frequency = CSI_VALUE;
2809         }
2810         else
2811         {
2812           frequency = 0;
2813         }
2814         break;
2815       }
2816       case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
2817       {
2818         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
2819         {
2820           frequency = HSE_VALUE;
2821         }
2822         else
2823         {
2824           frequency = 0;
2825         }
2826         break;
2827       }
2828 #if defined(RCC_SPI6CLKSOURCE_PIN)
2829       case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */
2830       {
2831         frequency = EXTERNAL_CLOCK_VALUE;
2832         break;
2833       }
2834 #endif /* RCC_SPI6CLKSOURCE_PIN */
2835       default :
2836       {
2837         frequency = 0;
2838         break;
2839       }
2840     }
2841   }
2842   else if (PeriphClk == RCC_PERIPHCLK_FDCAN)
2843   {
2844     /* Get FDCAN clock source */
2845     srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
2846
2847     switch (srcclk)
2848     {
2849       case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */
2850       {
2851         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
2852         {
2853           frequency = HSE_VALUE;
2854         }
2855         else
2856         {
2857           frequency = 0;
2858         }
2859         break;
2860       }
2861       case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */
2862       {
2863         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2864         {
2865           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2866           frequency = pll1_clocks.PLL1_Q_Frequency;
2867         }
2868         else
2869         {
2870           frequency = 0;
2871         }
2872         break;
2873       }
2874       case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */
2875       {
2876         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2877         {
2878           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2879           frequency = pll2_clocks.PLL2_Q_Frequency;
2880         }
2881         else
2882         {
2883           frequency = 0;
2884         }
2885         break;
2886       }
2887       default :
2888       {
2889         frequency = 0;
2890         break;
2891       }
2892     }
2893   }
2894   else
2895   {
2896     frequency = 0;
2897   }
2898
2899   return frequency;
2900 }
2901
2902
2903 /**
2904   * @brief  Returns the D1PCLK1 frequency
2905   * @note   Each time D1PCLK1 changes, this function must be called to update the
2906   *         right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
2907   * @retval D1PCLK1 frequency
2908   */
2909 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
2910 {
2911 #if defined(RCC_D1CFGR_D1PPRE)
2912   /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
2913   return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU));
2914 #else
2915   /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
2916   return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU));
2917 #endif
2918 }
2919
2920 /**
2921   * @brief  Returns the D3PCLK1 frequency
2922   * @note   Each time D3PCLK1 changes, this function must be called to update the
2923   *         right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
2924   * @retval D3PCLK1 frequency
2925   */
2926 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
2927 {
2928 #if defined(RCC_D3CFGR_D3PPRE)
2929   /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
2930   return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
2931 #else
2932   /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
2933   return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
2934 #endif
2935 }
2936 /**
2937 * @brief  Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
2938   * @note   The PLL2 clock frequencies computed by this function is not the real
2939   *         frequency in the chip. It is calculated based on the predefined
2940   *         constant and the selected clock source:
2941   * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
2942   * @note   This function can be used by the user application to compute the
2943   *         baud-rate for the communication peripherals or configure other parameters.
2944   *
2945   * @note   Each time PLL2CLK changes, this function must be called to update the
2946   *         right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
2947   * @param  PLL2_Clocks structure.
2948   * @retval None
2949   */
2950 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
2951 {
2952   uint32_t  pllsource, pll2m,  pll2fracen, hsivalue;
2953   float_t fracn2, pll2vco;
2954
2955   /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
2956      PLL2xCLK = PLL2_VCO / PLL2x
2957   */
2958   pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
2959   pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12);
2960   pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
2961   fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
2962
2963   if (pll2m != 0U)
2964   {
2965     switch (pllsource)
2966     {
2967
2968       case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
2969
2970         if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
2971         {
2972           hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2973           pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
2974         }
2975         else
2976         {
2977           pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
2978         }
2979         break;
2980
2981       case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
2982         pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
2983         break;
2984
2985       case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
2986         pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
2987         break;
2988
2989       default:
2990         pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
2991         break;
2992     }
2993     PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9)  + (float_t)1)) ;
2994     PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ;
2995     PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ;
2996   }
2997   else
2998   {
2999     PLL2_Clocks->PLL2_P_Frequency = 0U;
3000     PLL2_Clocks->PLL2_Q_Frequency = 0U;
3001     PLL2_Clocks->PLL2_R_Frequency = 0U;
3002   }
3003 }
3004
3005 /**
3006 * @brief  Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
3007   * @note   The PLL3 clock frequencies computed by this function is not the real
3008   *         frequency in the chip. It is calculated based on the predefined
3009   *         constant and the selected clock source:
3010   * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
3011   * @note   This function can be used by the user application to compute the
3012   *         baud-rate for the communication peripherals or configure other parameters.
3013   *
3014   * @note   Each time PLL3CLK changes, this function must be called to update the
3015   *         right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
3016   * @param  PLL3_Clocks structure.
3017   * @retval None
3018   */
3019 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
3020 {
3021   uint32_t pllsource, pll3m, pll3fracen, hsivalue;
3022   float_t fracn3, pll3vco;
3023
3024   /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
3025      PLL3xCLK = PLL3_VCO / PLLxR
3026   */
3027   pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
3028   pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20)  ;
3029   pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
3030   fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
3031
3032   if (pll3m != 0U)
3033   {
3034     switch (pllsource)
3035     {
3036       case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
3037
3038         if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
3039         {
3040           hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
3041           pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
3042         }
3043         else
3044         {
3045           pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
3046         }
3047         break;
3048       case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
3049         pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
3050         break;
3051
3052       case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
3053         pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
3054         break;
3055
3056       default:
3057         pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
3058         break;
3059     }
3060     PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9)  + (float_t)1)) ;
3061     PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ;
3062     PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ;
3063   }
3064   else
3065   {
3066     PLL3_Clocks->PLL3_P_Frequency = 0U;
3067     PLL3_Clocks->PLL3_Q_Frequency = 0U;
3068     PLL3_Clocks->PLL3_R_Frequency = 0U;
3069   }
3070
3071 }
3072
3073 /**
3074 * @brief  Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
3075   * @note   The PLL1 clock frequencies computed by this function is not the real
3076   *         frequency in the chip. It is calculated based on the predefined
3077   *         constant and the selected clock source:
3078   * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
3079   * @note   This function can be used by the user application to compute the
3080   *         baud-rate for the communication peripherals or configure other parameters.
3081   *
3082   * @note   Each time PLL1CLK changes, this function must be called to update the
3083   *         right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
3084   * @param  PLL1_Clocks structure.
3085   * @retval None
3086   */
3087 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
3088 {
3089   uint32_t pllsource, pll1m, pll1fracen, hsivalue;
3090   float_t fracn1, pll1vco;
3091
3092   pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
3093   pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
3094   pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
3095   fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
3096
3097   if (pll1m != 0U)
3098   {
3099     switch (pllsource)
3100     {
3101
3102       case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
3103
3104         if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
3105         {
3106           hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
3107           pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
3108         }
3109         else
3110         {
3111           pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
3112         }
3113         break;
3114       case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
3115         pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
3116         break;
3117
3118       case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
3119         pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
3120         break;
3121
3122       default:
3123         pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
3124         break;
3125     }
3126
3127     PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9)  + (float_t)1)) ;
3128     PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ;
3129     PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ;
3130   }
3131   else
3132   {
3133     PLL1_Clocks->PLL1_P_Frequency = 0U;
3134     PLL1_Clocks->PLL1_Q_Frequency = 0U;
3135     PLL1_Clocks->PLL1_R_Frequency = 0U;
3136   }
3137
3138 }
3139
3140 /**
3141   * @brief  Returns the main System frequency
3142   * @note   Each time System clock changes, this function must be called to update the
3143   *         right core clock value. Otherwise, any configuration based on this function will be incorrect.
3144   * @note   The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency
3145   *         and updated within this function
3146   * @retval HCLK frequency
3147   */
3148 uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
3149 {
3150   uint32_t common_system_clock;
3151
3152 #if defined(RCC_D1CFGR_D1CPRE)
3153   common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
3154 #else
3155   common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
3156 #endif
3157
3158   /* Update the SystemD2Clock global variable */
3159 #if defined(RCC_D1CFGR_HPRE)
3160   SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
3161 #else
3162   SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
3163 #endif
3164
3165 #if defined(DUAL_CORE) && defined(CORE_CM4)
3166   SystemCoreClock = SystemD2Clock;
3167 #else
3168   SystemCoreClock = common_system_clock;
3169 #endif /* DUAL_CORE && CORE_CM4 */
3170
3171   return common_system_clock;
3172 }
3173 /**
3174   * @}
3175   */
3176
3177 /** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions
3178   * @ingroup RTEMSBSPsARMSTM32H7
3179  *  @brief  Extended Peripheral Control functions
3180   * @{
3181   */
3182 /**
3183   * @brief  Enables the LSE Clock Security System.
3184   * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
3185   *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
3186   *         clock with HAL_RCCEx_PeriphCLKConfig().
3187   * @retval None
3188   */
3189 void HAL_RCCEx_EnableLSECSS(void)
3190 {
3191   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
3192 }
3193
3194 /**
3195   * @brief  Disables the LSE Clock Security System.
3196   * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
3197   * @retval None
3198   */
3199 void HAL_RCCEx_DisableLSECSS(void)
3200 {
3201   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
3202   /* Disable LSE CSS IT if any */
3203   __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
3204 }
3205
3206 /**
3207   * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
3208   * @note   LSE Clock Security System Interrupt is mapped on EXTI line 18
3209   * @retval None
3210   */
3211 void HAL_RCCEx_EnableLSECSS_IT(void)
3212 {
3213   /* Enable LSE CSS */
3214   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
3215
3216   /* Enable LSE CSS IT */
3217   __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
3218
3219   /* Enable IT on EXTI Line 18 */
3220 #if defined(DUAL_CORE) && defined(CORE_CM4)
3221   __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT();
3222 #else
3223   __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
3224 #endif /* DUAL_CORE && CORE_CM4 */
3225   __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
3226 }
3227
3228 /**
3229   * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock
3230   * @param  WakeUpClk: Wakeup clock
3231   *         This parameter can be one of the following values:
3232   *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
3233   *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
3234   * @note   This function shall not be called after the Clock Security System on HSE has been
3235   *         enabled.
3236   * @retval None
3237   */
3238 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
3239 {
3240   assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
3241
3242   __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
3243 }
3244
3245 /**
3246   * @brief  Configure the oscillator Kernel clock source for wakeup from Stop
3247   * @param  WakeUpClk: Kernel Wakeup clock
3248   *         This parameter can be one of the following values:
3249   *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
3250   *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
3251   * @retval None
3252   */
3253 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
3254 {
3255   assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
3256
3257   __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
3258 }
3259
3260 #if defined(DUAL_CORE)
3261 /**
3262   * @brief  Enable COREx boot independently of CMx_B option byte value
3263   * @param  RCC_BootCx: Boot Core to be enabled
3264   *         This parameter can be one of the following values:
3265   *            @arg RCC_BOOT_C1: CM7 core selection
3266   *            @arg RCC_BOOT_C2: CM4 core selection
3267   * @note   This bit can be set by software but is cleared by hardware after a system reset or STANDBY
3268   *
3269   * @retval None
3270   */
3271 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
3272 {
3273   assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
3274   SET_BIT(RCC->GCR, RCC_BootCx) ;
3275 }
3276
3277 #endif /*DUAL_CORE*/
3278
3279 #if defined(DUAL_CORE)
3280 /**
3281   * @brief  Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs
3282   * @param  RCC_WWDGx: WWDGx to be configured
3283   *         This parameter can be one of the following values:
3284   *            @arg RCC_WWDG1: WWDG1 generates system reset
3285   *            @arg RCC_WWDG2: WWDG2 generates system reset
3286   * @note   This bit can be set by software but is cleared by hardware during a system reset
3287   *
3288   * @retval None
3289   */
3290 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
3291 {
3292   assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
3293   SET_BIT(RCC->GCR, RCC_WWDGx) ;
3294 }
3295
3296 #else
3297 #if defined(RCC_GCR_WW1RSC)
3298 /**
3299   * @brief  Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs
3300   * @param  RCC_WWDGx: WWDGx to be configured
3301   *         This parameter can be one of the following values:
3302   *            @arg RCC_WWDG1: WWDG1 generates system reset
3303   * @note   This bit can be set by software but is cleared by hardware during a system reset
3304   *
3305   * @retval None
3306   */
3307 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
3308 {
3309   assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
3310   SET_BIT(RCC->GCR, RCC_WWDGx) ;
3311 }
3312 #endif
3313 #endif /*DUAL_CORE*/
3314
3315 /**
3316   * @}
3317   */
3318
3319 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
3320   * @ingroup RTEMSBSPsARMSTM32H7
3321  *  @brief  Extended Clock Recovery System Control functions
3322  *
3323 @verbatim
3324  ===============================================================================
3325                 ##### Extended Clock Recovery System Control functions  #####
3326  ===============================================================================
3327     [..]
3328       For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
3329
3330       (#) In System clock config, HSI48 needs to be enabled
3331
3332       (#) Enable CRS clock in IP MSP init which will use CRS functions
3333
3334       (#) Call CRS functions as follows:
3335           (##) Prepare synchronization configuration necessary for HSI48 calibration
3336               (+++) Default values can be set for frequency Error Measurement (reload and error limit)
3337                         and also HSI48 oscillator smooth trimming.
3338               (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
3339                         directly reload value with target and synchronization frequencies values
3340           (##) Call function HAL_RCCEx_CRSConfig which
3341               (+++) Resets CRS registers to their default values.
3342               (+++) Configures CRS registers with synchronization configuration
3343               (+++) Enables automatic calibration and frequency error counter feature
3344            Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
3345            periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
3346            provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
3347            precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
3348            should be used as SYNC signal.
3349
3350           (##) A polling function is provided to wait for complete synchronization
3351               (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
3352               (+++) According to CRS status, user can decide to adjust again the calibration or continue
3353                         application if synchronization is OK
3354
3355       (#) User can retrieve information related to synchronization in calling function
3356             HAL_RCCEx_CRSGetSynchronizationInfo()
3357
3358       (#) Regarding synchronization status and synchronization information, user can try a new calibration
3359            in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
3360            Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value),
3361            it means that the actual frequency is lower than the target (and so, that the TRIM value should be
3362            incremented), while when it is detected during the up-counting phase it means that the actual frequency
3363            is higher (and that the TRIM value should be decremented).
3364
3365       (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
3366           through CRS Handler (CRS_IRQn/CRS_IRQHandler)
3367               (++) Call function HAL_RCCEx_CRSConfig()
3368               (++) Enable CRS_IRQn (thanks to NVIC functions)
3369               (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
3370               (++) Implement CRS status management in the following user callbacks called from
3371                    HAL_RCCEx_CRS_IRQHandler():
3372                    (+++) HAL_RCCEx_CRS_SyncOkCallback()
3373                    (+++) HAL_RCCEx_CRS_SyncWarnCallback()
3374                    (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
3375                    (+++) HAL_RCCEx_CRS_ErrorCallback()
3376
3377       (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
3378           This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
3379
3380 @endverbatim
3381  * @{
3382  */
3383
3384 /**
3385   * @brief  Start automatic synchronization for polling mode
3386   * @param  pInit Pointer on RCC_CRSInitTypeDef structure
3387   * @retval None
3388   */
3389 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
3390 {
3391   uint32_t value;
3392
3393   /* Check the parameters */
3394   assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
3395   assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
3396   assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
3397   assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
3398   assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
3399   assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
3400
3401   /* CONFIGURATION */
3402
3403   /* Before configuration, reset CRS registers to their default values*/
3404   __HAL_RCC_CRS_FORCE_RESET();
3405   __HAL_RCC_CRS_RELEASE_RESET();
3406
3407   /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */
3408   /* Set the SYNCSRC[1:0] bits according to Source value */
3409   /* Set the SYNCSPOL bit according to Polarity value */
3410   if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2))
3411   {
3412     /* Use Rev.Y value of USB2 */
3413     value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity);
3414   }
3415   else
3416   {
3417     value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
3418   }
3419   /* Set the RELOAD[15:0] bits according to ReloadValue value */
3420   value |= pInit->ReloadValue;
3421   /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
3422   value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
3423   WRITE_REG(CRS->CFGR, value);
3424
3425   /* Adjust HSI48 oscillator smooth trimming */
3426   /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
3427   MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
3428
3429   /* START AUTOMATIC SYNCHRONIZATION*/
3430
3431   /* Enable Automatic trimming & Frequency error counter */
3432   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
3433 }
3434
3435 /**
3436   * @brief  Generate the software synchronization event
3437   * @retval None
3438   */
3439 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
3440 {
3441   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
3442 }
3443
3444 /**
3445   * @brief  Return synchronization info
3446   * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
3447   * @retval None
3448   */
3449 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
3450 {
3451   /* Check the parameter */
3452   assert_param(pSynchroInfo != (void *)NULL);
3453
3454   /* Get the reload value */
3455   pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
3456
3457   /* Get HSI48 oscillator smooth trimming */
3458   pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
3459
3460   /* Get Frequency error capture */
3461   pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
3462
3463   /* Get Frequency error direction */
3464   pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
3465 }
3466
3467 /**
3468 * @brief Wait for CRS Synchronization status.
3469 * @param Timeout  Duration of the time-out
3470 * @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
3471 *        frequency.
3472 * @note    If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
3473 * @retval Combination of Synchronization status
3474 *          This parameter can be a combination of the following values:
3475 *            @arg @ref RCC_CRS_TIMEOUT
3476 *            @arg @ref RCC_CRS_SYNCOK
3477 *            @arg @ref RCC_CRS_SYNCWARN
3478 *            @arg @ref RCC_CRS_SYNCERR
3479 *            @arg @ref RCC_CRS_SYNCMISS
3480 *            @arg @ref RCC_CRS_TRIMOVF
3481 */
3482 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
3483 {
3484   uint32_t crsstatus = RCC_CRS_NONE;
3485   uint32_t tickstart;
3486
3487   /* Get time-out */
3488   tickstart = HAL_GetTick();
3489
3490   /* Wait for CRS flag or time-out detection */
3491   do
3492   {
3493     if (Timeout != HAL_MAX_DELAY)
3494     {
3495       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3496       {
3497         crsstatus = RCC_CRS_TIMEOUT;
3498       }
3499     }
3500     /* Check CRS SYNCOK flag  */
3501     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
3502     {
3503       /* CRS SYNC event OK */
3504       crsstatus |= RCC_CRS_SYNCOK;
3505
3506       /* Clear CRS SYNC event OK bit */
3507       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
3508     }
3509
3510     /* Check CRS SYNCWARN flag  */
3511     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
3512     {
3513       /* CRS SYNC warning */
3514       crsstatus |= RCC_CRS_SYNCWARN;
3515
3516       /* Clear CRS SYNCWARN bit */
3517       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
3518     }
3519
3520     /* Check CRS TRIM overflow flag  */
3521     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
3522     {
3523       /* CRS SYNC Error */
3524       crsstatus |= RCC_CRS_TRIMOVF;
3525
3526       /* Clear CRS Error bit */
3527       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
3528     }
3529
3530     /* Check CRS Error flag  */
3531     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
3532     {
3533       /* CRS SYNC Error */
3534       crsstatus |= RCC_CRS_SYNCERR;
3535
3536       /* Clear CRS Error bit */
3537       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
3538     }
3539
3540     /* Check CRS SYNC Missed flag  */
3541     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
3542     {
3543       /* CRS SYNC Missed */
3544       crsstatus |= RCC_CRS_SYNCMISS;
3545
3546       /* Clear CRS SYNC Missed bit */
3547       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
3548     }
3549
3550     /* Check CRS Expected SYNC flag  */
3551     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
3552     {
3553       /* frequency error counter reached a zero value */
3554       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
3555     }
3556   }
3557   while (RCC_CRS_NONE == crsstatus);
3558
3559   return crsstatus;
3560 }
3561
3562 /**
3563   * @brief Handle the Clock Recovery System interrupt request.
3564   * @retval None
3565   */
3566 void HAL_RCCEx_CRS_IRQHandler(void)
3567 {
3568   uint32_t crserror = RCC_CRS_NONE;
3569   /* Get current IT flags and IT sources values */
3570   uint32_t itflags = READ_REG(CRS->ISR);
3571   uint32_t itsources = READ_REG(CRS->CR);
3572
3573   /* Check CRS SYNCOK flag  */
3574   if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
3575   {
3576     /* Clear CRS SYNC event OK flag */
3577     WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
3578
3579     /* user callback */
3580     HAL_RCCEx_CRS_SyncOkCallback();
3581   }
3582   /* Check CRS SYNCWARN flag  */
3583   else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
3584   {
3585     /* Clear CRS SYNCWARN flag */
3586     WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
3587
3588     /* user callback */
3589     HAL_RCCEx_CRS_SyncWarnCallback();
3590   }
3591   /* Check CRS Expected SYNC flag  */
3592   else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
3593   {
3594     /* frequency error counter reached a zero value */
3595     WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
3596
3597     /* user callback */
3598     HAL_RCCEx_CRS_ExpectedSyncCallback();
3599   }
3600   /* Check CRS Error flags  */
3601   else
3602   {
3603     if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
3604     {
3605       if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
3606       {
3607         crserror |= RCC_CRS_SYNCERR;
3608       }
3609       if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
3610       {
3611         crserror |= RCC_CRS_SYNCMISS;
3612       }
3613       if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
3614       {
3615         crserror |= RCC_CRS_TRIMOVF;
3616       }
3617
3618       /* Clear CRS Error flags */
3619       WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
3620
3621       /* user error callback */
3622       HAL_RCCEx_CRS_ErrorCallback(crserror);
3623     }
3624   }
3625 }
3626
3627 /**
3628   * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
3629   * @retval none
3630   */
3631 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
3632 {
3633   /* NOTE : This function should not be modified, when the callback is needed,
3634             the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
3635    */
3636 }
3637
3638 /**
3639   * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
3640   * @retval none
3641   */
3642 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
3643 {
3644   /* NOTE : This function should not be modified, when the callback is needed,
3645             the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
3646    */
3647 }
3648
3649 /**
3650   * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
3651   * @retval none
3652   */
3653 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
3654 {
3655   /* NOTE : This function should not be modified, when the callback is needed,
3656             the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
3657    */
3658 }
3659
3660 /**
3661   * @brief  RCCEx Clock Recovery System Error interrupt callback.
3662   * @param  Error Combination of Error status.
3663   *         This parameter can be a combination of the following values:
3664   *           @arg @ref RCC_CRS_SYNCERR
3665   *           @arg @ref RCC_CRS_SYNCMISS
3666   *           @arg @ref RCC_CRS_TRIMOVF
3667   * @retval none
3668   */
3669 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
3670 {
3671   /* Prevent unused argument(s) compilation warning */
3672   UNUSED(Error);
3673
3674   /* NOTE : This function should not be modified, when the callback is needed,
3675             the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
3676    */
3677 }
3678
3679
3680 /**
3681   * @}
3682   */
3683
3684 /**
3685   * @}
3686   */
3687
3688 /** @defgroup RCCEx_Private_functions RCCEx Private Functions
3689   * @ingroup RTEMSBSPsARMSTM32H7
3690  * @{
3691  */
3692 /**
3693   * @brief  Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it
3694   * @param  pll2: Pointer to an RCC_PLL2InitTypeDef structure that
3695   *         contains the configuration parameters  as well as VCI, VCO clock ranges.
3696   * @param  Divider  divider parameter to be updated
3697   * @note   PLL2 is temporary disabled to apply new parameters
3698   *
3699   * @retval HAL status
3700   */
3701 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
3702 {
3703
3704   uint32_t tickstart;
3705   HAL_StatusTypeDef status = HAL_OK;
3706   assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M));
3707   assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N));
3708   assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P));
3709   assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R));
3710   assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q));
3711   assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
3712   assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
3713   assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
3714
3715   /* Check that PLL2 OSC clock source is already set */
3716   if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
3717   {
3718     return HAL_ERROR;
3719   }
3720
3721
3722   else
3723   {
3724     /* Disable  PLL2. */
3725     __HAL_RCC_PLL2_DISABLE();
3726
3727     /* Get Start Tick*/
3728     tickstart = HAL_GetTick();
3729
3730     /* Wait till PLL is disabled */
3731     while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
3732     {
3733       if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
3734       {
3735         return HAL_TIMEOUT;
3736       }
3737     }
3738
3739     /* Configure PLL2 multiplication and division factors. */
3740     __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
3741                           pll2->PLL2N,
3742                           pll2->PLL2P,
3743                           pll2->PLL2Q,
3744                           pll2->PLL2R);
3745
3746     /* Select PLL2 input reference frequency range: VCI */
3747     __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
3748
3749     /* Select PLL2 output frequency range : VCO */
3750     __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
3751
3752     /* Disable PLL2FRACN . */
3753     __HAL_RCC_PLL2FRACN_DISABLE();
3754
3755     /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
3756     __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
3757
3758     /* Enable PLL2FRACN . */
3759     __HAL_RCC_PLL2FRACN_ENABLE();
3760
3761     /* Enable the PLL2 clock output */
3762     if (Divider == DIVIDER_P_UPDATE)
3763     {
3764       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
3765     }
3766     else if (Divider == DIVIDER_Q_UPDATE)
3767     {
3768       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
3769     }
3770     else
3771     {
3772       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
3773     }
3774
3775     /* Enable  PLL2. */
3776     __HAL_RCC_PLL2_ENABLE();
3777
3778     /* Get Start Tick*/
3779     tickstart = HAL_GetTick();
3780
3781     /* Wait till PLL2 is ready */
3782     while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
3783     {
3784       if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
3785       {
3786         return HAL_TIMEOUT;
3787       }
3788     }
3789
3790   }
3791
3792
3793   return status;
3794 }
3795
3796
3797 /**
3798   * @brief  Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it
3799   * @param  pll3: Pointer to an RCC_PLL3InitTypeDef structure that
3800   *         contains the configuration parameters  as well as VCI, VCO clock ranges.
3801   * @param  Divider  divider parameter to be updated
3802   * @note   PLL3 is temporary disabled to apply new parameters
3803   *
3804   * @retval HAL status
3805   */
3806 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
3807 {
3808   uint32_t tickstart;
3809   HAL_StatusTypeDef status = HAL_OK;
3810   assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M));
3811   assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N));
3812   assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P));
3813   assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R));
3814   assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q));
3815   assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
3816   assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
3817   assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
3818
3819   /* Check that PLL3 OSC clock source is already set */
3820   if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
3821   {
3822     return HAL_ERROR;
3823   }
3824
3825
3826   else
3827   {
3828     /* Disable  PLL3. */
3829     __HAL_RCC_PLL3_DISABLE();
3830
3831     /* Get Start Tick*/
3832     tickstart = HAL_GetTick();
3833     /* Wait till PLL3 is ready */
3834     while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
3835     {
3836       if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
3837       {
3838         return HAL_TIMEOUT;
3839       }
3840     }
3841
3842     /* Configure the PLL3  multiplication and division factors. */
3843     __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
3844                           pll3->PLL3N,
3845                           pll3->PLL3P,
3846                           pll3->PLL3Q,
3847                           pll3->PLL3R);
3848
3849     /* Select PLL3 input reference frequency range: VCI */
3850     __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
3851
3852     /* Select PLL3 output frequency range : VCO */
3853     __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
3854
3855     /* Disable PLL3FRACN . */
3856     __HAL_RCC_PLL3FRACN_DISABLE();
3857
3858     /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
3859     __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
3860
3861     /* Enable PLL3FRACN . */
3862     __HAL_RCC_PLL3FRACN_ENABLE();
3863
3864     /* Enable the PLL3 clock output */
3865     if (Divider == DIVIDER_P_UPDATE)
3866     {
3867       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
3868     }
3869     else if (Divider == DIVIDER_Q_UPDATE)
3870     {
3871       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
3872     }
3873     else
3874     {
3875       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
3876     }
3877
3878     /* Enable  PLL3. */
3879     __HAL_RCC_PLL3_ENABLE();
3880
3881     /* Get Start Tick*/
3882     tickstart = HAL_GetTick();
3883
3884     /* Wait till PLL3 is ready */
3885     while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
3886     {
3887       if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
3888       {
3889         return HAL_TIMEOUT;
3890       }
3891     }
3892
3893   }
3894
3895
3896   return status;
3897 }
3898
3899 /**
3900   * @brief Handle the RCC LSE Clock Security System interrupt request.
3901   * @retval None
3902   */
3903 void HAL_RCCEx_LSECSS_IRQHandler(void)
3904 {
3905   /* Check RCC LSE CSSF flag  */
3906   if (__HAL_RCC_GET_IT(RCC_IT_LSECSS))
3907   {
3908
3909     /* Clear RCC LSE CSS pending bit */
3910     __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
3911
3912     /* RCC LSE Clock Security System interrupt user callback */
3913     HAL_RCCEx_LSECSS_Callback();
3914
3915   }
3916 }
3917
3918 /**
3919   * @brief  RCCEx LSE Clock Security System interrupt callback.
3920   * @retval none
3921   */
3922 __weak void HAL_RCCEx_LSECSS_Callback(void)
3923 {
3924   /* NOTE : This function should not be modified, when the callback is needed,
3925             the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
3926   */
3927 }
3928
3929
3930
3931 /**
3932   * @}
3933   */
3934
3935 #endif /* HAL_RCC_MODULE_ENABLED */
3936 /**
3937   * @}
3938   */
3939
3940 /**
3941   * @}
3942   */
3943