stm32h7/hal/stm32h7xx_hal_rcc.c

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_rcc.c
0004   * @author  MCD Application Team
0005   * @brief   RCC HAL module driver.
0006   *          This file provides firmware functions to manage the following
0007   *          functionalities of the Reset and Clock Control (RCC) peripheral:
0008   *           + Initialization and de-initialization functions
0009   *           + Peripheral Control functions
0010   *
0011   @verbatim
0012   ==============================================================================
0013                       ##### RCC specific features #####
0014   ==============================================================================
0015     [..]
0016       After reset the device is running from Internal High Speed oscillator
0017       (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except
0018       internal SRAM, Flash, JTAG and PWR
0019       (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
0020           all peripherals mapped on these buses are running at HSI speed.
0021       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
0022       (+) All GPIOs are in analogue mode , except the JTAG pins which
0023           are assigned to be used for debug purpose.
0024
0025     [..]
0026       Once the device started from reset, the user application has to:
0027       (+) Configure the clock source to be used to drive the System clock
0028           (if the application needs higher frequency/performance)
0029       (+) Configure the System clock frequency and Flash settings
0030       (+) Configure the AHB and APB buses pre-scalers
0031       (+) Enable the clock for the peripheral(s) to be used
0032       (+) Configure the clock kernel source(s) for peripherals which clocks are not
0033           derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R
0034           and RCC_D3CCIPR registers
0035
0036                       ##### RCC Limitations #####
0037   ==============================================================================
0038     [..]
0039       A delay between an RCC peripheral clock enable and the effective peripheral
0040       enabling should be taken into account in order to manage the peripheral read/write
0041       from/to registers.
0042       (+) This delay depends on the peripheral mapping.
0043       (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
0044           after the clock enable bit is set on the hardware register
0045       (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
0046           after the clock enable bit is set on the hardware register
0047
0048     [..]
0049       Implemented Workaround:
0050       (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
0051           inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
0052
0053   @endverbatim
0054  ******************************************************************************
0055   * @attention
0056   *
0057   * Copyright (c) 2017 STMicroelectronics.
0058   * All rights reserved.
0059   *
0060   * This software is licensed under terms that can be found in the LICENSE file in
0061   * the root directory of this software component.
0062   * If no LICENSE file comes with this software, it is provided AS-IS.
0063   ******************************************************************************
0064   */
0065
0066 /* Includes ------------------------------------------------------------------*/
0067 #include "stm32h7xx_hal.h"
0068
0069 /** @addtogroup STM32H7xx_HAL_Driver
0070   * @{
0071   */
0072
0073 /** @defgroup RCC  RCC
0074   * @ingroup RTEMSBSPsARMSTM32H7
0075   * @brief RCC HAL module driver
0076   * @{
0077   */
0078
0079 #ifdef HAL_RCC_MODULE_ENABLED
0080
0081 /* Private typedef -----------------------------------------------------------*/
0082 /* Private define ------------------------------------------------------------*/
0083 /* Private macro -------------------------------------------------------------*/
0084 /** @defgroup RCC_Private_Macros RCC Private Macros
0085   * @ingroup RTEMSBSPsARMSTM32H7
0086   * @{
0087   */
0088 #define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
0089 #define MCO1_GPIO_PORT        GPIOA
0090 #define MCO1_PIN              GPIO_PIN_8
0091
0092 #define MCO2_CLK_ENABLE()      __HAL_RCC_GPIOC_CLK_ENABLE()
0093 #define MCO2_GPIO_PORT         GPIOC
0094 #define MCO2_PIN               GPIO_PIN_9
0095
0096 /**
0097   * @}
0098   */
0099 /* Private variables ---------------------------------------------------------*/
0100 /** @defgroup RCC_Private_Variables RCC Private Variables
0101   * @ingroup RTEMSBSPsARMSTM32H7
0102   * @{
0103   */
0104
0105 /**
0106   * @}
0107   */
0108 /* Private function prototypes -----------------------------------------------*/
0109 /* Exported functions --------------------------------------------------------*/
0110
0111 /** @defgroup RCC_Exported_Functions RCC Exported Functions
0112   * @ingroup RTEMSBSPsARMSTM32H7
0113   * @{
0114   */
0115
0116 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
0117   * @ingroup RTEMSBSPsARMSTM32H7
0118  *  @brief    Initialization and Configuration functions
0119  *
0120 @verbatim
0121  ===============================================================================
0122            ##### Initialization and de-initialization functions #####
0123  ===============================================================================
0124     [..]
0125       This section provides functions allowing to configure the internal/external oscillators
0126       (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1
0127        AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4).
0128
0129     [..] Internal/external clock and PLL configuration
0130          (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
0131              the PLL as System clock source.
0132          (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
0133              clock, or PLL input.But even with frequency calibration, is less accurate than an
0134              external crystal oscillator or ceramic resonator.
0135          (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
0136              clock source.
0137
0138          (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
0139              through the PLL as System clock source. Can be used also as RTC clock source.
0140
0141          (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
0142
0143          (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI),
0144              featuring three different output clocks and able  to work either in integer or Fractional mode.
0145            (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU
0146                 and to some peripherals.
0147            (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.
0148
0149
0150          (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
0151             (HSE used directly or through PLL as System clock source), the System clock
0152              is automatically switched to HSI and an interrupt is generated if enabled.
0153              The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt)
0154              exception vector.
0155
0156          (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q)
0157              or HSI48 clock (through a configurable pre-scaler) on PA8 pin.
0158
0159          (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK,
0160              LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin.
0161
0162     [..] System, AHB and APB buses clocks configuration
0163          (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI,
0164              HSE and PLL.
0165              The AHB clock (HCLK) is derived from System core clock through configurable
0166              pre-scaler and used to clock the CPU, memory and peripherals mapped
0167              on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers
0168              and used to clock the peripherals mapped on these buses. You can use
0169              "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.
0170
0171          -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those
0172              with dual clock domain where kernel source clock could be selected through
0173              RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers.
0174
0175      (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines.
0176 @endverbatim
0177   * @{
0178   */
0179
0180 #ifndef __rtems__
0181 /**
0182   * @brief  Resets the RCC clock configuration to the default reset state.
0183   * @note   The default reset state of the clock configuration is given below:
0184   *            - HSI ON and used as system clock source
0185   *            - HSE, PLL1, PLL2 and PLL3 OFF
0186   *            - AHB, APB Bus pre-scaler set to 1.
0187   *            - CSS, MCO1 and MCO2 OFF
0188   *            - All interrupts disabled
0189   * @note   This function doesn't modify the configuration of the
0190   *            - Peripheral clocks
0191   *            - LSI, LSE and RTC clocks
0192   * @retval HAL status
0193   */
0194 HAL_StatusTypeDef HAL_RCC_DeInit(void)
0195 {
0196   uint32_t tickstart;
0197
0198   /* Increasing the CPU frequency */
0199   if (FLASH_LATENCY_DEFAULT  > __HAL_FLASH_GET_LATENCY())
0200   {
0201     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
0202     __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
0203
0204     /* Check that the new number of wait states is taken into account to access the Flash
0205     memory by reading the FLASH_ACR register */
0206     if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
0207     {
0208       return HAL_ERROR;
0209     }
0210
0211   }
0212
0213
0214   /* Get Start Tick */
0215   tickstart = HAL_GetTick();
0216
0217   /* Set HSION bit */
0218   SET_BIT(RCC->CR, RCC_CR_HSION);
0219
0220   /* Wait till HSI is ready */
0221   while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
0222   {
0223     if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
0224     {
0225       return HAL_TIMEOUT;
0226     }
0227   }
0228
0229   /* Set HSITRIM[6:0] bits to the reset value */
0230   SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6);
0231
0232   /* Reset CFGR register */
0233   CLEAR_REG(RCC->CFGR);
0234
0235   /* Update the SystemCoreClock and SystemD2Clock global variables */
0236   SystemCoreClock = HSI_VALUE;
0237   SystemD2Clock = HSI_VALUE;
0238
0239   /* Adapt Systick interrupt period */
0240   if (HAL_InitTick(uwTickPrio) != HAL_OK)
0241   {
0242     return HAL_ERROR;
0243   }
0244
0245   /* Get Start Tick */
0246   tickstart = HAL_GetTick();
0247
0248   /* Wait till clock switch is ready */
0249   while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
0250   {
0251     if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
0252     {
0253       return HAL_TIMEOUT;
0254     }
0255   }
0256
0257   /* Get Start Tick */
0258   tickstart = HAL_GetTick();
0259
0260   /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */
0261   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON  \
0262             | RCC_CR_HSI48ON | RCC_CR_CSSHSEON);
0263
0264   /* Wait till HSE is disabled */
0265   while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
0266   {
0267     if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
0268     {
0269       return HAL_TIMEOUT;
0270     }
0271   }
0272
0273   /* Get Start Tick */
0274   tickstart = HAL_GetTick();
0275
0276   /* Clear PLLON bit */
0277   CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
0278
0279   /* Wait till PLL is disabled */
0280   while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
0281   {
0282     if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
0283     {
0284       return HAL_TIMEOUT;
0285     }
0286   }
0287
0288   /* Get Start Tick */
0289   tickstart = HAL_GetTick();
0290
0291   /* Reset PLL2ON bit */
0292   CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
0293
0294   /* Wait till PLL2 is disabled */
0295   while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
0296   {
0297     if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
0298     {
0299       return HAL_TIMEOUT;
0300     }
0301   }
0302
0303   /* Get Start Tick */
0304   tickstart = HAL_GetTick();
0305
0306   /* Reset PLL3 bit */
0307   CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
0308
0309   /* Wait till PLL3 is disabled */
0310   while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
0311   {
0312     if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
0313     {
0314       return HAL_TIMEOUT;
0315     }
0316   }
0317
0318 #if defined(RCC_D1CFGR_HPRE)
0319   /* Reset D1CFGR register */
0320   CLEAR_REG(RCC->D1CFGR);
0321
0322   /* Reset D2CFGR register */
0323   CLEAR_REG(RCC->D2CFGR);
0324
0325   /* Reset D3CFGR register */
0326   CLEAR_REG(RCC->D3CFGR);
0327 #else
0328   /* Reset CDCFGR1 register */
0329   CLEAR_REG(RCC->CDCFGR1);
0330
0331   /* Reset CDCFGR2 register */
0332   CLEAR_REG(RCC->CDCFGR2);
0333
0334   /* Reset SRDCFGR register */
0335   CLEAR_REG(RCC->SRDCFGR);
0336 #endif
0337
0338   /* Reset PLLCKSELR register to default value */
0339   RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM1_5 | RCC_PLLCKSELR_DIVM2_5 | RCC_PLLCKSELR_DIVM3_5;
0340
0341   /* Reset PLLCFGR register to default value */
0342   WRITE_REG(RCC->PLLCFGR, 0x01FF0000U);
0343
0344   /* Reset PLL1DIVR register to default value */
0345   WRITE_REG(RCC->PLL1DIVR, 0x01010280U);
0346
0347   /* Reset PLL1FRACR register */
0348   CLEAR_REG(RCC->PLL1FRACR);
0349
0350   /* Reset PLL2DIVR register to default value */
0351   WRITE_REG(RCC->PLL2DIVR, 0x01010280U);
0352
0353   /* Reset PLL2FRACR register */
0354   CLEAR_REG(RCC->PLL2FRACR);
0355
0356   /* Reset PLL3DIVR register to default value */
0357   WRITE_REG(RCC->PLL3DIVR, 0x01010280U);
0358
0359   /* Reset PLL3FRACR register */
0360   CLEAR_REG(RCC->PLL3FRACR);
0361
0362 #if defined(RCC_CR_HSEEXT)
0363   /* Reset HSEEXT  */
0364   CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
0365 #endif /* RCC_CR_HSEEXT */
0366
0367   /* Reset HSEBYP bit */
0368   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
0369
0370   /* Disable all interrupts */
0371   CLEAR_REG(RCC->CIER);
0372
0373   /* Clear all interrupts flags */
0374   WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
0375
0376   /* Reset all RSR flags */
0377   SET_BIT(RCC->RSR, RCC_RSR_RMVF);
0378
0379   /* Decreasing the number of wait states because of lower CPU frequency */
0380   if (FLASH_LATENCY_DEFAULT  < __HAL_FLASH_GET_LATENCY())
0381   {
0382     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
0383     __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
0384
0385     /* Check that the new number of wait states is taken into account to access the Flash
0386     memory by reading the FLASH_ACR register */
0387     if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
0388     {
0389       return HAL_ERROR;
0390     }
0391
0392   }
0393
0394   return HAL_OK;
0395 }
0396 #endif /* __rtems__ */
0397
0398 /**
0399   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
0400   *         RCC_OscInitTypeDef.
0401   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
0402   *         contains the configuration information for the RCC Oscillators.
0403   * @note   The PLL is not disabled when used as system clock.
0404   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
0405   *         supported by this function. User should request a transition to LSE Off
0406   *         first and then LSE On or LSE Bypass.
0407   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
0408   *         supported by this function. User should request a transition to HSE Off
0409   *         first and then HSE On or HSE Bypass.
0410   * @retval HAL status
0411   */
0412 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
0413 {
0414   uint32_t tickstart;
0415   uint32_t temp1_pllckcfg, temp2_pllckcfg;
0416
0417   /* Check Null pointer */
0418   if (RCC_OscInitStruct == NULL)
0419   {
0420     return HAL_ERROR;
0421   }
0422
0423   /* Check the parameters */
0424   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
0425   /*------------------------------- HSE Configuration ------------------------*/
0426   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
0427   {
0428     /* Check the parameters */
0429     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
0430
0431     const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
0432     const uint32_t temp_pllckselr = RCC->PLLCKSELR;
0433     /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
0434     if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
0435     {
0436       if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
0437       {
0438         return HAL_ERROR;
0439       }
0440     }
0441     else
0442     {
0443       /* Set the new HSE configuration ---------------------------------------*/
0444       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
0445
0446       /* Check the HSE State */
0447       if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
0448       {
0449         /* Get Start Tick*/
0450         tickstart = HAL_GetTick();
0451
0452         /* Wait till HSE is ready */
0453         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
0454         {
0455           if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
0456           {
0457             return HAL_TIMEOUT;
0458           }
0459         }
0460       }
0461       else
0462       {
0463         /* Get Start Tick*/
0464         tickstart = HAL_GetTick();
0465
0466         /* Wait till HSE is disabled */
0467         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
0468         {
0469           if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
0470           {
0471             return HAL_TIMEOUT;
0472           }
0473         }
0474       }
0475     }
0476   }
0477   /*----------------------------- HSI Configuration --------------------------*/
0478   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
0479   {
0480     /* Check the parameters */
0481     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
0482     assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
0483
0484     /* When the HSI is used as system clock it will not be disabled */
0485     const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
0486     const uint32_t temp_pllckselr = RCC->PLLCKSELR;
0487     if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
0488     {
0489       /* When HSI is used as system clock it will not be disabled */
0490       if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
0491       {
0492         return HAL_ERROR;
0493       }
0494       /* Otherwise, only HSI division and calibration are allowed */
0495       else
0496       {
0497         /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */
0498         __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
0499
0500         /* Get Start Tick*/
0501         tickstart = HAL_GetTick();
0502
0503         /* Wait till HSI is ready */
0504         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
0505         {
0506           if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
0507           {
0508             return HAL_TIMEOUT;
0509           }
0510         }
0511         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
0512         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
0513       }
0514     }
0515
0516     else
0517     {
0518       /* Check the HSI State */
0519       if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
0520       {
0521         /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
0522         __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
0523
0524         /* Get Start Tick*/
0525         tickstart = HAL_GetTick();
0526
0527         /* Wait till HSI is ready */
0528         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
0529         {
0530           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
0531           {
0532             return HAL_TIMEOUT;
0533           }
0534         }
0535
0536         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
0537         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
0538       }
0539       else
0540       {
0541         /* Disable the Internal High Speed oscillator (HSI). */
0542         __HAL_RCC_HSI_DISABLE();
0543
0544         /* Get Start Tick*/
0545         tickstart = HAL_GetTick();
0546
0547         /* Wait till HSI is disabled */
0548         while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
0549         {
0550           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
0551           {
0552             return HAL_TIMEOUT;
0553           }
0554         }
0555       }
0556     }
0557   }
0558   /*----------------------------- CSI Configuration --------------------------*/
0559   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
0560   {
0561     /* Check the parameters */
0562     assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
0563     assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
0564
0565     /* When the CSI is used as system clock it will not disabled */
0566     const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
0567     const uint32_t temp_pllckselr = RCC->PLLCKSELR;
0568     if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
0569     {
0570       /* When CSI is used as system clock it will not disabled */
0571       if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
0572       {
0573         return HAL_ERROR;
0574       }
0575       /* Otherwise, just the calibration is allowed */
0576       else
0577       {
0578         /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
0579         __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
0580       }
0581     }
0582     else
0583     {
0584       /* Check the CSI State */
0585       if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
0586       {
0587         /* Enable the Internal High Speed oscillator (CSI). */
0588         __HAL_RCC_CSI_ENABLE();
0589
0590         /* Get Start Tick*/
0591         tickstart = HAL_GetTick();
0592
0593         /* Wait till CSI is ready */
0594         while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
0595         {
0596           if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
0597           {
0598             return HAL_TIMEOUT;
0599           }
0600         }
0601
0602         /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
0603         __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
0604       }
0605       else
0606       {
0607         /* Disable the Internal High Speed oscillator (CSI). */
0608         __HAL_RCC_CSI_DISABLE();
0609
0610         /* Get Start Tick*/
0611         tickstart = HAL_GetTick();
0612
0613         /* Wait till CSI is disabled */
0614         while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
0615         {
0616           if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
0617           {
0618             return HAL_TIMEOUT;
0619           }
0620         }
0621       }
0622     }
0623   }
0624   /*------------------------------ LSI Configuration -------------------------*/
0625   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
0626   {
0627     /* Check the parameters */
0628     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
0629
0630     /* Check the LSI State */
0631     if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
0632     {
0633       /* Enable the Internal Low Speed oscillator (LSI). */
0634       __HAL_RCC_LSI_ENABLE();
0635
0636       /* Get Start Tick*/
0637       tickstart = HAL_GetTick();
0638
0639       /* Wait till LSI is ready */
0640       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
0641       {
0642         if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
0643         {
0644           return HAL_TIMEOUT;
0645         }
0646       }
0647     }
0648     else
0649     {
0650       /* Disable the Internal Low Speed oscillator (LSI). */
0651       __HAL_RCC_LSI_DISABLE();
0652
0653       /* Get Start Tick*/
0654       tickstart = HAL_GetTick();
0655
0656       /* Wait till LSI is ready */
0657       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
0658       {
0659         if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
0660         {
0661           return HAL_TIMEOUT;
0662         }
0663       }
0664     }
0665   }
0666
0667   /*------------------------------ HSI48 Configuration -------------------------*/
0668   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
0669   {
0670     /* Check the parameters */
0671     assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
0672
0673     /* Check the HSI48 State */
0674     if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF)
0675     {
0676       /* Enable the Internal Low Speed oscillator (HSI48). */
0677       __HAL_RCC_HSI48_ENABLE();
0678
0679       /* Get time-out */
0680       tickstart = HAL_GetTick();
0681
0682       /* Wait till HSI48 is ready */
0683       while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
0684       {
0685         if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
0686         {
0687           return HAL_TIMEOUT;
0688         }
0689       }
0690     }
0691     else
0692     {
0693       /* Disable the Internal Low Speed oscillator (HSI48). */
0694       __HAL_RCC_HSI48_DISABLE();
0695
0696       /* Get time-out */
0697       tickstart = HAL_GetTick();
0698
0699       /* Wait till HSI48 is ready */
0700       while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
0701       {
0702         if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
0703         {
0704           return HAL_TIMEOUT;
0705         }
0706       }
0707     }
0708   }
0709   /*------------------------------ LSE Configuration -------------------------*/
0710   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
0711   {
0712     /* Check the parameters */
0713     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
0714
0715     /* Enable write access to Backup domain */
0716     PWR->CR1 |= PWR_CR1_DBP;
0717
0718     /* Wait for Backup domain Write protection disable */
0719     tickstart = HAL_GetTick();
0720
0721     while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
0722     {
0723       if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
0724       {
0725         return HAL_TIMEOUT;
0726       }
0727     }
0728
0729     /* Set the new LSE configuration -----------------------------------------*/
0730     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
0731     /* Check the LSE State */
0732     if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
0733     {
0734       /* Get Start Tick*/
0735       tickstart = HAL_GetTick();
0736
0737       /* Wait till LSE is ready */
0738       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
0739       {
0740         if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
0741         {
0742           return HAL_TIMEOUT;
0743         }
0744       }
0745     }
0746     else
0747     {
0748       /* Get Start Tick*/
0749       tickstart = HAL_GetTick();
0750
0751       /* Wait till LSE is disabled */
0752       while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
0753       {
0754         if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
0755         {
0756           return HAL_TIMEOUT;
0757         }
0758       }
0759     }
0760   }
0761   /*-------------------------------- PLL Configuration -----------------------*/
0762   /* Check the parameters */
0763   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
0764   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
0765   {
0766     /* Check if the PLL is used as system clock or not */
0767     if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
0768     {
0769       if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
0770       {
0771         /* Check the parameters */
0772         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
0773         assert_param(IS_RCC_PLLRGE_VALUE(RCC_OscInitStruct->PLL.PLLRGE));
0774         assert_param(IS_RCC_PLLVCO_VALUE(RCC_OscInitStruct->PLL.PLLVCOSEL));
0775         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
0776         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
0777         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
0778         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
0779         assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
0780         assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
0781
0782         /* Disable the main PLL. */
0783         __HAL_RCC_PLL_DISABLE();
0784
0785         /* Get Start Tick*/
0786         tickstart = HAL_GetTick();
0787
0788         /* Wait till PLL is disabled */
0789         while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
0790         {
0791           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
0792           {
0793             return HAL_TIMEOUT;
0794           }
0795         }
0796
0797         /* Configure the main PLL clock source, multiplication and division factors. */
0798         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
0799                              RCC_OscInitStruct->PLL.PLLM,
0800                              RCC_OscInitStruct->PLL.PLLN,
0801                              RCC_OscInitStruct->PLL.PLLP,
0802                              RCC_OscInitStruct->PLL.PLLQ,
0803                              RCC_OscInitStruct->PLL.PLLR);
0804
0805         /* Disable PLLFRACN . */
0806         __HAL_RCC_PLLFRACN_DISABLE();
0807
0808         /* Configure PLL PLL1FRACN */
0809         __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
0810
0811         /* Select PLL1 input reference frequency range: VCI */
0812         __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
0813
0814         /* Select PLL1 output frequency range : VCO */
0815         __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
0816
0817         /* Enable PLL System Clock output. */
0818         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
0819
0820         /* Enable PLL1Q Clock output. */
0821         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
0822
0823         /* Enable PLL1R  Clock output. */
0824         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
0825
0826         /* Enable PLL1FRACN . */
0827         __HAL_RCC_PLLFRACN_ENABLE();
0828
0829         /* Enable the main PLL. */
0830         __HAL_RCC_PLL_ENABLE();
0831
0832         /* Get Start Tick*/
0833         tickstart = HAL_GetTick();
0834
0835         /* Wait till PLL is ready */
0836         while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
0837         {
0838           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
0839           {
0840             return HAL_TIMEOUT;
0841           }
0842         }
0843       }
0844       else
0845       {
0846         /* Disable the main PLL. */
0847         __HAL_RCC_PLL_DISABLE();
0848
0849         /* Get Start Tick*/
0850         tickstart = HAL_GetTick();
0851
0852         /* Wait till PLL is disabled */
0853         while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
0854         {
0855           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
0856           {
0857             return HAL_TIMEOUT;
0858           }
0859         }
0860       }
0861     }
0862     else
0863     {
0864       /* Do not return HAL_ERROR if request repeats the current configuration */
0865       temp1_pllckcfg = RCC->PLLCKSELR;
0866       temp2_pllckcfg = RCC->PLL1DIVR;
0867       if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
0868           (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
0869           ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
0870           (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
0871           ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
0872           ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
0873           ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
0874       {
0875         return HAL_ERROR;
0876       }
0877       else
0878       {
0879         /* Check if only fractional part needs to be updated  */
0880         temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
0881         if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg)
0882         {
0883           assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
0884           /* Disable PLL1FRACEN */
0885           __HAL_RCC_PLLFRACN_DISABLE();
0886           /* Get Start Tick*/
0887           tickstart = HAL_GetTick();
0888           /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */
0889           while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE)
0890           {
0891           }
0892           /* Configure PLL1 PLL1FRACN */
0893           __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
0894           /* Enable PLL1FRACEN to latch new value. */
0895           __HAL_RCC_PLLFRACN_ENABLE();
0896         }
0897       }
0898     }
0899   }
0900   return HAL_OK;
0901 }
0902
0903 /**
0904   * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
0905   *         parameters in the RCC_ClkInitStruct.
0906   * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
0907   *         contains the configuration information for the RCC peripheral.
0908   * @param  FLatency: FLASH Latency, this parameter depend on device selected
0909   *
0910   * @note   The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency
0911   *         and updated by HAL_InitTick() function called within this function
0912   *
0913   * @note   The HSI is used (enabled by hardware) as system clock source after
0914   *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
0915   *         of failure of the HSE used directly or indirectly as system clock
0916   *         (if the Clock Security System CSS is enabled).
0917   *
0918   * @note   A switch from one clock source to another occurs only if the target
0919   *         clock source is ready (clock stable after start-up delay or PLL locked).
0920   *         If a clock source which is not yet ready is selected, the switch will
0921   *         occur when the clock source will be ready.
0922   *         You can use HAL_RCC_GetClockConfig() function to know which clock is
0923   *         currently used as system clock source.
0924   * @note   Depending on the device voltage range, the software has to set correctly
0925   *         D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
0926   *         (for more details refer to section above "Initialization/de-initialization functions")
0927   * @retval None
0928   */
0929 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
0930 {
0931   HAL_StatusTypeDef halstatus;
0932   uint32_t tickstart;
0933   uint32_t common_system_clock;
0934
0935   /* Check Null pointer */
0936   if (RCC_ClkInitStruct == NULL)
0937   {
0938     return HAL_ERROR;
0939   }
0940
0941   /* Check the parameters */
0942   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
0943   assert_param(IS_FLASH_LATENCY(FLatency));
0944
0945   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
0946     must be correctly programmed according to the frequency of the CPU clock
0947     (HCLK) and the supply voltage of the device. */
0948
0949   /* Increasing the CPU frequency */
0950   if (FLatency > __HAL_FLASH_GET_LATENCY())
0951   {
0952     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
0953     __HAL_FLASH_SET_LATENCY(FLatency);
0954
0955     /* Check that the new number of wait states is taken into account to access the Flash
0956     memory by reading the FLASH_ACR register */
0957     if (__HAL_FLASH_GET_LATENCY() != FLatency)
0958     {
0959       return HAL_ERROR;
0960     }
0961
0962   }
0963
0964   /* Increasing the BUS frequency divider */
0965   /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
0966   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
0967   {
0968 #if defined (RCC_D1CFGR_D1PPRE)
0969     if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
0970     {
0971       assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
0972       MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
0973     }
0974 #else
0975     if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
0976     {
0977       assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
0978       MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
0979     }
0980 #endif
0981   }
0982
0983   /*-------------------------- PCLK1 Configuration ---------------------------*/
0984   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
0985   {
0986 #if defined (RCC_D2CFGR_D2PPRE1)
0987     if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
0988     {
0989       assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
0990       MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
0991     }
0992 #else
0993     if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
0994     {
0995       assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
0996       MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
0997     }
0998 #endif
0999   }
1000   /*-------------------------- PCLK2 Configuration ---------------------------*/
1001   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
1002   {
1003 #if defined(RCC_D2CFGR_D2PPRE2)
1004     if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
1005     {
1006       assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
1007       MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
1008     }
1009 #else
1010     if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
1011     {
1012       assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
1013       MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
1014     }
1015 #endif
1016   }
1017
1018   /*-------------------------- D3PCLK1 Configuration ---------------------------*/
1019   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
1020   {
1021 #if defined(RCC_D3CFGR_D3PPRE)
1022     if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
1023     {
1024       assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
1025       MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
1026     }
1027 #else
1028     if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
1029     {
1030       assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
1031       MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider));
1032     }
1033 #endif
1034   }
1035
1036   /*-------------------------- HCLK Configuration --------------------------*/
1037   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
1038   {
1039 #if defined (RCC_D1CFGR_HPRE)
1040     if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
1041     {
1042       /* Set the new HCLK clock divider */
1043       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
1044       MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
1045     }
1046 #else
1047     if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
1048     {
1049       /* Set the new HCLK clock divider */
1050       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
1051       MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
1052     }
1053 #endif
1054   }
1055
1056   /*------------------------- SYSCLK Configuration -------------------------*/
1057   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
1058   {
1059     assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
1060     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
1061 #if defined(RCC_D1CFGR_D1CPRE)
1062     MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
1063 #else
1064     MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
1065 #endif
1066     /* HSE is selected as System Clock Source */
1067     if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
1068     {
1069       /* Check the HSE ready flag */
1070       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
1071       {
1072         return HAL_ERROR;
1073       }
1074     }
1075     /* PLL is selected as System Clock Source */
1076     else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
1077     {
1078       /* Check the PLL ready flag */
1079       if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
1080       {
1081         return HAL_ERROR;
1082       }
1083     }
1084     /* CSI is selected as System Clock Source */
1085     else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
1086     {
1087       /* Check the PLL ready flag */
1088       if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
1089       {
1090         return HAL_ERROR;
1091       }
1092     }
1093     /* HSI is selected as System Clock Source */
1094     else
1095     {
1096       /* Check the HSI ready flag */
1097       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
1098       {
1099         return HAL_ERROR;
1100       }
1101     }
1102     MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
1103
1104     /* Get Start Tick*/
1105     tickstart = HAL_GetTick();
1106
1107     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
1108     {
1109       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1110       {
1111         return HAL_TIMEOUT;
1112       }
1113     }
1114
1115   }
1116
1117   /* Decreasing the BUS frequency divider */
1118   /*-------------------------- HCLK Configuration --------------------------*/
1119   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
1120   {
1121 #if defined(RCC_D1CFGR_HPRE)
1122     if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
1123     {
1124       /* Set the new HCLK clock divider */
1125       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
1126       MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
1127     }
1128 #else
1129     if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
1130     {
1131       /* Set the new HCLK clock divider */
1132       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
1133       MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
1134     }
1135 #endif
1136   }
1137
1138   /* Decreasing the number of wait states because of lower CPU frequency */
1139   if (FLatency < __HAL_FLASH_GET_LATENCY())
1140   {
1141     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
1142     __HAL_FLASH_SET_LATENCY(FLatency);
1143
1144     /* Check that the new number of wait states is taken into account to access the Flash
1145     memory by reading the FLASH_ACR register */
1146     if (__HAL_FLASH_GET_LATENCY() != FLatency)
1147     {
1148       return HAL_ERROR;
1149     }
1150   }
1151
1152   /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
1153   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
1154   {
1155 #if defined(RCC_D1CFGR_D1PPRE)
1156     if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
1157     {
1158       assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
1159       MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
1160     }
1161 #else
1162     if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
1163     {
1164       assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
1165       MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
1166     }
1167 #endif
1168   }
1169
1170   /*-------------------------- PCLK1 Configuration ---------------------------*/
1171   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
1172   {
1173 #if defined(RCC_D2CFGR_D2PPRE1)
1174     if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
1175     {
1176       assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
1177       MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
1178     }
1179 #else
1180     if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
1181     {
1182       assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
1183       MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
1184     }
1185 #endif
1186   }
1187
1188   /*-------------------------- PCLK2 Configuration ---------------------------*/
1189   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
1190   {
1191 #if defined (RCC_D2CFGR_D2PPRE2)
1192     if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
1193     {
1194       assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
1195       MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
1196     }
1197 #else
1198     if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
1199     {
1200       assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
1201       MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
1202     }
1203 #endif
1204   }
1205
1206   /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
1207   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
1208   {
1209 #if defined(RCC_D3CFGR_D3PPRE)
1210     if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
1211     {
1212       assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
1213       MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
1214     }
1215 #else
1216     if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
1217     {
1218       assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider));
1219       MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider));
1220     }
1221 #endif
1222   }
1223
1224   /* Update the SystemCoreClock global variable */
1225 #if defined(RCC_D1CFGR_D1CPRE)
1226   common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
1227 #else
1228   common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
1229 #endif
1230
1231 #if defined(RCC_D1CFGR_HPRE)
1232   SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
1233 #else
1234   SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
1235 #endif
1236
1237 #if defined(DUAL_CORE) && defined(CORE_CM4)
1238   SystemCoreClock = SystemD2Clock;
1239 #else
1240   SystemCoreClock = common_system_clock;
1241 #endif /* DUAL_CORE && CORE_CM4 */
1242
1243   /* Configure the source of time base considering new system clocks settings*/
1244 #ifndef __rtems__
1245   halstatus = HAL_InitTick(uwTickPrio);
1246 #else /* __rtems__ */
1247   halstatus = HAL_OK;
1248 #endif /* __rtems__ */
1249
1250   return halstatus;
1251 }
1252
1253 /**
1254   * @}
1255   */
1256
1257 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
1258   * @ingroup RTEMSBSPsARMSTM32H7
1259  *  @brief   RCC clocks control functions
1260  *
1261 @verbatim
1262  ===============================================================================
1263                       ##### Peripheral Control functions #####
1264  ===============================================================================
1265     [..]
1266     This subsection provides a set of functions allowing to control the RCC Clocks
1267     frequencies.
1268
1269 @endverbatim
1270   * @{
1271   */
1272
1273 /**
1274   * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
1275   * @note   PA8/PC9 should be configured in alternate function mode.
1276   * @param  RCC_MCOx: specifies the output direction for the clock source.
1277   *          This parameter can be one of the following values:
1278   *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
1279   *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
1280   * @param  RCC_MCOSource: specifies the clock source to output.
1281   *          This parameter can be one of the following values:
1282   *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
1283   *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
1284   *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
1285   *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source
1286   *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
1287   *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
1288   *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
1289   *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
1290   *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source
1291   *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source
1292   *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source
1293   * @param  RCC_MCODiv: specifies the MCOx pre-scaler.
1294   *          This parameter can be one of the following values:
1295   *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCOx clock
1296   * @retval None
1297   */
1298 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
1299 {
1300   GPIO_InitTypeDef GPIO_InitStruct;
1301   /* Check the parameters */
1302   assert_param(IS_RCC_MCO(RCC_MCOx));
1303   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
1304   /* RCC_MCO1 */
1305   if (RCC_MCOx == RCC_MCO1)
1306   {
1307     assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
1308
1309     /* MCO1 Clock Enable */
1310     MCO1_CLK_ENABLE();
1311
1312     /* Configure the MCO1 pin in alternate function mode */
1313     GPIO_InitStruct.Pin = MCO1_PIN;
1314     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1315     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
1316     GPIO_InitStruct.Pull = GPIO_NOPULL;
1317     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
1318     HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
1319
1320     /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */
1321     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
1322   }
1323   else
1324   {
1325     assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
1326
1327     /* MCO2 Clock Enable */
1328     MCO2_CLK_ENABLE();
1329
1330     /* Configure the MCO2 pin in alternate function mode */
1331     GPIO_InitStruct.Pin = MCO2_PIN;
1332     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1333     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
1334     GPIO_InitStruct.Pull = GPIO_NOPULL;
1335     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
1336     HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
1337
1338     /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */
1339     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7U)));
1340   }
1341 }
1342
1343 /**
1344   * @brief  Enables the Clock Security System.
1345   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
1346   *         is automatically disabled and an interrupt is generated to inform the
1347   *         software about the failure (Clock Security System Interrupt, CSSI),
1348   *         allowing the MCU to perform rescue operations. The CSSI is linked to
1349   *         the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
1350   * @retval None
1351   */
1352 void HAL_RCC_EnableCSS(void)
1353 {
1354   SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;
1355 }
1356
1357 /**
1358   * @brief  Disables the Clock Security System.
1359   * @retval None
1360   */
1361 void HAL_RCC_DisableCSS(void)
1362 {
1363   CLEAR_BIT(RCC->CR, RCC_CR_CSSHSEON);
1364 }
1365
1366 /**
1367   * @brief  Returns the SYSCLK frequency
1368   *
1369   * @note   The system frequency computed by this function is not the real
1370   *         frequency in the chip. It is calculated based on the predefined
1371   *         constant and the selected clock source:
1372   * @note     If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)
1373   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
1374   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
1375   * @note     If SYSCLK source is PLL, function returns values based on CSI_VALUE(*),
1376   *           HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
1377   * @note     (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
1378   *               4 MHz) but the real value may vary depending on the variations
1379   *               in voltage and temperature.
1380   * @note     (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
1381   *               64 MHz) but the real value may vary depending on the variations
1382   *               in voltage and temperature.
1383   * @note     (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
1384   *                25 MHz), user has to ensure that HSE_VALUE is same as the real
1385   *                frequency of the crystal used. Otherwise, this function may
1386   *                have wrong result.
1387   *
1388   * @note   The result of this function could be not correct when using fractional
1389   *         value for HSE crystal.
1390   *
1391   * @note   This function can be used by the user application to compute the
1392   *         baud rate for the communication peripherals or configure other parameters.
1393   *
1394   * @note   Each time SYSCLK changes, this function must be called to update the
1395   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
1396   *
1397   *
1398   * @retval SYSCLK frequency
1399   */
1400 uint32_t HAL_RCC_GetSysClockFreq(void)
1401 {
1402   uint32_t pllp, pllsource, pllm, pllfracen, hsivalue;
1403   float_t fracn1, pllvco;
1404   uint32_t sysclockfreq;
1405
1406   /* Get SYSCLK source -------------------------------------------------------*/
1407
1408   switch (RCC->CFGR & RCC_CFGR_SWS)
1409   {
1410     case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
1411
1412       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
1413       {
1414         sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
1415       }
1416       else
1417       {
1418         sysclockfreq = (uint32_t) HSI_VALUE;
1419       }
1420
1421       break;
1422
1423     case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
1424       sysclockfreq = CSI_VALUE;
1425       break;
1426
1427     case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
1428       sysclockfreq = HSE_VALUE;
1429       break;
1430
1431     case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
1432
1433       /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
1434       SYSCLK = PLL_VCO / PLLR
1435       */
1436       pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
1437       pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4)  ;
1438       pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
1439       fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
1440
1441       if (pllm != 0U)
1442       {
1443         switch (pllsource)
1444         {
1445           case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
1446
1447             if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
1448             {
1449               hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
1450               pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
1451             }
1452             else
1453             {
1454               pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
1455             }
1456             break;
1457
1458           case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
1459             pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
1460             break;
1461
1462           case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
1463             pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
1464             break;
1465
1466           default:
1467             pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
1468             break;
1469         }
1470         pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
1471         sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp);
1472       }
1473       else
1474       {
1475         sysclockfreq = 0U;
1476       }
1477       break;
1478
1479     default:
1480       sysclockfreq = CSI_VALUE;
1481       break;
1482   }
1483
1484   return sysclockfreq;
1485 }
1486
1487
1488 /**
1489   * @brief  Returns the HCLK frequency
1490   * @note   Each time HCLK changes, this function must be called to update the
1491   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
1492   *
1493   * @note   The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
1494   *         and updated within this function
1495   * @retval HCLK frequency
1496   */
1497 uint32_t HAL_RCC_GetHCLKFreq(void)
1498 {
1499   uint32_t common_system_clock;
1500
1501 #if defined(RCC_D1CFGR_D1CPRE)
1502   common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
1503 #else
1504   common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
1505 #endif
1506
1507 #if defined(RCC_D1CFGR_HPRE)
1508   SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
1509 #else
1510   SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
1511 #endif
1512
1513 #if defined(DUAL_CORE) && defined(CORE_CM4)
1514   SystemCoreClock = SystemD2Clock;
1515 #else
1516   SystemCoreClock = common_system_clock;
1517 #endif /* DUAL_CORE && CORE_CM4 */
1518
1519   return SystemD2Clock;
1520 }
1521
1522
1523 /**
1524   * @brief  Returns the PCLK1 frequency
1525   * @note   Each time PCLK1 changes, this function must be called to update the
1526   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
1527   * @retval PCLK1 frequency
1528   */
1529 uint32_t HAL_RCC_GetPCLK1Freq(void)
1530 {
1531 #if defined (RCC_D2CFGR_D2PPRE1)
1532   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
1533   return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
1534 #else
1535   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
1536   return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
1537 #endif
1538 }
1539
1540
1541 /**
1542   * @brief  Returns the D2 PCLK2 frequency
1543   * @note   Each time PCLK2 changes, this function must be called to update the
1544   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
1545   * @retval PCLK1 frequency
1546   */
1547 uint32_t HAL_RCC_GetPCLK2Freq(void)
1548 {
1549   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
1550 #if defined(RCC_D2CFGR_D2PPRE2)
1551   return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
1552 #else
1553   return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
1554 #endif
1555 }
1556
1557 /**
1558   * @brief  Configures the RCC_OscInitStruct according to the internal
1559   * RCC configuration registers.
1560   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
1561   * will be configured.
1562   * @retval None
1563   */
1564 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
1565 {
1566   /* Set all possible values for the Oscillator type parameter ---------------*/
1567   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \
1568                                       RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
1569
1570   /* Get the HSE configuration -----------------------------------------------*/
1571 #if defined(RCC_CR_HSEEXT)
1572   if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP)
1573   {
1574     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
1575   }
1576   else if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT))
1577   {
1578     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL;
1579   }
1580   else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
1581   {
1582     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
1583   }
1584   else
1585   {
1586     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
1587   }
1588 #else
1589   if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
1590   {
1591     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
1592   }
1593   else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
1594   {
1595     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
1596   }
1597   else
1598   {
1599     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
1600   }
1601 #endif /* RCC_CR_HSEEXT */
1602
1603   /* Get the CSI configuration -----------------------------------------------*/
1604   if ((RCC->CR & RCC_CR_CSION) == RCC_CR_CSION)
1605   {
1606     RCC_OscInitStruct->CSIState = RCC_CSI_ON;
1607   }
1608   else
1609   {
1610     RCC_OscInitStruct->CSIState = RCC_CSI_OFF;
1611   }
1612
1613 #if defined(RCC_VER_X)
1614   if (HAL_GetREVID() <= REV_ID_Y)
1615   {
1616     RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos);
1617   }
1618   else
1619   {
1620     RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1621   }
1622 #else
1623   RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1624 #endif /*RCC_VER_X*/
1625
1626   /* Get the HSI configuration -----------------------------------------------*/
1627   if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
1628   {
1629     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
1630   }
1631   else
1632   {
1633     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
1634   }
1635
1636 #if defined(RCC_VER_X)
1637   if (HAL_GetREVID() <= REV_ID_Y)
1638   {
1639     RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos);
1640   }
1641   else
1642   {
1643     RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1644   }
1645 #else
1646   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1647 #endif /*RCC_VER_X*/
1648
1649   /* Get the LSE configuration -----------------------------------------------*/
1650 #if defined(RCC_BDCR_LSEEXT)
1651   if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP)
1652   {
1653     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
1654   }
1655   else if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT))
1656   {
1657     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL;
1658   }
1659   else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
1660   {
1661     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
1662   }
1663   else
1664   {
1665     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
1666   }
1667 #else
1668   if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
1669   {
1670     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
1671   }
1672   else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
1673   {
1674     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
1675   }
1676   else
1677   {
1678     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
1679   }
1680 #endif /* RCC_BDCR_LSEEXT */
1681
1682   /* Get the LSI configuration -----------------------------------------------*/
1683   if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
1684   {
1685     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
1686   }
1687   else
1688   {
1689     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
1690   }
1691
1692   /* Get the HSI48 configuration ---------------------------------------------*/
1693   if ((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
1694   {
1695     RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
1696   }
1697   else
1698   {
1699     RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
1700   }
1701
1702   /* Get the PLL configuration -----------------------------------------------*/
1703   if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
1704   {
1705     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
1706   }
1707   else
1708   {
1709     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
1710   }
1711   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
1712   RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos);
1713   RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1U;
1714   RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1U;
1715   RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1U;
1716   RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1U;
1717   RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE));
1718   RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLCFGR_PLL1VCOSEL_Pos);
1719   RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos));
1720 }
1721
1722 /**
1723   * @brief  Configures the RCC_ClkInitStruct according to the internal
1724   * RCC configuration registers.
1725   * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
1726   * will be configured.
1727   * @param  pFLatency: Pointer on the Flash Latency.
1728   * @retval None
1729   */
1730 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
1731 {
1732   /* Set all possible values for the Clock type parameter --------------------*/
1733   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
1734                                  RCC_CLOCKTYPE_PCLK2 |  RCC_CLOCKTYPE_D3PCLK1  ;
1735
1736   /* Get the SYSCLK configuration --------------------------------------------*/
1737   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
1738
1739 #if defined(RCC_D1CFGR_D1CPRE)
1740   /* Get the SYSCLK configuration ----------------------------------------------*/
1741   RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
1742
1743   /* Get the D1HCLK configuration ----------------------------------------------*/
1744   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
1745
1746   /* Get the APB3 configuration ----------------------------------------------*/
1747   RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
1748
1749   /* Get the APB1 configuration ----------------------------------------------*/
1750   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
1751
1752   /* Get the APB2 configuration ----------------------------------------------*/
1753   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
1754
1755   /* Get the APB4 configuration ----------------------------------------------*/
1756   RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
1757 #else
1758   /* Get the SYSCLK configuration ----------------------------------------------*/
1759   RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE);
1760
1761   /* Get the D1HCLK configuration ----------------------------------------------*/
1762   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE);
1763
1764   /* Get the APB3 configuration ----------------------------------------------*/
1765   RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE);
1766
1767   /* Get the APB1 configuration ----------------------------------------------*/
1768   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1);
1769
1770   /* Get the APB2 configuration ----------------------------------------------*/
1771   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2);
1772
1773   /* Get the APB4 configuration ----------------------------------------------*/
1774   RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE);
1775 #endif
1776
1777   /* Get the Flash Wait State (Latency) configuration ------------------------*/
1778   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
1779 }
1780
1781 /**
1782   * @brief This function handles the RCC CSS interrupt request.
1783   * @note This API should be called under the NMI_Handler().
1784   * @retval None
1785   */
1786 void HAL_RCC_NMI_IRQHandler(void)
1787 {
1788   /* Check RCC CSSF flag  */
1789   if (__HAL_RCC_GET_IT(RCC_IT_CSS))
1790   {
1791     /* RCC Clock Security System interrupt user callback */
1792     HAL_RCC_CSSCallback();
1793
1794     /* Clear RCC CSS pending bit */
1795     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
1796   }
1797 }
1798
1799 /**
1800   * @brief  RCC Clock Security System interrupt callback
1801   * @retval none
1802   */
1803 __weak void HAL_RCC_CSSCallback(void)
1804 {
1805   /* NOTE : This function Should not be modified, when the callback is needed,
1806             the HAL_RCC_CSSCallback could be implemented in the user file
1807    */
1808 }
1809
1810 /**
1811   * @}
1812   */
1813
1814 /**
1815   * @}
1816   */
1817
1818 #endif /* HAL_RCC_MODULE_ENABLED */
1819 /**
1820   * @}
1821   */
1822
1823 /**
1824   * @}
1825   */
1826