stm32h7/hal/stm32h7xx_hal_pwr.c

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_pwr.c
0004   * @author  MCD Application Team
0005   * @brief   PWR HAL module driver.
0006   *          This file provides firmware functions to manage the following
0007   *          functionalities of the Power Controller (PWR) peripheral:
0008   *           + Initialization and de-initialization functions.
0009   *           + Peripheral Control functions.
0010   *           + Interrupt Handling functions.
0011   ******************************************************************************
0012   * @attention
0013   *
0014   * Copyright (c) 2017 STMicroelectronics.
0015   * All rights reserved.
0016   *
0017   * This software is licensed under terms that can be found in the LICENSE file
0018   * in the root directory of this software component.
0019   * If no LICENSE file comes with this software, it is provided AS-IS.
0020   *
0021   ******************************************************************************
0022   @verbatim
0023   ==============================================================================
0024                         ##### PWR peripheral overview #####
0025   ==============================================================================
0026   [..]
0027    (#) The Power control (PWR) provides an overview of the supply architecture
0028        for the different power domains and of the supply configuration
0029        controller.
0030        In the H7 family, the number of power domains is different between
0031        device lines. This difference is due to characteristics of each device.
0032
0033    (#) Domain architecture overview for the different H7 lines:
0034       (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757.
0035           These devices have 3 power domains (D1, D2 and D3).
0036           The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
0037           peripherals. The D2 domain contains peripherals and a CPU
0038           (Cortex-M4). The D3 domain contains the system control, I/O logic
0039           and low-power peripherals.
0040       (+) STM32H72x, STM32H73x, STM32H742, STM32H743, STM32H750 and STM32H753
0041           devices have 3 power domains (D1, D2 and D3).
0042           The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
0043           peripherals. The D2 domain contains peripherals. The D3 domains
0044           contains the system control, I/O logic and low-power peripherals.
0045       (+) STM32H7Axxx and STM32H7Bxxx devices have 2 power domains (CD and SRD).
0046           The core domain (CD) contains a CPU (Cortex-M7), a Flash
0047           memory and peripherals. The SmartRun domain contains the system
0048           control, I/O logic and low-power peripherals.
0049
0050    (#) Every entity have low power mode as described below :
0051    (#) The CPU low power modes are :
0052       (+) CPU CRUN.
0053       (+) CPU CSLEEP.
0054       (+) CPU CSTOP.
0055    (#) The domain low power modes are :
0056       (+) DRUN.
0057       (+) DSTOP.
0058       (+) DSTANDBY.
0059    (#) The SYSTEM low power modes are :
0060       (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from
0061                  Standby. In Run* mode, the performance is limited and the
0062                  system supply configuration shall be programmed. The system
0063                  enters Run mode only when the ACTVOSRDY bit in PWR control
0064                  status register 1 (PWR_CSR1) is set to 1.
0065       (+) RUN.
0066       (+) STOP.
0067       (+) STANDBY.
0068
0069   ==============================================================================
0070                         ##### How to use this driver #####
0071   ==============================================================================
0072   [..]
0073    (#) Power management peripheral is active by default at startup level in
0074        STM32h7xx lines.
0075
0076    (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
0077        to enable/disable access to the backup domain (RTC registers, RTC backup
0078        data registers and backup SRAM).
0079
0080    (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
0081        mode and voltage threshold) in order to set up the Power Voltage Detector,
0082        then use HAL_PWR_EnablePVD() and  HAL_PWR_DisablePVD() functions to start
0083        and stop the PVD detection.
0084        (+) PVD level could be one of the following values :
0085              (++) 1V95
0086              (++) 2V1
0087              (++) 2V25
0088              (++) 2V4
0089              (++) 2V55
0090              (++) 2V7
0091              (++) 2V85
0092              (++) External voltage level
0093
0094    (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
0095        with the right parameter to configure the wake up pin polarity (Low or
0096        High) and to enable and disable it.
0097
0098    (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP
0099        mode. Wake-up from SLEEP mode could be following to an event or an
0100        interrupt according to low power mode intrinsic request called (__WFI()
0101        or __WFE()).
0102        Please ensure to clear all CPU pending events by calling
0103        HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
0104        in SLEEP mode with __WFE() entry.
0105
0106    (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
0107        mode for single core devices. For dual core devices, this API will enter
0108        the domain (containing Cortex-Mx that executing this function) in DSTOP
0109        mode. According to the used parameter, user could select the regulator to
0110        be kept actif in low power mode and wake-up event type.
0111        Please ensure to clear all CPU pending events by calling
0112        HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
0113        in CSTOP mode with __WFE() entry.
0114
0115    (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
0116        STANDBY mode for single core devices. For dual core devices, this API
0117        will enter the domain (containing Cortex-Mx that executing this function)
0118        in DSTANDBY mode.
0119
0120    (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
0121        enable and disable the Cortex-Mx re-entring in SLEEP mode after an
0122        interruption handling is over.
0123
0124    (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
0125        to configure the Cortex-Mx to wake-up after any pending event / interrupt
0126        even if it's disabled or has insufficient priority to cause exception
0127        entry.
0128
0129    (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt
0130        request.
0131
0132      *** PWR HAL driver macros list ***
0133      =============================================
0134      [..]
0135        Below the list of most used macros in PWR HAL driver.
0136
0137       (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal
0138                                               regulator output voltage.
0139       (+) __HAL_PWR_GET_FLAG()              : Get the PWR pending flags.
0140       (+) __HAL_PWR_CLEAR_FLAG()            : Clear the PWR pending flags.
0141
0142   @endverbatim
0143   */
0144
0145 /* Includes ------------------------------------------------------------------*/
0146 #include "stm32h7xx_hal.h"
0147
0148 /** @addtogroup STM32H7xx_HAL_Driver
0149   * @{
0150   */
0151
0152 /** @defgroup PWR PWR
0153   * @ingroup RTEMSBSPsARMSTM32H7
0154   * @brief PWR HAL module driver
0155   * @{
0156   */
0157
0158 #ifdef HAL_PWR_MODULE_ENABLED
0159
0160 /* Private typedef -----------------------------------------------------------*/
0161 /* Private define ------------------------------------------------------------*/
0162
0163 /** @addtogroup PWR_Private_Constants PWR Private Constants
0164   * @{
0165   */
0166
0167 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
0168   * @ingroup RTEMSBSPsARMSTM32H7
0169   * @{
0170   */
0171 #if !defined (DUAL_CORE)
0172 #define PVD_MODE_IT              (0x00010000U)
0173 #define PVD_MODE_EVT             (0x00020000U)
0174 #endif /* !defined (DUAL_CORE) */
0175
0176 #define PVD_RISING_EDGE          (0x00000001U)
0177 #define PVD_FALLING_EDGE         (0x00000002U)
0178 #define PVD_RISING_FALLING_EDGE  (0x00000003U)
0179 /**
0180   * @}
0181   */
0182
0183 /**
0184   * @}
0185   */
0186
0187 /* Private macro -------------------------------------------------------------*/
0188 /* Private variables ---------------------------------------------------------*/
0189 /* Private function prototypes -----------------------------------------------*/
0190 /* Private functions ---------------------------------------------------------*/
0191
0192 /** @defgroup PWR_Exported_Functions PWR Exported Functions
0193   * @ingroup RTEMSBSPsARMSTM32H7
0194   * @{
0195   */
0196
0197 /** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
0198   * @ingroup RTEMSBSPsARMSTM32H7
0199   * @brief    Initialization and De-Initialization functions
0200   *
0201 @verbatim
0202  ===============================================================================
0203               ##### Initialization and De-Initialization Functions #####
0204  ===============================================================================
0205     [..]
0206       This section provides functions allowing to deinitialize power peripheral.
0207
0208     [..]
0209       After system reset, the backup domain (RTC registers, RTC backup data
0210       registers and backup SRAM) is protected against possible unwanted write
0211       accesses.
0212       The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
0213       domain.
0214       The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
0215       domain.
0216
0217 @endverbatim
0218   * @{
0219   */
0220
0221 /**
0222   * @brief  Deinitialize the HAL PWR peripheral registers to their default reset
0223   *         values.
0224   * @note   This functionality is not available in this product.
0225   *         The prototype is kept just to maintain compatibility with other
0226   *         products.
0227   * @retval None.
0228   */
0229 void HAL_PWR_DeInit (void)
0230 {
0231 }
0232
0233 /**
0234   * @brief  Enable access to the backup domain (RTC registers, RTC backup data
0235   *         registers and backup SRAM).
0236   * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
0237   *         Backup Domain Access should be kept enabled.
0238   * @retval None.
0239   */
0240 void HAL_PWR_EnableBkUpAccess (void)
0241 {
0242   /* Enable access to RTC and backup registers */
0243   SET_BIT (PWR->CR1, PWR_CR1_DBP);
0244 }
0245
0246 /**
0247   * @brief  Disable access to the backup domain (RTC registers, RTC backup data
0248   *         registers and backup SRAM).
0249   * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
0250   *         Backup Domain Access should be kept enabled.
0251   * @retval None.
0252   */
0253 void HAL_PWR_DisableBkUpAccess (void)
0254 {
0255   /* Disable access to RTC and backup registers */
0256   CLEAR_BIT (PWR->CR1, PWR_CR1_DBP);
0257 }
0258 /**
0259   * @}
0260   */
0261
0262 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
0263   * @ingroup RTEMSBSPsARMSTM32H7
0264   *  @brief   Power Control functions
0265   *
0266 @verbatim
0267  ===============================================================================
0268                  ##### Peripheral Control Functions #####
0269  ===============================================================================
0270     [..]
0271       This section provides functions allowing to control power peripheral.
0272
0273     *** PVD configuration ***
0274     =========================
0275     [..]
0276       (+) The PVD is used to monitor the VDD power supply by comparing it to a
0277           threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1
0278           register).
0279
0280       (+) A PVDO flag is available to indicate if VDD is higher or lower
0281           than the PVD threshold. This event is internally connected to the EXTI
0282           line 16 to generate an interrupt if enabled.
0283           It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
0284
0285       (+) The PVD is stopped in STANDBY mode.
0286
0287     *** Wake-up pin configuration ***
0288     =================================
0289     [..]
0290       (+) Wake-up pin is used to wake up the system from STANDBY mode.
0291           The pin pull is configurable through the WKUPEPR register to be in
0292           No-pull, Pull-up and Pull-down.
0293           The pin polarity is configurable through the WKUPEPR register to be
0294           active on rising or falling edges.
0295
0296       (+) There are up to six Wake-up pin in the STM32H7 devices family.
0297
0298     *** Low Power modes configuration ***
0299     =====================================
0300     [..]
0301      The device present 3 principles low-power modes features:
0302       (+) SLEEP mode   : Cortex-Mx is stopped and all PWR domains are remaining
0303                          active (Powered and Clocked).
0304
0305       (+) STOP mode    : Cortex-Mx is stopped, clocks are stopped and the
0306                          regulator is running. The Main regulator or the LP
0307                          regulator could be selected.
0308
0309       (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
0310                          supply regulator is powered off.
0311
0312    *** SLEEP mode ***
0313    ==================
0314     [..]
0315       (+) Entry:
0316         The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
0317         SLEEPEntry) function.
0318
0319           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction.
0320           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction.
0321
0322       -@@- The Regulator parameter is not used for the STM32H7 family
0323               and is kept as parameter just to maintain compatibility with the
0324               lower power families (STM32L).
0325
0326       (+) Exit:
0327         Any peripheral interrupt acknowledged by the nested vectored interrupt
0328         controller (NVIC) can wake up the device from SLEEP mode.
0329
0330    *** STOP mode ***
0331    =================
0332     [..]
0333       In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL,
0334       the HSI, and the HSE RC oscillators are disabled. Internal SRAM and
0335       register contents are preserved.
0336       The voltage regulator can be configured either in normal or low-power mode.
0337       To minimize the consumption in STOP mode, FLASH can be powered off before
0338       entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
0339       It can be switched on again by software after exiting the STOP mode using
0340       the HAL_PWREx_DisableFlashPowerDown() function.
0341
0342       (+) Entry:
0343          The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
0344          STOPEntry) function with:
0345
0346          (++) Regulator:
0347           (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
0348           (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
0349
0350          (++) STOPEntry:
0351           (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction.
0352           (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction.
0353
0354       (+) Exit:
0355          Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
0356
0357    *** STANDBY mode ***
0358    ====================
0359     [..]
0360     (+)
0361       The system STANDBY mode allows to achieve the lowest power consumption.
0362       It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator
0363       disabled. The system is consequently powered off. The PLL, the HSI
0364       oscillator and the HSE oscillator are also switched off. SRAM and register
0365       contents are lost except for the RTC registers, RTC backup registers,
0366       backup SRAM and standby circuitry.
0367
0368     [..]
0369       The voltage regulator is OFF.
0370
0371       (++) Entry:
0372         (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
0373               function.
0374
0375       (++) Exit:
0376         (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
0377               RTC wakeup, tamper event, time stamp event, external reset in NRST
0378               pin, IWDG reset.
0379
0380    *** Auto-wakeup (AWU) from low-power mode ***
0381    =============================================
0382     [..]
0383      (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
0384          RTC Wakeup event, a tamper event or a time-stamp event, without
0385          depending on an external interrupt (Auto-wakeup mode).
0386
0387      (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
0388
0389        (++) To wake up from the STOP mode with an RTC alarm event, it is
0390             necessary to configure the RTC to generate the RTC alarm using the
0391             HAL_RTC_SetAlarm_IT() function.
0392
0393        (++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
0394             it is necessary to configure the RTC to detect the tamper or time
0395             stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
0396             HAL_RTCEx_SetTamper_IT() functions.
0397
0398        (++) To wake up from the STOP mode with an RTC WakeUp event, it is
0399             necessary to configure the RTC to generate the RTC WakeUp event
0400             using the HAL_RTCEx_SetWakeUpTimer_IT() function.
0401
0402 @endverbatim
0403   * @{
0404   */
0405
0406 /**
0407   * @brief  Configure the event mode and the voltage threshold detected by the
0408   *         Programmable Voltage Detector(PVD).
0409   * @param  sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains
0410   *                      the configuration information for the PVD.
0411   * @note   Refer to the electrical characteristics of your device datasheet for
0412   *         more details about the voltage threshold corresponding to each
0413   *         detection level.
0414   * @note   For dual core devices, please ensure to configure the EXTI lines for
0415   *         the different Cortex-Mx through PWR_Exported_Macro provided by this
0416   *         driver. All combination are allowed: wake up only Cortex-M7, wake up
0417   *         only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
0418   * @retval None.
0419   */
0420 void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
0421 {
0422   /* Check the PVD configuration parameter */
0423   if (sConfigPVD == NULL)
0424   {
0425     return;
0426   }
0427
0428   /* Check the parameters */
0429   assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
0430   assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));
0431
0432   /* Set PLS[7:5] bits according to PVDLevel value */
0433   MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
0434
0435   /* Clear previous config */
0436 #if !defined (DUAL_CORE)
0437   __HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
0438   __HAL_PWR_PVD_EXTI_DISABLE_IT ();
0439 #endif /* !defined (DUAL_CORE) */
0440
0441   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
0442   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
0443
0444 #if !defined (DUAL_CORE)
0445   /* Interrupt mode configuration */
0446   if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
0447   {
0448     __HAL_PWR_PVD_EXTI_ENABLE_IT ();
0449   }
0450
0451   /* Event mode configuration */
0452   if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
0453   {
0454     __HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
0455   }
0456 #endif /* !defined (DUAL_CORE) */
0457
0458   /* Rising edge configuration */
0459   if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
0460   {
0461     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
0462   }
0463
0464   /* Falling edge configuration */
0465   if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
0466   {
0467     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
0468   }
0469 }
0470
0471 /**
0472   * @brief Enable the Programmable Voltage Detector (PVD).
0473   * @retval None.
0474   */
0475 void HAL_PWR_EnablePVD (void)
0476 {
0477   /* Enable the power voltage detector */
0478   SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
0479 }
0480
0481 /**
0482   * @brief Disable the Programmable Voltage Detector (PVD).
0483   * @retval None.
0484   */
0485 void HAL_PWR_DisablePVD (void)
0486 {
0487   /* Disable the power voltage detector */
0488   CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN);
0489 }
0490
0491 /**
0492   * @brief  Enable the WakeUp PINx functionality.
0493   * @param  WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
0494   *          This parameter can be one of the following legacy values, which
0495   *          sets the default (rising edge):
0496   *            @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
0497   *                 PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6.
0498   *          or one of the following values where the user can explicitly states
0499   *          the enabled pin and the chosen polarity:
0500   *            @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
0501   *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
0502   *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
0503   *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
0504   *                 PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
0505   *                 PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
0506   * @note   PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
0507   * @note   The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH
0508   *         and PWR_WAKEUP_PIN5_LOW are available only for devices that includes
0509   *         GPIOI port.
0510   * @retval None.
0511   */
0512 void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
0513 {
0514   /* Check the parameters */
0515   assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity));
0516
0517   /*
0518      Enable and Specify the Wake-Up pin polarity and the pull configuration
0519      for the event detection (rising or falling edge).
0520   */
0521   MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
0522 }
0523
0524 /**
0525   * @brief  Disable the WakeUp PINx functionality.
0526   * @param  WakeUpPinx : Specifies the Power Wake-Up pin to disable.
0527   *          This parameter can be one of the following values:
0528   *            @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
0529   *                 PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6,
0530   *                 PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
0531   *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
0532   *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
0533   *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
0534   *                 PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
0535   *                 PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
0536   * @note   The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH
0537   *         and PWR_WAKEUP_PIN5_LOW are available only for devices that includes
0538   *         GPIOI port.
0539   * @retval None.
0540   */
0541 void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
0542 {
0543   /* Check the parameters */
0544   assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx));
0545
0546   /* Disable the wake up pin selected */
0547   CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
0548 }
0549
0550 /**
0551   * @brief  Enter the current core in SLEEP mode (CSLEEP).
0552   * @param  Regulator : Specifies the regulator state in SLEEP mode.
0553   *          This parameter can be one of the following values:
0554   *            @arg PWR_MAINREGULATOR_ON     : SLEEP mode with regulator ON.
0555   *            @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power
0556   *                                           regulator ON.
0557   * @note   This parameter is not used for the STM32H7 family and is kept as
0558   *         parameter just to maintain compatibility with the lower power
0559   *         families.
0560   * @param  SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
0561   *                      intrinsic instruction.
0562   *          This parameter can be one of the following values:
0563   *            @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction.
0564   *            @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction.
0565   * @note   Ensure to clear pending events before calling this API through
0566   *         HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE.
0567   * @retval None.
0568   */
0569 void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
0570 {
0571   /* Check the parameters */
0572   assert_param (IS_PWR_REGULATOR (Regulator));
0573   assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
0574
0575   /* Prevent unused argument(s) compilation warning */
0576   UNUSED(Regulator);
0577
0578   /* Clear SLEEPDEEP bit of Cortex System Control Register */
0579   CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
0580
0581   /* Select SLEEP mode entry */
0582   if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
0583   {
0584     /* Request Wait For Interrupt */
0585     __WFI ();
0586   }
0587   else
0588   {
0589     /* Request Wait For Event */
0590     __WFE ();
0591   }
0592 }
0593
0594 /**
0595   * @brief  Enter STOP mode.
0596   * @note   For single core devices, this API will enter the system in STOP mode
0597   *         with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR register is
0598   *         cleared.
0599   *         For dual core devices, this API will enter the domain (containing
0600   *         Cortex-Mx that executing this function) in DSTOP mode. If all
0601   *         Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is
0602   *         cleared, all the system will enter in STOP mode.
0603   * @param  Regulator : Specifies the regulator state in STOP mode.
0604   *          This parameter can be one of the following values:
0605   *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
0606   *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
0607   *                                            regulator ON.
0608   * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
0609   *                     intrinsic instruction.
0610   *          This parameter can be one of the following values:
0611   *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
0612   *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
0613   * @note   In System STOP mode, all I/O pins keep the same state as in Run mode.
0614   * @note   When exiting System STOP mode by issuing an interrupt or a wakeup
0615   *         event, the HSI RC oscillator is selected as default system wakeup
0616   *         clock.
0617   * @note   In System STOP mode, when the voltage regulator operates in low
0618   *         power mode, an additional startup delay is incurred when the system
0619   *         is waking up. By keeping the internal regulator ON during STOP mode,
0620   *         the consumption is higher although the startup time is reduced.
0621   * @retval None.
0622   */
0623 void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
0624 {
0625   /* Check the parameters */
0626   assert_param (IS_PWR_REGULATOR (Regulator));
0627   assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
0628
0629   /* Select the regulator state in STOP mode */
0630   MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
0631
0632   /* Configure the PWR mode for the different Domains */
0633 #if defined (DUAL_CORE)
0634   /* Check CPU ID */
0635   if (HAL_GetCurrentCPUID () == CM7_CPUID)
0636   {
0637     /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */
0638     CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
0639   }
0640   else
0641   {
0642     /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */
0643     CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
0644   }
0645 #else /* Single core devices */
0646   /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
0647   CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
0648
0649 #if defined (PWR_CPUCR_PDDS_D2)
0650   /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
0651   CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
0652 #endif /* PWR_CPUCR_PDDS_D2 */
0653 #endif /* defined (DUAL_CORE) */
0654
0655   /* Set SLEEPDEEP bit of Cortex System Control Register */
0656   SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
0657
0658   /* Ensure that all instructions are done before entering STOP mode */
0659   __DSB ();
0660   __ISB ();
0661
0662   /* Select STOP mode entry */
0663   if (STOPEntry == PWR_STOPENTRY_WFI)
0664   {
0665     /* Request Wait For Interrupt */
0666     __WFI ();
0667   }
0668   else
0669   {
0670     /* Request Wait For Event */
0671     __WFE ();
0672   }
0673
0674   /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
0675   CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
0676 }
0677
0678 /**
0679   * @brief  Enter STANDBY mode.
0680   * @note   For single core devices, this API will enter the system in STANDBY
0681   *         mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR
0682   *         register is cleared.
0683   *         For dual core devices, this API will enter the domain (containing
0684   *         Cortex-Mx that executing this function) in DSTANDBY mode. If all
0685   *         Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register
0686   *         is cleared, all the system will enter in STANDBY mode.
0687   * @note   The system enters Standby mode only when all domains are in DSTANDBY.
0688   * @note   When the System exit STANDBY mode by issuing an interrupt or a
0689   *         wakeup event, the HSI RC oscillator is selected as system clock.
0690   * @note   It is recommended to disable all regulators before entring STANDBY
0691   *         mode for power consumption saving purpose.
0692   * @retval None.
0693   */
0694 void HAL_PWR_EnterSTANDBYMode (void)
0695 {
0696   /* Configure the PWR mode for the different Domains */
0697 #if defined (DUAL_CORE)
0698   /* Check CPU ID */
0699   if (HAL_GetCurrentCPUID () == CM7_CPUID)
0700   {
0701     /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
0702     SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
0703     SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3));
0704   }
0705   else
0706   {
0707     /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */
0708     SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
0709     SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3));
0710   }
0711 #else /* Single core devices */
0712   /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
0713   SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
0714
0715 #if defined (PWR_CPUCR_PDDS_D2)
0716   /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
0717   SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
0718 #endif /* PWR_CPUCR_PDDS_D2 */
0719 #endif /* defined (DUAL_CORE) */
0720
0721   /* Set SLEEPDEEP bit of Cortex System Control Register */
0722   SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
0723
0724   /* Ensure that all instructions are done before entering STOP mode */
0725   __DSB ();
0726   __ISB ();
0727
0728   /* This option is used to ensure that store operations are completed */
0729 #if defined (__CC_ARM)
0730   __force_stores();
0731 #endif /* defined (__CC_ARM) */
0732
0733   /* Request Wait For Interrupt */
0734   __WFI ();
0735 }
0736
0737 /**
0738   * @brief  Indicate Sleep-On-Exit feature when returning from Handler mode to
0739   *         Thread mode.
0740   * @note   Set SLEEPONEXIT bit of SCR register. When this bit is set, the
0741   *         processor re-enters SLEEP mode when an interruption handling is over.
0742   *         Setting this bit is useful when the processor is expected to run
0743   *         only on interruptions handling.
0744   * @retval None.
0745   */
0746 void HAL_PWR_EnableSleepOnExit (void)
0747 {
0748   /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */
0749   SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
0750 }
0751
0752 /**
0753   * @brief  Disable Sleep-On-Exit feature when returning from Handler mode to
0754   *         Thread mode.
0755   * @note   Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
0756   *         processor re-enters SLEEP mode when an interruption handling is over.
0757   * @retval None
0758   */
0759 void HAL_PWR_DisableSleepOnExit (void)
0760 {
0761   /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */
0762   CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
0763 }
0764
0765 /**
0766   * @brief  Enable CORTEX SEVONPEND feature.
0767   * @note   Sets SEVONPEND bit of SCR register. When this bit is set, any
0768   *         pending event / interrupt even if it's disabled or has insufficient
0769   *         priority to cause exception entry wakes up the Cortex-Mx.
0770   * @retval None.
0771   */
0772 void HAL_PWR_EnableSEVOnPend (void)
0773 {
0774   /* Set SEVONPEND bit of Cortex-Mx System Control Register */
0775   SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
0776 }
0777
0778 /**
0779   * @brief  Disable CORTEX SEVONPEND feature.
0780   * @note   Resets SEVONPEND bit of SCR register. When this bit is reset, only
0781   *         enabled pending causes exception entry wakes up the Cortex-Mx.
0782   * @retval None.
0783   */
0784 void HAL_PWR_DisableSEVOnPend (void)
0785 {
0786   /* Clear SEVONPEND bit of Cortex System Control Register */
0787   CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
0788 }
0789 /**
0790   * @}
0791   */
0792
0793 /** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions
0794   * @ingroup RTEMSBSPsARMSTM32H7
0795   *  @brief   Interrupt Handling functions
0796   *
0797 @verbatim
0798  ===============================================================================
0799                     ##### Interrupt Handling Functions #####
0800  ===============================================================================
0801     [..]
0802     This section provides functions allowing to handle the PVD pending
0803     interrupts.
0804
0805 @endverbatim
0806   * @{
0807   */
0808
0809 /**
0810   * @brief  This function handles the PWR PVD interrupt request.
0811   * @note   This API should be called under the PVD_AVD_IRQHandler().
0812   * @retval None.
0813   */
0814 void HAL_PWR_PVD_IRQHandler (void)
0815 {
0816 #if defined (DUAL_CORE)
0817   /* Check Cortex-Mx ID */
0818   if (HAL_GetCurrentCPUID () == CM7_CPUID)
0819   {
0820     /* Check PWR EXTI D1 flag */
0821     if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
0822     {
0823       /* Clear PWR EXTI D1 pending bit */
0824       __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
0825
0826       /* PWR PVD interrupt user callback */
0827       HAL_PWR_PVDCallback ();
0828     }
0829   }
0830   else
0831   {
0832     /* Check PWR EXTI D2 flag */
0833     if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
0834     {
0835       /* Clear PWR EXTI D2 pending bit */
0836       __HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
0837
0838       /* PWR PVD interrupt user callback */
0839       HAL_PWR_PVDCallback ();
0840     }
0841   }
0842 #else /* Single core devices */
0843   /* PVD EXTI line interrupt detected */
0844   if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
0845   {
0846     /* Clear PWR EXTI pending bit */
0847     __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
0848
0849     /* PWR PVD interrupt user callback */
0850     HAL_PWR_PVDCallback ();
0851   }
0852 #endif /* defined (DUAL_CORE) */
0853 }
0854
0855 /**
0856   * @brief  PWR PVD interrupt callback.
0857   * @retval None.
0858   */
0859 __weak void HAL_PWR_PVDCallback (void)
0860 {
0861   /* NOTE : This function should not be modified, when the callback is needed,
0862             the HAL_PWR_PVDCallback can be implemented in the user file
0863   */
0864 }
0865
0866 /**
0867   * @}
0868   */
0869
0870 /**
0871   * @}
0872   */
0873
0874 #endif /* HAL_PWR_MODULE_ENABLED */
0875 /**
0876   * @}
0877   */
0878
0879 /**
0880   * @}
0881   */
0882