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0147 #include "stm32h7xx_hal.h"
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0158
0159 #ifdef HAL_PSSI_MODULE_ENABLED
0160 #if defined(PSSI)
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0183
0184 #if defined(HAL_DMA_MODULE_ENABLED)
0185 void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
0186 void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
0187 void PSSI_DMAError(DMA_HandleTypeDef *hdma);
0188 void PSSI_DMAAbort(DMA_HandleTypeDef *hdma);
0189 #endif
0190
0191
0192 static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode);
0193
0194
0195
0196
0197
0198
0199 static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status,
0200 uint32_t Timeout, uint32_t Tickstart);
0201
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0250
0251 HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi)
0252 {
0253
0254 if (hpssi == NULL)
0255 {
0256 return HAL_ERROR;
0257 }
0258
0259
0260 assert_param(IS_PSSI_ALL_INSTANCE(hpssi->Instance));
0261 assert_param(IS_PSSI_CONTROL_SIGNAL(hpssi->Init.ControlSignal));
0262 assert_param(IS_PSSI_BUSWIDTH(hpssi->Init.BusWidth));
0263 assert_param(IS_PSSI_CLOCK_POLARITY(hpssi->Init.ClockPolarity));
0264 assert_param(IS_PSSI_DE_POLARITY(hpssi->Init.DataEnablePolarity));
0265 assert_param(IS_PSSI_RDY_POLARITY(hpssi->Init.ReadyPolarity));
0266
0267 if (hpssi->State == HAL_PSSI_STATE_RESET)
0268 {
0269
0270 hpssi->Lock = HAL_UNLOCKED;
0271
0272 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
0273
0274 hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback;
0275 hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback;
0276 hpssi->ErrorCallback = HAL_PSSI_ErrorCallback;
0277 hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback;
0278
0279 if (hpssi->MspInitCallback == NULL)
0280 {
0281 hpssi->MspInitCallback = HAL_PSSI_MspInit;
0282 }
0283
0284
0285 hpssi->MspInitCallback(hpssi);
0286 #else
0287
0288 HAL_PSSI_MspInit(hpssi);
0289 #endif
0290 }
0291
0292 hpssi->State = HAL_PSSI_STATE_BUSY;
0293
0294
0295 HAL_PSSI_DISABLE(hpssi);
0296
0297
0298
0299
0300 MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DERDYCFG | PSSI_CR_EDM | PSSI_CR_DEPOL | PSSI_CR_RDYPOL,
0301 hpssi->Init.ControlSignal | hpssi->Init.DataEnablePolarity |
0302 hpssi->Init.ReadyPolarity | hpssi->Init.BusWidth);
0303
0304 hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
0305 hpssi->State = HAL_PSSI_STATE_READY;
0306
0307 return HAL_OK;
0308 }
0309
0310
0311
0312
0313
0314
0315
0316 HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi)
0317 {
0318
0319 if (hpssi == NULL)
0320 {
0321 return HAL_ERROR;
0322 }
0323
0324
0325 assert_param(IS_PSSI_ALL_INSTANCE(hpssi->Instance));
0326
0327 hpssi->State = HAL_PSSI_STATE_BUSY;
0328
0329
0330 HAL_PSSI_DISABLE(hpssi);
0331
0332 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
0333 if (hpssi->MspDeInitCallback == NULL)
0334 {
0335 hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit;
0336 }
0337
0338
0339 hpssi->MspDeInitCallback(hpssi);
0340 #else
0341
0342 HAL_PSSI_MspDeInit(hpssi);
0343 #endif
0344
0345 hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
0346 hpssi->State = HAL_PSSI_STATE_RESET;
0347
0348
0349 __HAL_UNLOCK(hpssi);
0350
0351 return HAL_OK;
0352 }
0353
0354
0355
0356
0357
0358
0359
0360 __weak void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi)
0361 {
0362
0363 UNUSED(hpssi);
0364
0365
0366
0367
0368 }
0369
0370
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0374
0375
0376 __weak void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi)
0377 {
0378
0379 UNUSED(hpssi);
0380
0381
0382
0383
0384 }
0385
0386 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
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0406 HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID,
0407 pPSSI_CallbackTypeDef pCallback)
0408 {
0409 HAL_StatusTypeDef status = HAL_OK;
0410
0411 if (pCallback == NULL)
0412 {
0413
0414 hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
0415
0416 return HAL_ERROR;
0417 }
0418
0419 if (HAL_PSSI_STATE_READY == hpssi->State)
0420 {
0421 switch (CallbackID)
0422 {
0423 case HAL_PSSI_TX_COMPLETE_CB_ID :
0424 hpssi->TxCpltCallback = pCallback;
0425 break;
0426
0427 case HAL_PSSI_RX_COMPLETE_CB_ID :
0428 hpssi->RxCpltCallback = pCallback;
0429 break;
0430
0431 case HAL_PSSI_ERROR_CB_ID :
0432 hpssi->ErrorCallback = pCallback;
0433 break;
0434
0435 case HAL_PSSI_ABORT_CB_ID :
0436 hpssi->AbortCpltCallback = pCallback;
0437 break;
0438
0439 case HAL_PSSI_MSPINIT_CB_ID :
0440 hpssi->MspInitCallback = pCallback;
0441 break;
0442
0443 case HAL_PSSI_MSPDEINIT_CB_ID :
0444 hpssi->MspDeInitCallback = pCallback;
0445 break;
0446
0447 default :
0448
0449 hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
0450
0451
0452 status = HAL_ERROR;
0453 break;
0454 }
0455 }
0456 else if (HAL_PSSI_STATE_RESET == hpssi->State)
0457 {
0458 switch (CallbackID)
0459 {
0460 case HAL_PSSI_MSPINIT_CB_ID :
0461 hpssi->MspInitCallback = pCallback;
0462 break;
0463
0464 case HAL_PSSI_MSPDEINIT_CB_ID :
0465 hpssi->MspDeInitCallback = pCallback;
0466 break;
0467
0468 default :
0469
0470 hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
0471
0472
0473 status = HAL_ERROR;
0474 break;
0475 }
0476 }
0477 else
0478 {
0479
0480 hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
0481
0482
0483 status = HAL_ERROR;
0484 }
0485
0486 return status;
0487 }
0488
0489
0490
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0495
0496
0497
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0500
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0502
0503
0504
0505
0506
0507 HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID)
0508 {
0509 HAL_StatusTypeDef status = HAL_OK;
0510
0511 if (HAL_PSSI_STATE_READY == hpssi->State)
0512 {
0513 switch (CallbackID)
0514 {
0515 case HAL_PSSI_TX_COMPLETE_CB_ID :
0516 hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback;
0517 break;
0518
0519 case HAL_PSSI_RX_COMPLETE_CB_ID :
0520 hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback;
0521 break;
0522
0523 case HAL_PSSI_ERROR_CB_ID :
0524 hpssi->ErrorCallback = HAL_PSSI_ErrorCallback;
0525 break;
0526
0527 case HAL_PSSI_ABORT_CB_ID :
0528 hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback;
0529 break;
0530
0531 case HAL_PSSI_MSPINIT_CB_ID :
0532 hpssi->MspInitCallback = HAL_PSSI_MspInit;
0533 break;
0534
0535 case HAL_PSSI_MSPDEINIT_CB_ID :
0536 hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit;
0537 break;
0538
0539 default :
0540
0541 hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
0542
0543
0544 status = HAL_ERROR;
0545 break;
0546 }
0547 }
0548 else if (HAL_PSSI_STATE_RESET == hpssi->State)
0549 {
0550 switch (CallbackID)
0551 {
0552 case HAL_PSSI_MSPINIT_CB_ID :
0553 hpssi->MspInitCallback = HAL_PSSI_MspInit;
0554 break;
0555
0556 case HAL_PSSI_MSPDEINIT_CB_ID :
0557 hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit;
0558 break;
0559
0560 default :
0561
0562 hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
0563
0564
0565 status = HAL_ERROR;
0566 break;
0567 }
0568 }
0569 else
0570 {
0571
0572 hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
0573
0574
0575 status = HAL_ERROR;
0576 }
0577
0578 return status;
0579 }
0580
0581 #endif
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0634
0635 HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
0636 {
0637 uint32_t tickstart;
0638 uint32_t transfer_size = Size;
0639
0640 if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
0641 ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) ||
0642 ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U)))
0643 {
0644 hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
0645 return HAL_ERROR;
0646 }
0647 if (hpssi->State == HAL_PSSI_STATE_READY)
0648 {
0649
0650 __HAL_LOCK(hpssi);
0651
0652 hpssi->State = HAL_PSSI_STATE_BUSY;
0653 hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
0654
0655
0656 HAL_PSSI_DISABLE(hpssi);
0657
0658
0659 MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL),
0660 (PSSI_CR_OUTEN_OUTPUT |((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)));
0661
0662 #if defined(HAL_DMA_MODULE_ENABLED)
0663
0664 hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
0665 #endif
0666
0667
0668 HAL_PSSI_ENABLE(hpssi);
0669
0670 if (hpssi->Init.DataWidth == HAL_PSSI_8BITS)
0671 {
0672 uint8_t *pbuffer = pData;
0673 while (transfer_size > 0U)
0674 {
0675
0676 tickstart = HAL_GetTick();
0677
0678 if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT1B, RESET, Timeout, tickstart) != HAL_OK)
0679 {
0680 hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
0681 hpssi->State = HAL_PSSI_STATE_READY;
0682
0683 __HAL_UNLOCK(hpssi);
0684 return HAL_ERROR;
0685 }
0686
0687 *(__IO uint8_t *)(&hpssi->Instance->DR) = *(uint8_t *)pbuffer;
0688
0689
0690 pbuffer++;
0691
0692 transfer_size--;
0693 }
0694 }
0695 else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS)
0696 {
0697 uint16_t *pbuffer = (uint16_t *)pData;
0698 __IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR);
0699
0700 while (transfer_size > 0U)
0701 {
0702
0703 tickstart = HAL_GetTick();
0704
0705 if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
0706 {
0707 hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
0708 hpssi->State = HAL_PSSI_STATE_READY;
0709
0710 __HAL_UNLOCK(hpssi);
0711 return HAL_ERROR;
0712 }
0713
0714 *dr = *pbuffer;
0715
0716
0717 pbuffer++;
0718 transfer_size -= 2U;
0719 }
0720 }
0721 else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
0722 {
0723 uint32_t *pbuffer = (uint32_t *)pData;
0724 while (transfer_size > 0U)
0725 {
0726
0727 tickstart = HAL_GetTick();
0728
0729 if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
0730 {
0731 hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
0732 hpssi->State = HAL_PSSI_STATE_READY;
0733
0734 __HAL_UNLOCK(hpssi);
0735 return HAL_ERROR;
0736 }
0737
0738 *(__IO uint32_t *)(&hpssi->Instance->DR) = *pbuffer;
0739
0740
0741 pbuffer++;
0742 transfer_size -= 4U;
0743 }
0744 }
0745 else
0746 {
0747 hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
0748 hpssi->State = HAL_PSSI_STATE_READY;
0749
0750 __HAL_UNLOCK(hpssi);
0751 return HAL_ERROR;
0752 }
0753
0754
0755 if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_RIS) != 0U)
0756 {
0757 HAL_PSSI_CLEAR_FLAG(hpssi, PSSI_FLAG_OVR_RIS);
0758 HAL_PSSI_DISABLE(hpssi);
0759 hpssi->ErrorCode = HAL_PSSI_ERROR_UNDER_RUN;
0760 hpssi->State = HAL_PSSI_STATE_READY;
0761
0762 __HAL_UNLOCK(hpssi);
0763 return HAL_ERROR;
0764 }
0765
0766 hpssi->State = HAL_PSSI_STATE_READY;
0767
0768
0769 __HAL_UNLOCK(hpssi);
0770
0771 return HAL_OK;
0772 }
0773 else
0774 {
0775 return HAL_BUSY;
0776 }
0777 }
0778
0779
0780
0781
0782
0783
0784
0785
0786
0787
0788 HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
0789 {
0790 uint32_t tickstart;
0791 uint32_t transfer_size = Size;
0792
0793 if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
0794 ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) ||
0795 ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U)))
0796 {
0797 hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
0798 return HAL_ERROR;
0799 }
0800
0801 if (hpssi->State == HAL_PSSI_STATE_READY)
0802 {
0803
0804 __HAL_LOCK(hpssi);
0805
0806 hpssi->State = HAL_PSSI_STATE_BUSY;
0807 hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
0808
0809
0810 HAL_PSSI_DISABLE(hpssi);
0811
0812 MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL),
0813 (PSSI_CR_OUTEN_INPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL)));
0814
0815 #if defined(HAL_DMA_MODULE_ENABLED)
0816
0817 hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
0818 #endif
0819
0820
0821 HAL_PSSI_ENABLE(hpssi);
0822 if (hpssi->Init.DataWidth == HAL_PSSI_8BITS)
0823 {
0824 uint8_t *pbuffer = pData;
0825
0826 while (transfer_size > 0U)
0827 {
0828
0829 tickstart = HAL_GetTick();
0830
0831 if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT1B, RESET, Timeout, tickstart) != HAL_OK)
0832 {
0833 hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
0834 hpssi->State = HAL_PSSI_STATE_READY;
0835
0836 __HAL_UNLOCK(hpssi);
0837 return HAL_ERROR;
0838 }
0839
0840 *pbuffer = *(__IO uint8_t *)(&hpssi->Instance->DR);
0841 pbuffer++;
0842 transfer_size--;
0843 }
0844 }
0845 else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS)
0846 {
0847 uint16_t *pbuffer = (uint16_t *)pData;
0848 __IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR);
0849
0850 while (transfer_size > 0U)
0851 {
0852
0853 tickstart = HAL_GetTick();
0854
0855 if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
0856 {
0857 hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
0858 hpssi->State = HAL_PSSI_STATE_READY;
0859
0860 __HAL_UNLOCK(hpssi);
0861 return HAL_ERROR;
0862 }
0863
0864
0865 *pbuffer = *dr;
0866 pbuffer++;
0867 transfer_size -= 2U;
0868 }
0869 }
0870 else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
0871 {
0872 uint32_t *pbuffer = (uint32_t *)pData;
0873
0874 while (transfer_size > 0U)
0875 {
0876
0877 tickstart = HAL_GetTick();
0878
0879 if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
0880 {
0881 hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
0882 hpssi->State = HAL_PSSI_STATE_READY;
0883
0884 __HAL_UNLOCK(hpssi);
0885 return HAL_ERROR;
0886 }
0887
0888
0889 *pbuffer = *(__IO uint32_t *)(&hpssi->Instance->DR);
0890 pbuffer++;
0891 transfer_size -= 4U;
0892 }
0893 }
0894 else
0895 {
0896 hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
0897 hpssi->State = HAL_PSSI_STATE_READY;
0898
0899 __HAL_UNLOCK(hpssi);
0900 return HAL_ERROR;
0901 }
0902
0903
0904 if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_RIS) != 0U)
0905 {
0906 HAL_PSSI_CLEAR_FLAG(hpssi, PSSI_FLAG_OVR_RIS);
0907 hpssi->ErrorCode = HAL_PSSI_ERROR_OVER_RUN;
0908 __HAL_UNLOCK(hpssi);
0909 return HAL_ERROR;
0910 }
0911
0912 hpssi->State = HAL_PSSI_STATE_READY;
0913
0914
0915 __HAL_UNLOCK(hpssi);
0916
0917 return HAL_OK;
0918 }
0919 else
0920 {
0921 return HAL_BUSY;
0922 }
0923 }
0924
0925 #if defined(HAL_DMA_MODULE_ENABLED)
0926
0927
0928
0929
0930
0931
0932
0933
0934 HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
0935 {
0936 HAL_StatusTypeDef dmaxferstatus;
0937
0938 if (hpssi->State == HAL_PSSI_STATE_READY)
0939 {
0940
0941
0942 __HAL_LOCK(hpssi);
0943
0944 hpssi->State = HAL_PSSI_STATE_BUSY_TX;
0945 hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
0946
0947
0948 HAL_PSSI_DISABLE(hpssi);
0949
0950
0951 hpssi->pBuffPtr = pData;
0952 hpssi->XferCount = Size;
0953
0954 if (hpssi->XferCount > PSSI_MAX_NBYTE_SIZE)
0955 {
0956 hpssi->XferSize = PSSI_MAX_NBYTE_SIZE;
0957 }
0958 else
0959 {
0960 hpssi->XferSize = hpssi->XferCount;
0961 }
0962
0963 if (hpssi->XferSize > 0U)
0964 {
0965 if (hpssi->hdmatx != NULL)
0966 {
0967
0968
0969 if (hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
0970 {
0971 MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
0972 PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT |
0973 ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
0974 }
0975 else
0976 {
0977 MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
0978 PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT |
0979 ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
0980 }
0981
0982
0983 hpssi->hdmatx->XferCpltCallback = PSSI_DMATransmitCplt;
0984
0985
0986 hpssi->hdmatx->XferErrorCallback = PSSI_DMAError;
0987
0988
0989 hpssi->hdmatx->XferHalfCpltCallback = NULL;
0990 hpssi->hdmatx->XferAbortCallback = NULL;
0991
0992
0993 dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmatx, (uint32_t)pData, (uint32_t)&hpssi->Instance->DR,
0994 hpssi->XferSize);
0995 }
0996 else
0997 {
0998
0999 hpssi->State = HAL_PSSI_STATE_READY;
1000
1001
1002 hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
1003
1004
1005 __HAL_UNLOCK(hpssi);
1006
1007 return HAL_ERROR;
1008 }
1009
1010 if (dmaxferstatus == HAL_OK)
1011 {
1012
1013 hpssi->XferCount -= hpssi->XferSize;
1014
1015
1016 __HAL_UNLOCK(hpssi);
1017
1018
1019
1020
1021
1022 HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
1023
1024
1025 hpssi->Instance->CR |= PSSI_CR_DMA_ENABLE;
1026
1027 HAL_PSSI_ENABLE(hpssi);
1028 }
1029 else
1030 {
1031
1032 hpssi->State = HAL_PSSI_STATE_READY;
1033
1034
1035 hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
1036
1037
1038 __HAL_UNLOCK(hpssi);
1039
1040 return HAL_ERROR;
1041 }
1042 }
1043 else
1044 {
1045
1046 __HAL_UNLOCK(hpssi);
1047
1048
1049
1050
1051
1052
1053
1054 HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
1055 }
1056 return HAL_OK;
1057 }
1058 else
1059 {
1060 return HAL_BUSY;
1061 }
1062 }
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072 HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
1073 {
1074
1075 HAL_StatusTypeDef dmaxferstatus;
1076
1077 if (hpssi->State == HAL_PSSI_STATE_READY)
1078 {
1079
1080
1081 HAL_PSSI_DISABLE(hpssi);
1082
1083 __HAL_LOCK(hpssi);
1084
1085 hpssi->State = HAL_PSSI_STATE_BUSY_RX;
1086 hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
1087
1088
1089 hpssi->pBuffPtr = pData;
1090 hpssi->XferCount = Size;
1091
1092 if (hpssi->XferCount > PSSI_MAX_NBYTE_SIZE)
1093 {
1094 hpssi->XferSize = PSSI_MAX_NBYTE_SIZE;
1095 }
1096 else
1097 {
1098 hpssi->XferSize = hpssi->XferCount;
1099 }
1100
1101 if (hpssi->XferSize > 0U)
1102 {
1103 if (hpssi->hdmarx != NULL)
1104 {
1105
1106 if (hpssi->hdmarx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
1107 {
1108 MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE |
1109 ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
1110 }
1111 else
1112 {
1113 MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
1114 PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth |
1115 ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
1116 }
1117
1118
1119 hpssi->hdmarx->XferCpltCallback = PSSI_DMAReceiveCplt;
1120
1121
1122 hpssi->hdmarx->XferErrorCallback = PSSI_DMAError;
1123
1124
1125 hpssi->hdmarx->XferHalfCpltCallback = NULL;
1126 hpssi->hdmarx->XferAbortCallback = NULL;
1127
1128
1129 dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmarx, (uint32_t)&hpssi->Instance->DR, (uint32_t)pData,
1130 hpssi->XferSize);
1131 }
1132 else
1133 {
1134
1135 hpssi->State = HAL_PSSI_STATE_READY;
1136
1137
1138 hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
1139
1140
1141 __HAL_UNLOCK(hpssi);
1142
1143 return HAL_ERROR;
1144 }
1145
1146 if (dmaxferstatus == HAL_OK)
1147 {
1148
1149 hpssi->XferCount -= hpssi->XferSize;
1150
1151
1152 __HAL_UNLOCK(hpssi);
1153
1154
1155
1156
1157
1158 HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
1159
1160
1161 hpssi->Instance->CR |= PSSI_CR_DMA_ENABLE;
1162
1163 HAL_PSSI_ENABLE(hpssi);
1164 }
1165 else
1166 {
1167
1168 hpssi->State = HAL_PSSI_STATE_READY;
1169
1170
1171 hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
1172
1173
1174 __HAL_UNLOCK(hpssi);
1175
1176 return HAL_ERROR;
1177 }
1178 }
1179 else
1180 {
1181
1182 __HAL_UNLOCK(hpssi);
1183
1184
1185 HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
1186 }
1187
1188 return HAL_OK;
1189 }
1190 else
1191 {
1192 return HAL_BUSY;
1193 }
1194 }
1195
1196
1197
1198
1199
1200
1201
1202 HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
1203 {
1204
1205 __HAL_LOCK(hpssi);
1206
1207
1208 HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
1209
1210
1211 hpssi->State = HAL_PSSI_STATE_ABORT;
1212
1213
1214 if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
1215 {
1216 if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
1217 {
1218 hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
1219
1220 if (hpssi->hdmatx != NULL)
1221 {
1222
1223
1224 hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
1225
1226
1227 if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
1228 {
1229
1230 hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
1231 }
1232 }
1233 }
1234
1235 else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
1236 {
1237 hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
1238
1239 if (hpssi->hdmarx != NULL)
1240 {
1241
1242
1243 hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
1244
1245
1246 if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
1247 {
1248
1249 hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
1250 }
1251 }
1252 }
1253 else
1254 {
1255
1256
1257 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
1258 hpssi->ErrorCallback(hpssi);
1259 #else
1260 HAL_PSSI_ErrorCallback(hpssi);
1261 #endif
1262 }
1263 }
1264
1265
1266 __HAL_UNLOCK(hpssi);
1267
1268
1269
1270
1271 HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
1272
1273 return HAL_OK;
1274 }
1275 #endif
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292 void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
1293 {
1294
1295 if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_MIS) != 0U)
1296 {
1297
1298 hpssi->XferCount = 0U;
1299
1300
1301 HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
1302
1303 #if defined(HAL_DMA_MODULE_ENABLED)
1304
1305 if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
1306 {
1307 if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
1308 {
1309
1310 hpssi->ErrorCode |= HAL_PSSI_ERROR_UNDER_RUN;
1311
1312 hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
1313
1314 if (hpssi->hdmatx != NULL)
1315 {
1316
1317
1318 hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
1319
1320
1321 __HAL_UNLOCK(hpssi);
1322
1323
1324 if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
1325 {
1326
1327 hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
1328 }
1329 }
1330 }
1331
1332 else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
1333 {
1334
1335 hpssi->ErrorCode |= HAL_PSSI_ERROR_OVER_RUN;
1336
1337 hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
1338
1339 if (hpssi->hdmarx != NULL)
1340 {
1341
1342
1343 hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
1344
1345
1346 __HAL_UNLOCK(hpssi);
1347
1348
1349 if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
1350 {
1351
1352 hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
1353 }
1354 }
1355 }
1356 else
1357 {
1358 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
1359
1360 hpssi->ErrorCallback(hpssi);
1361 #else
1362 HAL_PSSI_ErrorCallback(hpssi);
1363 #endif
1364 }
1365 }
1366 #endif
1367
1368
1369 if (hpssi->State == HAL_PSSI_STATE_ABORT)
1370 {
1371 hpssi->State = HAL_PSSI_STATE_READY;
1372
1373
1374 __HAL_UNLOCK(hpssi);
1375
1376 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
1377
1378 hpssi->AbortCpltCallback(hpssi);
1379 #else
1380 HAL_PSSI_AbortCpltCallback(hpssi);
1381 #endif
1382 }
1383 else
1384 {
1385
1386 hpssi->State = HAL_PSSI_STATE_READY;
1387
1388 __HAL_UNLOCK(hpssi);
1389
1390 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
1391
1392 hpssi->ErrorCallback(hpssi);
1393 #else
1394 HAL_PSSI_ErrorCallback(hpssi);
1395 #endif
1396 }
1397 }
1398 }
1399
1400
1401
1402
1403
1404
1405
1406 __weak void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi)
1407 {
1408
1409 UNUSED(hpssi);
1410
1411
1412
1413
1414 }
1415
1416
1417
1418
1419
1420
1421
1422 __weak void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi)
1423 {
1424
1425 UNUSED(hpssi);
1426
1427
1428
1429
1430 }
1431
1432
1433
1434
1435
1436
1437
1438 __weak void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi)
1439 {
1440
1441 UNUSED(hpssi);
1442
1443
1444
1445
1446 }
1447
1448
1449
1450
1451
1452
1453
1454 __weak void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi)
1455 {
1456
1457 UNUSED(hpssi);
1458
1459
1460
1461
1462 }
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490 HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi)
1491 {
1492
1493 return hpssi->State;
1494 }
1495
1496
1497
1498
1499
1500
1501
1502 uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi)
1503 {
1504 return hpssi->ErrorCode;
1505 }
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525 static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
1526 {
1527
1528 hpssi->XferCount = 0U;
1529
1530
1531 hpssi->ErrorCode |= ErrorCode;
1532
1533
1534 HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
1535
1536 #if defined(HAL_DMA_MODULE_ENABLED)
1537
1538 if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
1539 {
1540 if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
1541 {
1542 hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
1543
1544 if (hpssi->hdmatx != NULL)
1545 {
1546
1547
1548 hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
1549
1550
1551 __HAL_UNLOCK(hpssi);
1552
1553
1554 if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
1555 {
1556
1557 hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
1558 }
1559 }
1560 }
1561
1562 else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
1563 {
1564 hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
1565
1566 if (hpssi->hdmarx != NULL)
1567 {
1568
1569
1570 hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
1571
1572
1573 __HAL_UNLOCK(hpssi);
1574
1575
1576 if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
1577 {
1578
1579 hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
1580 }
1581 }
1582 }
1583 else
1584 {
1585
1586 }
1587 }
1588 #endif
1589
1590
1591 if (hpssi->State == HAL_PSSI_STATE_ABORT)
1592 {
1593 hpssi->State = HAL_PSSI_STATE_READY;
1594
1595
1596 __HAL_UNLOCK(hpssi);
1597
1598
1599 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
1600 hpssi->AbortCpltCallback(hpssi);
1601 #else
1602 HAL_PSSI_AbortCpltCallback(hpssi);
1603 #endif
1604 }
1605 else
1606 {
1607
1608 hpssi->State = HAL_PSSI_STATE_READY;
1609
1610
1611 __HAL_UNLOCK(hpssi);
1612
1613
1614 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
1615 hpssi->ErrorCallback(hpssi);
1616 #else
1617 HAL_PSSI_ErrorCallback(hpssi);
1618 #endif
1619 }
1620 }
1621
1622 #if defined(HAL_DMA_MODULE_ENABLED)
1623
1624
1625
1626
1627
1628 void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
1629 {
1630
1631 PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
1632
1633 uint32_t tmperror;
1634
1635
1636 HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
1637
1638
1639 tmperror = hpssi->ErrorCode;
1640
1641
1642 if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
1643 {
1644
1645 PSSI_Error(hpssi, hpssi->ErrorCode);
1646 }
1647
1648 else
1649 {
1650 hpssi->State = HAL_PSSI_STATE_READY;
1651
1652
1653 __HAL_UNLOCK(hpssi);
1654
1655
1656 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
1657 hpssi->TxCpltCallback(hpssi);
1658 #else
1659 HAL_PSSI_TxCpltCallback(hpssi);
1660 #endif
1661 }
1662 }
1663
1664
1665
1666
1667
1668
1669 void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
1670 {
1671
1672 PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
1673
1674 uint32_t tmperror;
1675
1676
1677 HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
1678
1679
1680 tmperror = hpssi->ErrorCode;
1681
1682
1683 if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
1684 {
1685
1686 PSSI_Error(hpssi, hpssi->ErrorCode);
1687 }
1688
1689 else
1690 {
1691 hpssi->State = HAL_PSSI_STATE_READY;
1692
1693
1694 __HAL_UNLOCK(hpssi);
1695
1696
1697 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
1698 hpssi->RxCpltCallback(hpssi);
1699 #else
1700 HAL_PSSI_RxCpltCallback(hpssi);
1701 #endif
1702 }
1703 }
1704
1705
1706
1707
1708
1709
1710
1711 void PSSI_DMAAbort(DMA_HandleTypeDef *hdma)
1712 {
1713
1714 PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
1715
1716
1717 hpssi->hdmatx->XferAbortCallback = NULL;
1718 hpssi->hdmarx->XferAbortCallback = NULL;
1719
1720
1721 if (hpssi->State == HAL_PSSI_STATE_ABORT)
1722 {
1723 hpssi->State = HAL_PSSI_STATE_READY;
1724
1725
1726 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
1727 hpssi->AbortCpltCallback(hpssi);
1728 #else
1729 HAL_PSSI_AbortCpltCallback(hpssi);
1730 #endif
1731 }
1732 else
1733 {
1734
1735 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
1736 hpssi->ErrorCallback(hpssi);
1737 #else
1738 HAL_PSSI_ErrorCallback(hpssi);
1739 #endif
1740 }
1741 }
1742 #endif
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754 static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status,
1755 uint32_t Timeout, uint32_t Tickstart)
1756 {
1757 while ((HAL_PSSI_GET_STATUS(hpssi, Flag) & Flag) == (uint32_t)Status)
1758 {
1759
1760 if (Timeout != HAL_MAX_DELAY)
1761 {
1762 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
1763 {
1764 hpssi->ErrorCode |= HAL_PSSI_ERROR_TIMEOUT;
1765 hpssi->State = HAL_PSSI_STATE_READY;
1766
1767
1768 __HAL_UNLOCK(hpssi);
1769
1770 return HAL_ERROR;
1771 }
1772 }
1773 }
1774 return HAL_OK;
1775 }
1776
1777 #if defined(HAL_DMA_MODULE_ENABLED)
1778 void PSSI_DMAError(DMA_HandleTypeDef *hdma)
1779 {
1780
1781 PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
1782
1783 uint32_t tmperror;
1784
1785
1786 HAL_PSSI_DISABLE(hpssi);
1787
1788
1789 HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
1790
1791
1792 tmperror = hpssi->ErrorCode;
1793
1794
1795 if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
1796 {
1797
1798 PSSI_Error(hpssi, hpssi->ErrorCode);
1799 }
1800 else
1801 {
1802 hpssi->State = HAL_PSSI_STATE_READY;
1803
1804
1805 __HAL_UNLOCK(hpssi);
1806
1807
1808 #if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
1809 hpssi->ErrorCallback(hpssi);
1810 #else
1811 HAL_PSSI_ErrorCallback(hpssi);
1812 #endif
1813 }
1814 }
1815 #endif
1816
1817
1818
1819
1820
1821 #endif
1822 #endif
1823
1824
1825
1826
1827
1828
1829