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0150 #include "stm32h7xx_hal.h"
0151
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0161
0162 #ifdef HAL_MDMA_MODULE_ENABLED
0163
0164
0165
0166
0167
0168
0169 #define HAL_TIMEOUT_MDMA_ABORT 5U
0170 #define HAL_MDMA_CHANNEL_SIZE 0x40U
0171
0172
0173
0174
0175
0176
0177
0178
0179
0180 static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
0181 static void MDMA_Init(MDMA_HandleTypeDef *hmdma);
0182
0183
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0217
0218
0219 HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma)
0220 {
0221 uint32_t tickstart = HAL_GetTick();
0222
0223
0224 if(hmdma == NULL)
0225 {
0226 return HAL_ERROR;
0227 }
0228
0229
0230 assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance));
0231 assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority));
0232 assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness));
0233 assert_param(IS_MDMA_REQUEST(hmdma->Init.Request));
0234 assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc));
0235 assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc));
0236 assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize));
0237 assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize));
0238 assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment));
0239 assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst));
0240 assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst));
0241 assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength));
0242 assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode));
0243 assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset));
0244 assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset));
0245
0246
0247
0248 __HAL_UNLOCK(hmdma);
0249
0250
0251 hmdma->State = HAL_MDMA_STATE_BUSY;
0252
0253
0254 __HAL_MDMA_DISABLE(hmdma);
0255
0256
0257 while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
0258 {
0259
0260 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
0261 {
0262
0263 hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT;
0264
0265
0266 hmdma->State = HAL_MDMA_STATE_ERROR;
0267
0268 return HAL_ERROR;
0269 }
0270 }
0271
0272
0273 MDMA_Init(hmdma);
0274
0275
0276 hmdma->FirstLinkedListNodeAddress = 0;
0277 hmdma->LastLinkedListNodeAddress = 0;
0278 hmdma->LinkedListNodeCounter = 0;
0279
0280
0281 hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
0282
0283
0284 hmdma->State = HAL_MDMA_STATE_READY;
0285
0286 return HAL_OK;
0287 }
0288
0289
0290
0291
0292
0293
0294
0295 HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma)
0296 {
0297
0298
0299 if(hmdma == NULL)
0300 {
0301 return HAL_ERROR;
0302 }
0303
0304
0305 __HAL_MDMA_DISABLE(hmdma);
0306
0307
0308 hmdma->Instance->CCR = 0;
0309 hmdma->Instance->CTCR = 0;
0310 hmdma->Instance->CBNDTR = 0;
0311 hmdma->Instance->CSAR = 0;
0312 hmdma->Instance->CDAR = 0;
0313 hmdma->Instance->CBRUR = 0;
0314 hmdma->Instance->CLAR = 0;
0315 hmdma->Instance->CTBR = 0;
0316 hmdma->Instance->CMAR = 0;
0317 hmdma->Instance->CMDR = 0;
0318
0319
0320 __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC));
0321
0322
0323 hmdma->FirstLinkedListNodeAddress = 0;
0324 hmdma->LastLinkedListNodeAddress = 0;
0325 hmdma->LinkedListNodeCounter = 0;
0326
0327
0328 hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
0329
0330
0331 hmdma->State = HAL_MDMA_STATE_RESET;
0332
0333
0334 __HAL_UNLOCK(hmdma);
0335
0336 return HAL_OK;
0337 }
0338
0339
0340
0341
0342
0343
0344
0345
0346
0347
0348 HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
0349 {
0350 HAL_StatusTypeDef status = HAL_OK;
0351
0352
0353 if(hmdma == NULL)
0354 {
0355 return HAL_ERROR;
0356 }
0357
0358
0359 __HAL_LOCK(hmdma);
0360
0361 if(HAL_MDMA_STATE_READY == hmdma->State)
0362 {
0363
0364 if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0U)
0365 {
0366
0367 hmdma->Instance->CMAR = MaskAddress;
0368 hmdma->Instance->CMDR = MaskData;
0369
0370
0371
0372
0373
0374
0375
0376 if(MaskAddress == 0U)
0377 {
0378 hmdma->Instance->CTCR &= ~MDMA_CTCR_BWM;
0379 }
0380 else
0381 {
0382 hmdma->Instance->CTCR |= MDMA_CTCR_BWM;
0383 }
0384 }
0385 else
0386 {
0387
0388 status = HAL_ERROR;
0389 }
0390 }
0391 else
0392 {
0393
0394 status = HAL_ERROR;
0395 }
0396
0397 __HAL_UNLOCK(hmdma);
0398
0399 return status;
0400 }
0401
0402
0403
0404
0405
0406
0407
0408
0409
0410 HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma))
0411 {
0412 HAL_StatusTypeDef status = HAL_OK;
0413
0414
0415 if(hmdma == NULL)
0416 {
0417 return HAL_ERROR;
0418 }
0419
0420
0421 __HAL_LOCK(hmdma);
0422
0423 if(HAL_MDMA_STATE_READY == hmdma->State)
0424 {
0425 switch (CallbackID)
0426 {
0427 case HAL_MDMA_XFER_CPLT_CB_ID:
0428 hmdma->XferCpltCallback = pCallback;
0429 break;
0430
0431 case HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
0432 hmdma->XferBufferCpltCallback = pCallback;
0433 break;
0434
0435 case HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
0436 hmdma->XferBlockCpltCallback = pCallback;
0437 break;
0438
0439 case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
0440 hmdma->XferRepeatBlockCpltCallback = pCallback;
0441 break;
0442
0443 case HAL_MDMA_XFER_ERROR_CB_ID:
0444 hmdma->XferErrorCallback = pCallback;
0445 break;
0446
0447 case HAL_MDMA_XFER_ABORT_CB_ID:
0448 hmdma->XferAbortCallback = pCallback;
0449 break;
0450
0451 default:
0452 break;
0453 }
0454 }
0455 else
0456 {
0457
0458 status = HAL_ERROR;
0459 }
0460
0461
0462 __HAL_UNLOCK(hmdma);
0463
0464 return status;
0465 }
0466
0467
0468
0469
0470
0471
0472
0473
0474
0475 HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
0476 {
0477 HAL_StatusTypeDef status = HAL_OK;
0478
0479
0480 if(hmdma == NULL)
0481 {
0482 return HAL_ERROR;
0483 }
0484
0485
0486 __HAL_LOCK(hmdma);
0487
0488 if(HAL_MDMA_STATE_READY == hmdma->State)
0489 {
0490 switch (CallbackID)
0491 {
0492 case HAL_MDMA_XFER_CPLT_CB_ID:
0493 hmdma->XferCpltCallback = NULL;
0494 break;
0495
0496 case HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
0497 hmdma->XferBufferCpltCallback = NULL;
0498 break;
0499
0500 case HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
0501 hmdma->XferBlockCpltCallback = NULL;
0502 break;
0503
0504 case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
0505 hmdma->XferRepeatBlockCpltCallback = NULL;
0506 break;
0507
0508 case HAL_MDMA_XFER_ERROR_CB_ID:
0509 hmdma->XferErrorCallback = NULL;
0510 break;
0511
0512 case HAL_MDMA_XFER_ABORT_CB_ID:
0513 hmdma->XferAbortCallback = NULL;
0514 break;
0515
0516 case HAL_MDMA_XFER_ALL_CB_ID:
0517 hmdma->XferCpltCallback = NULL;
0518 hmdma->XferBufferCpltCallback = NULL;
0519 hmdma->XferBlockCpltCallback = NULL;
0520 hmdma->XferRepeatBlockCpltCallback = NULL;
0521 hmdma->XferErrorCallback = NULL;
0522 hmdma->XferAbortCallback = NULL;
0523 break;
0524
0525 default:
0526 status = HAL_ERROR;
0527 break;
0528 }
0529 }
0530 else
0531 {
0532 status = HAL_ERROR;
0533 }
0534
0535
0536 __HAL_UNLOCK(hmdma);
0537
0538 return status;
0539 }
0540
0541
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0561
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0564
0565
0566
0567
0568
0569 HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
0570 {
0571 uint32_t addressMask;
0572 uint32_t blockoffset;
0573
0574
0575 if((pNode == NULL) || (pNodeConfig == NULL))
0576 {
0577 return HAL_ERROR;
0578 }
0579
0580
0581 assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority));
0582 assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness));
0583 assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request));
0584 assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc));
0585 assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc));
0586 assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize));
0587 assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize));
0588 assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment));
0589 assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst));
0590 assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst));
0591 assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength));
0592 assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode));
0593 assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset));
0594 assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset));
0595
0596 assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength));
0597 assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount));
0598
0599
0600
0601 pNode->CLAR = 0;
0602
0603
0604 pNode->CTBR = 0;
0605 pNode->CMAR = 0;
0606 pNode->CMDR = 0;
0607 pNode->Reserved = 0;
0608
0609
0610 pNode->CTCR = pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \
0611 pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \
0612 pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst | \
0613 pNodeConfig->Init.DestBurst | \
0614 ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
0615 pNodeConfig->Init.TransferTriggerMode;
0616
0617
0618 if(pNodeConfig->Init.Request == MDMA_REQUEST_SW)
0619 {
0620 pNode->CTCR |= MDMA_CTCR_SWRM;
0621 }
0622
0623
0624
0625
0626
0627
0628
0629 if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0U))
0630 {
0631 pNode->CTCR |= MDMA_CTCR_BWM;
0632 }
0633
0634
0635 pNode->CBNDTR = ((pNodeConfig->BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC;
0636
0637
0638 if(pNodeConfig->Init.SourceBlockAddressOffset < 0)
0639 {
0640 pNode->CBNDTR |= MDMA_CBNDTR_BRSUM;
0641
0642 blockoffset = (uint32_t)(- pNodeConfig->Init.SourceBlockAddressOffset);
0643 pNode->CBRUR = blockoffset & 0x0000FFFFU;
0644 }
0645 else
0646 {
0647
0648 pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
0649 }
0650
0651
0652 if(pNodeConfig->Init.DestBlockAddressOffset < 0)
0653 {
0654 pNode->CBNDTR |= MDMA_CBNDTR_BRDUM;
0655
0656 blockoffset = (uint32_t)(- pNodeConfig->Init.DestBlockAddressOffset);
0657 pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
0658 }
0659 else
0660 {
0661
0662 pNode->CBRUR |= ((((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
0663 }
0664
0665
0666 pNode->CBNDTR |= pNodeConfig->BlockDataLength;
0667
0668
0669 pNode->CDAR = pNodeConfig->DstAddress;
0670
0671
0672 pNode->CSAR = pNodeConfig->SrcAddress;
0673
0674
0675 if(pNodeConfig->Init.Request != MDMA_REQUEST_SW)
0676 {
0677
0678 pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL;
0679
0680 pNode->CMAR = pNodeConfig->PostRequestMaskAddress;
0681 pNode->CMDR = pNodeConfig->PostRequestMaskData;
0682 }
0683
0684 addressMask = pNodeConfig->SrcAddress & 0xFF000000U;
0685 if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
0686 {
0687
0688 pNode->CTBR |= MDMA_CTBR_SBUS;
0689 }
0690
0691 addressMask = pNodeConfig->DstAddress & 0xFF000000U;
0692 if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
0693 {
0694
0695 pNode->CTBR |= MDMA_CTBR_DBUS;
0696 }
0697
0698 return HAL_OK;
0699 }
0700
0701
0702
0703
0704
0705
0706
0707
0708
0709
0710
0711
0712 HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
0713 {
0714 MDMA_LinkNodeTypeDef *pNode;
0715 uint32_t counter = 0, nodeInserted = 0;
0716 HAL_StatusTypeDef hal_status = HAL_OK;
0717
0718
0719 if((hmdma == NULL) || (pNewNode == NULL))
0720 {
0721 return HAL_ERROR;
0722 }
0723
0724
0725 __HAL_LOCK(hmdma);
0726
0727 if(HAL_MDMA_STATE_READY == hmdma->State)
0728 {
0729
0730 hmdma->State = HAL_MDMA_STATE_BUSY;
0731
0732
0733 if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U)
0734 {
0735 if(pPrevNode == NULL)
0736 {
0737
0738
0739
0740 hmdma->Instance->CLAR = (uint32_t)pNewNode;
0741
0742 hmdma->FirstLinkedListNodeAddress = pNewNode;
0743
0744
0745 pNewNode->CLAR = 0;
0746
0747
0748 hmdma->LastLinkedListNodeAddress = pNewNode;
0749
0750 hmdma->LinkedListNodeCounter = 1;
0751 }
0752 else
0753 {
0754 hal_status = HAL_ERROR;
0755 }
0756 }
0757 else if(hmdma->FirstLinkedListNodeAddress != pNewNode)
0758 {
0759
0760 pNode = hmdma->FirstLinkedListNodeAddress;
0761 while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK))
0762 {
0763 if(pNode->CLAR == (uint32_t)pNewNode)
0764 {
0765 hal_status = HAL_ERROR;
0766 }
0767 pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
0768 counter++;
0769 }
0770
0771 if(hal_status == HAL_OK)
0772 {
0773
0774 if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == NULL))
0775 {
0776
0777 pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR;
0778 hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode;
0779
0780 hmdma->LastLinkedListNodeAddress = pNewNode;
0781
0782 hmdma->LinkedListNodeCounter++;
0783 }
0784 else
0785 {
0786
0787 pNode = hmdma->FirstLinkedListNodeAddress;
0788 counter = 0;
0789 while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0U))
0790 {
0791 counter++;
0792 if(pNode == pPrevNode)
0793 {
0794
0795 pNewNode->CLAR = pNode->CLAR;
0796 pNode->CLAR = (uint32_t)pNewNode;
0797
0798 hmdma->LinkedListNodeCounter++;
0799 nodeInserted = 1;
0800 }
0801 else
0802 {
0803 pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
0804 }
0805 }
0806
0807 if(nodeInserted == 0U)
0808 {
0809 hal_status = HAL_ERROR;
0810 }
0811 }
0812 }
0813 }
0814 else
0815 {
0816 hal_status = HAL_ERROR;
0817 }
0818
0819
0820 __HAL_UNLOCK(hmdma);
0821
0822 hmdma->State = HAL_MDMA_STATE_READY;
0823
0824 return hal_status;
0825 }
0826 else
0827 {
0828
0829 __HAL_UNLOCK(hmdma);
0830
0831
0832 return HAL_BUSY;
0833 }
0834 }
0835
0836
0837
0838
0839
0840
0841
0842
0843
0844
0845 HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
0846 {
0847 MDMA_LinkNodeTypeDef *ptmpNode;
0848 uint32_t counter = 0, nodeDeleted = 0;
0849 HAL_StatusTypeDef hal_status = HAL_OK;
0850
0851
0852 if((hmdma == NULL) || (pNode == NULL))
0853 {
0854 return HAL_ERROR;
0855 }
0856
0857
0858 __HAL_LOCK(hmdma);
0859
0860 if(HAL_MDMA_STATE_READY == hmdma->State)
0861 {
0862
0863 hmdma->State = HAL_MDMA_STATE_BUSY;
0864
0865
0866 if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
0867 {
0868 hal_status = HAL_ERROR;
0869 }
0870 else if(hmdma->FirstLinkedListNodeAddress == pNode)
0871 {
0872
0873 if(hmdma->LastLinkedListNodeAddress == pNode)
0874 {
0875
0876
0877
0878 hmdma->FirstLinkedListNodeAddress = 0;
0879 hmdma->LastLinkedListNodeAddress = 0;
0880 hmdma->LinkedListNodeCounter = 0;
0881
0882 hmdma->Instance->CLAR = 0;
0883 }
0884 else
0885 {
0886 if((uint32_t)hmdma->FirstLinkedListNodeAddress == hmdma->LastLinkedListNodeAddress->CLAR)
0887 {
0888
0889 hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR;
0890 }
0891
0892
0893
0894
0895 hmdma->Instance->CLAR = pNode->CLAR;
0896 hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR;
0897
0898 hmdma->LinkedListNodeCounter--;
0899 }
0900 }
0901 else
0902 {
0903
0904 ptmpNode = hmdma->FirstLinkedListNodeAddress;
0905 while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0U))
0906 {
0907 counter++;
0908 if(ptmpNode->CLAR == ((uint32_t)pNode))
0909 {
0910
0911 if(pNode == hmdma->LastLinkedListNodeAddress)
0912 {
0913
0914 hmdma->LastLinkedListNodeAddress = ptmpNode;
0915 }
0916
0917 ptmpNode->CLAR = pNode->CLAR;
0918 nodeDeleted = 1;
0919
0920 hmdma->LinkedListNodeCounter--;
0921 }
0922 else
0923 {
0924 ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR;
0925 }
0926 }
0927
0928 if(nodeDeleted == 0U)
0929 {
0930
0931 hal_status = HAL_ERROR;
0932 }
0933 }
0934
0935
0936 __HAL_UNLOCK(hmdma);
0937
0938 hmdma->State = HAL_MDMA_STATE_READY;
0939
0940 return hal_status;
0941 }
0942 else
0943 {
0944
0945 __HAL_UNLOCK(hmdma);
0946
0947
0948 return HAL_BUSY;
0949 }
0950 }
0951
0952
0953
0954
0955
0956
0957
0958 HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma)
0959 {
0960 HAL_StatusTypeDef hal_status = HAL_OK;
0961
0962
0963 if(hmdma == NULL)
0964 {
0965 return HAL_ERROR;
0966 }
0967
0968
0969 __HAL_LOCK(hmdma);
0970
0971 if(HAL_MDMA_STATE_READY == hmdma->State)
0972 {
0973
0974 hmdma->State = HAL_MDMA_STATE_BUSY;
0975
0976
0977 if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
0978 {
0979 hal_status = HAL_ERROR;
0980 }
0981 else
0982 {
0983
0984 hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
0985 }
0986
0987 }
0988
0989 __HAL_UNLOCK(hmdma);
0990
0991 hmdma->State = HAL_MDMA_STATE_READY;
0992
0993 return hal_status;
0994 }
0995
0996
0997
0998
0999
1000
1001
1002 HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma)
1003 {
1004 HAL_StatusTypeDef hal_status = HAL_OK;
1005
1006
1007 if(hmdma == NULL)
1008 {
1009 return HAL_ERROR;
1010 }
1011
1012
1013 __HAL_LOCK(hmdma);
1014
1015 if(HAL_MDMA_STATE_READY == hmdma->State)
1016 {
1017
1018 hmdma->State = HAL_MDMA_STATE_BUSY;
1019
1020
1021 if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
1022 {
1023 hal_status = HAL_ERROR;
1024 }
1025 else
1026 {
1027
1028 hmdma->LastLinkedListNodeAddress->CLAR = 0;
1029 }
1030
1031 }
1032
1033 __HAL_UNLOCK(hmdma);
1034
1035 hmdma->State = HAL_MDMA_STATE_READY;
1036
1037 return hal_status;
1038 }
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073 HAL_StatusTypeDef HAL_MDMA_Start(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
1074 {
1075
1076 assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
1077 assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
1078
1079
1080 if(hmdma == NULL)
1081 {
1082 return HAL_ERROR;
1083 }
1084
1085
1086 __HAL_LOCK(hmdma);
1087
1088 if(HAL_MDMA_STATE_READY == hmdma->State)
1089 {
1090
1091 hmdma->State = HAL_MDMA_STATE_BUSY;
1092
1093
1094 hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
1095
1096
1097 __HAL_MDMA_DISABLE(hmdma);
1098
1099
1100 MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
1101
1102
1103 __HAL_MDMA_ENABLE(hmdma);
1104
1105 if(hmdma->Init.Request == MDMA_REQUEST_SW)
1106 {
1107
1108 hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
1109 }
1110 }
1111 else
1112 {
1113
1114 __HAL_UNLOCK(hmdma);
1115
1116
1117 return HAL_BUSY;
1118 }
1119
1120 return HAL_OK;
1121 }
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133 HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
1134 {
1135
1136 assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
1137 assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
1138
1139
1140 if(hmdma == NULL)
1141 {
1142 return HAL_ERROR;
1143 }
1144
1145
1146 __HAL_LOCK(hmdma);
1147
1148 if(HAL_MDMA_STATE_READY == hmdma->State)
1149 {
1150
1151 hmdma->State = HAL_MDMA_STATE_BUSY;
1152
1153
1154 hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
1155
1156
1157 __HAL_MDMA_DISABLE(hmdma);
1158
1159
1160 MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
1161
1162
1163 __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC));
1164
1165 if(hmdma->XferBlockCpltCallback != NULL)
1166 {
1167
1168 __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT);
1169 }
1170
1171 if(hmdma->XferRepeatBlockCpltCallback != NULL)
1172 {
1173
1174 __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT);
1175 }
1176
1177 if(hmdma->XferBufferCpltCallback != NULL)
1178 {
1179
1180 __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC);
1181 }
1182
1183
1184 __HAL_MDMA_ENABLE(hmdma);
1185
1186 if(hmdma->Init.Request == MDMA_REQUEST_SW)
1187 {
1188
1189 hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
1190 }
1191 }
1192 else
1193 {
1194
1195 __HAL_UNLOCK(hmdma);
1196
1197
1198 return HAL_BUSY;
1199 }
1200
1201 return HAL_OK;
1202 }
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216 HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma)
1217 {
1218 uint32_t tickstart = HAL_GetTick();
1219
1220
1221 if(hmdma == NULL)
1222 {
1223 return HAL_ERROR;
1224 }
1225
1226 if(HAL_MDMA_STATE_BUSY != hmdma->State)
1227 {
1228 hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
1229
1230
1231 __HAL_UNLOCK(hmdma);
1232
1233 return HAL_ERROR;
1234 }
1235 else
1236 {
1237
1238 __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
1239
1240
1241 __HAL_MDMA_DISABLE(hmdma);
1242
1243
1244 while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
1245 {
1246
1247 if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
1248 {
1249
1250 hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
1251
1252
1253 __HAL_UNLOCK(hmdma);
1254
1255
1256 hmdma->State = HAL_MDMA_STATE_ERROR;
1257
1258 return HAL_ERROR;
1259 }
1260 }
1261
1262
1263 __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC));
1264
1265
1266 __HAL_UNLOCK(hmdma);
1267
1268
1269 hmdma->State = HAL_MDMA_STATE_READY;
1270 }
1271
1272 return HAL_OK;
1273 }
1274
1275
1276
1277
1278
1279
1280
1281 HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma)
1282 {
1283
1284 if(hmdma == NULL)
1285 {
1286 return HAL_ERROR;
1287 }
1288
1289 if(HAL_MDMA_STATE_BUSY != hmdma->State)
1290 {
1291
1292 hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
1293
1294 return HAL_ERROR;
1295 }
1296 else
1297 {
1298
1299 hmdma->State = HAL_MDMA_STATE_ABORT;
1300
1301
1302 __HAL_MDMA_DISABLE(hmdma);
1303 }
1304
1305 return HAL_OK;
1306 }
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316 HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
1317 {
1318 uint32_t levelFlag, errorFlag;
1319 uint32_t tickstart;
1320
1321
1322 assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel));
1323
1324
1325 if(hmdma == NULL)
1326 {
1327 return HAL_ERROR;
1328 }
1329
1330 if(HAL_MDMA_STATE_BUSY != hmdma->State)
1331 {
1332
1333 hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
1334
1335 return HAL_ERROR;
1336 }
1337
1338
1339 levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER) ? MDMA_FLAG_CTC : \
1340 (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \
1341 (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT : \
1342 MDMA_FLAG_BRT);
1343
1344
1345
1346 tickstart = HAL_GetTick();
1347
1348 while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == 0U)
1349 {
1350 if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
1351 {
1352
1353 errorFlag = hmdma->Instance->CESR;
1354
1355 if((errorFlag & MDMA_CESR_TED) == 0U)
1356 {
1357
1358 hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
1359 }
1360 else
1361 {
1362
1363 hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
1364 }
1365
1366 if((errorFlag & MDMA_CESR_TEMD) != 0U)
1367 {
1368
1369 hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
1370 }
1371
1372 if((errorFlag & MDMA_CESR_TELD) != 0U)
1373 {
1374
1375 hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
1376 }
1377
1378 if((errorFlag & MDMA_CESR_ASE) != 0U)
1379 {
1380
1381 hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
1382 }
1383
1384 if((errorFlag & MDMA_CESR_BSE) != 0U)
1385 {
1386
1387 hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
1388 }
1389
1390 (void) HAL_MDMA_Abort(hmdma);
1391
1392
1393
1394
1395
1396
1397
1398
1399 return HAL_ERROR;
1400
1401 }
1402
1403
1404 if(Timeout != HAL_MAX_DELAY)
1405 {
1406 if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
1407 {
1408
1409 hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
1410
1411 (void) HAL_MDMA_Abort(hmdma);
1412
1413
1414
1415
1416
1417
1418
1419
1420 return HAL_ERROR;
1421 }
1422 }
1423 }
1424
1425
1426 if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)
1427 {
1428 __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
1429
1430 }
1431 else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER)
1432 {
1433 __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT));
1434
1435 }
1436 else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER)
1437 {
1438 __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT));
1439 }
1440 else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER)
1441 {
1442 __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC));
1443
1444
1445 __HAL_UNLOCK(hmdma);
1446
1447 hmdma->State = HAL_MDMA_STATE_READY;
1448 }
1449 else
1450 {
1451 return HAL_ERROR;
1452 }
1453
1454 return HAL_OK;
1455 }
1456
1457
1458
1459
1460
1461
1462
1463 HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma)
1464 {
1465 uint32_t request_mode;
1466
1467
1468 if(hmdma == NULL)
1469 {
1470 return HAL_ERROR;
1471 }
1472
1473
1474 request_mode = hmdma->Instance->CTCR & MDMA_CTCR_SWRM;
1475
1476 if((hmdma->Instance->CCR & MDMA_CCR_EN) == 0U)
1477 {
1478
1479 hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
1480
1481 return HAL_ERROR;
1482 }
1483 else if(((hmdma->Instance->CISR & MDMA_CISR_CRQA) != 0U) || (request_mode == 0U))
1484 {
1485
1486 hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
1487
1488 return HAL_ERROR;
1489 }
1490 else
1491 {
1492
1493 hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
1494
1495 return HAL_OK;
1496 }
1497 }
1498
1499
1500
1501
1502
1503
1504
1505 void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
1506 {
1507 __IO uint32_t count = 0;
1508 uint32_t timeout = SystemCoreClock / 9600U;
1509
1510 uint32_t generalIntFlag, errorFlag;
1511
1512
1513 generalIntFlag = 1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE) & 0x1FU);
1514 if((MDMA->GISR0 & generalIntFlag) == 0U)
1515 {
1516 return;
1517 }
1518
1519
1520 if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
1521 {
1522 if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U)
1523 {
1524
1525 __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE);
1526
1527
1528 errorFlag = hmdma->Instance->CESR;
1529
1530 if((errorFlag & MDMA_CESR_TED) == 0U)
1531 {
1532
1533 hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
1534 }
1535 else
1536 {
1537
1538 hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
1539 }
1540
1541 if((errorFlag & MDMA_CESR_TEMD) != 0U)
1542 {
1543
1544 hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
1545 }
1546
1547 if((errorFlag & MDMA_CESR_TELD) != 0U)
1548 {
1549
1550 hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
1551 }
1552
1553 if((errorFlag & MDMA_CESR_ASE) != 0U)
1554 {
1555
1556 hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
1557 }
1558
1559 if((errorFlag & MDMA_CESR_BSE) != 0U)
1560 {
1561
1562 hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
1563 }
1564
1565
1566 __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
1567 }
1568 }
1569
1570
1571 if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U))
1572 {
1573 if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != 0U)
1574 {
1575
1576 __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
1577
1578 if(hmdma->XferBufferCpltCallback != NULL)
1579 {
1580
1581 hmdma->XferBufferCpltCallback(hmdma);
1582 }
1583 }
1584 }
1585
1586
1587 if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U))
1588 {
1589 if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != 0U)
1590 {
1591
1592 __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT);
1593
1594 if(hmdma->XferBlockCpltCallback != NULL)
1595 {
1596
1597 hmdma->XferBlockCpltCallback(hmdma);
1598 }
1599 }
1600 }
1601
1602
1603 if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U))
1604 {
1605 if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != 0U)
1606 {
1607
1608 __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT);
1609
1610 if(hmdma->XferRepeatBlockCpltCallback != NULL)
1611 {
1612
1613 hmdma->XferRepeatBlockCpltCallback(hmdma);
1614 }
1615 }
1616 }
1617
1618
1619 if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U))
1620 {
1621 if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != 0U)
1622 {
1623
1624 __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
1625
1626 if(HAL_MDMA_STATE_ABORT == hmdma->State)
1627 {
1628
1629 __HAL_UNLOCK(hmdma);
1630
1631
1632 hmdma->State = HAL_MDMA_STATE_READY;
1633
1634 if(hmdma->XferAbortCallback != NULL)
1635 {
1636 hmdma->XferAbortCallback(hmdma);
1637 }
1638 return;
1639 }
1640
1641
1642 __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC);
1643
1644
1645 __HAL_UNLOCK(hmdma);
1646
1647
1648 hmdma->State = HAL_MDMA_STATE_READY;
1649
1650 if(hmdma->XferCpltCallback != NULL)
1651 {
1652
1653 hmdma->XferCpltCallback(hmdma);
1654 }
1655 }
1656 }
1657
1658
1659 if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE)
1660 {
1661 hmdma->State = HAL_MDMA_STATE_ABORT;
1662
1663
1664 __HAL_MDMA_DISABLE(hmdma);
1665
1666 do
1667 {
1668 if (++count > timeout)
1669 {
1670 break;
1671 }
1672 }
1673 while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U);
1674
1675
1676 __HAL_UNLOCK(hmdma);
1677
1678 if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
1679 {
1680
1681 hmdma->State = HAL_MDMA_STATE_ERROR;
1682 }
1683 else
1684 {
1685
1686 hmdma->State = HAL_MDMA_STATE_READY;
1687 }
1688
1689
1690 if (hmdma->XferErrorCallback != NULL)
1691 {
1692
1693 hmdma->XferErrorCallback(hmdma);
1694 }
1695 }
1696 }
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723 HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma)
1724 {
1725 return hmdma->State;
1726 }
1727
1728
1729
1730
1731
1732
1733
1734 uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma)
1735 {
1736 return hmdma->ErrorCode;
1737 }
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761 static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
1762 {
1763 uint32_t addressMask;
1764
1765
1766 MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT));
1767
1768
1769 MODIFY_REG(hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC);
1770
1771
1772 __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF);
1773
1774
1775 hmdma->Instance->CDAR = DstAddress;
1776
1777
1778 hmdma->Instance->CSAR = SrcAddress;
1779
1780 addressMask = SrcAddress & 0xFF000000U;
1781 if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
1782 {
1783
1784 hmdma->Instance->CTBR |= MDMA_CTBR_SBUS;
1785 }
1786 else
1787 {
1788
1789 hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS);
1790 }
1791
1792 addressMask = DstAddress & 0xFF000000U;
1793 if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
1794 {
1795
1796 hmdma->Instance->CTBR |= MDMA_CTBR_DBUS;
1797 }
1798 else
1799 {
1800
1801 hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS);
1802 }
1803
1804
1805 hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
1806 }
1807
1808
1809
1810
1811
1812
1813
1814
1815 static void MDMA_Init(MDMA_HandleTypeDef *hmdma)
1816 {
1817 uint32_t blockoffset;
1818
1819
1820 hmdma->Instance->CCR = hmdma->Init.Priority | hmdma->Init.Endianness;
1821
1822
1823 hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \
1824 hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \
1825 hmdma->Init.DataAlignment | hmdma->Init.SourceBurst | \
1826 hmdma->Init.DestBurst | \
1827 ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
1828 hmdma->Init.TransferTriggerMode;
1829
1830
1831 if(hmdma->Init.Request == MDMA_REQUEST_SW)
1832 {
1833
1834
1835
1836
1837
1838
1839 hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM);
1840 }
1841
1842
1843 hmdma->Instance->CBNDTR = 0;
1844
1845
1846 if(hmdma->Init.SourceBlockAddressOffset < 0)
1847 {
1848 hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM;
1849
1850 blockoffset = (uint32_t)(- hmdma->Init.SourceBlockAddressOffset);
1851 hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU);
1852 }
1853 else
1854 {
1855
1856 hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
1857 }
1858
1859
1860 if(hmdma->Init.DestBlockAddressOffset < 0)
1861 {
1862 hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM;
1863
1864 blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset);
1865 hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
1866 }
1867 else
1868 {
1869
1870 hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
1871 }
1872
1873
1874 if(hmdma->Init.Request != MDMA_REQUEST_SW)
1875 {
1876
1877 hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL;
1878 }
1879 else
1880 {
1881 hmdma->Instance->CTBR = 0;
1882 }
1883
1884
1885 hmdma->Instance->CLAR = 0;
1886 }
1887
1888
1889
1890
1891
1892 #endif
1893
1894
1895
1896
1897
1898
1899
1900