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0360 #include "stm32h7xx_hal.h"
0361
0362
0363
0364
0365
0366 #ifdef HAL_HRTIM_MODULE_ENABLED
0367
0368 #if defined(HRTIM1)
0369
0370
0371
0372
0373
0374
0375
0376
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0380
0381
0382 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
0383 HRTIM_FLTR_FLT2EN |\
0384 HRTIM_FLTR_FLT3EN |\
0385 HRTIM_FLTR_FLT4EN | \
0386 HRTIM_FLTR_FLT5EN)
0387
0388 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
0389 HRTIM_TIMUPDATETRIGGER_TIMER_A |\
0390 HRTIM_TIMUPDATETRIGGER_TIMER_B |\
0391 HRTIM_TIMUPDATETRIGGER_TIMER_C |\
0392 HRTIM_TIMUPDATETRIGGER_TIMER_D |\
0393 HRTIM_TIMUPDATETRIGGER_TIMER_E)
0394
0395 #define HRTIM_FLTINR1_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
0396 (HRTIM_FAULTLOCK_READONLY << 8U) | \
0397 (HRTIM_FAULTLOCK_READONLY << 16U) | \
0398 (HRTIM_FAULTLOCK_READONLY << 24U))
0399
0400 #define HRTIM_FLTINR2_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
0401 (HRTIM_FAULTLOCK_READONLY << 8U))
0402
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0410
0411
0412 static uint32_t TimerIdxToTimerId[] =
0413 {
0414 HRTIM_TIMERID_TIMER_A,
0415 HRTIM_TIMERID_TIMER_B,
0416 HRTIM_TIMERID_TIMER_C,
0417 HRTIM_TIMERID_TIMER_D,
0418 HRTIM_TIMERID_TIMER_E,
0419 HRTIM_TIMERID_MASTER,
0420 };
0421
0422
0423
0424
0425
0426
0427
0428
0429
0430 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
0431 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
0432
0433 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
0434 uint32_t TimerIdx,
0435 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
0436
0437 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
0438 const HRTIM_TimerCfgTypeDef * pTimerCfg);
0439
0440 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
0441 uint32_t TimerIdx,
0442 const HRTIM_TimerCfgTypeDef * pTimerCfg);
0443
0444
0445 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
0446 uint32_t TimerIdx,
0447 uint32_t CaptureUnit,
0448 uint32_t Event);
0449
0450 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
0451 uint32_t TimerIdx,
0452 uint32_t Output,
0453 const HRTIM_OutputCfgTypeDef * pOutputCfg);
0454
0455 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
0456 uint32_t Event,
0457 const HRTIM_EventCfgTypeDef * pEventCfg);
0458
0459 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
0460 uint32_t TimerIdx,
0461 uint32_t Event);
0462
0463 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
0464 uint32_t TimerIdx,
0465 uint32_t OCChannel);
0466
0467 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
0468 uint32_t TimerIdx,
0469 uint32_t OCChannel);
0470
0471 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,
0472 uint32_t TimerIdx);
0473
0474 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,
0475 const DMA_HandleTypeDef * hdma);
0476
0477 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
0478 uint32_t TimerIdx);
0479
0480 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
0481
0482 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
0483
0484 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
0485 uint32_t TimerIdx);
0486
0487 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
0488
0489 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
0490
0491 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
0492
0493 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
0494
0495
0496
0497
0498
0499
0500
0501
0502
0503
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0506
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0525
0526
0527 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
0528 {
0529 uint8_t timer_idx;
0530 uint32_t hrtim_mcr;
0531
0532
0533 if(hhrtim == NULL)
0534 {
0535 return HAL_ERROR;
0536 }
0537
0538
0539 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
0540 assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
0541
0542 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
0543 if (hhrtim->State == HAL_HRTIM_STATE_RESET)
0544 {
0545
0546 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
0547 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
0548 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
0549 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
0550 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
0551 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
0552 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
0553 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
0554 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
0555 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
0556 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
0557 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
0558 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
0559 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
0560 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
0561 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
0562 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
0563 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
0564 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
0565 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
0566 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
0567 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
0568 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
0569 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
0570
0571 if (hhrtim->MspInitCallback == NULL)
0572 {
0573 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
0574 }
0575 }
0576 #endif
0577
0578
0579 hhrtim->State = HAL_HRTIM_STATE_BUSY;
0580
0581
0582 hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
0583 hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
0584 hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
0585 hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
0586 hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
0587 hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
0588
0589
0590 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET)
0591 {
0592
0593 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
0594 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
0595
0596
0597
0598
0599 if (hhrtim->Instance == HRTIM1)
0600 {
0601
0602 __HAL_RCC_HRTIM1_CLK_ENABLE();
0603 }
0604
0605 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
0606
0607
0608 hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
0609 hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
0610
0611
0612 hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
0613 hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
0614
0615
0616 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
0617 }
0618
0619
0620 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
0621 hhrtim->MspInitCallback(hhrtim);
0622 #else
0623 HAL_HRTIM_MspInit(hhrtim);
0624 #endif
0625
0626
0627 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET)
0628 {
0629
0630 assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
0631
0632 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
0633
0634
0635 hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
0636 hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
0637
0638
0639 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
0640 }
0641
0642
0643 hhrtim->State = HAL_HRTIM_STATE_READY;
0644
0645
0646 __HAL_UNLOCK(hhrtim);
0647
0648
0649 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
0650 timer_idx <= HRTIM_TIMERINDEX_MASTER ;
0651 timer_idx++)
0652 {
0653 hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
0654 hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
0655 hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
0656 hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
0657 hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
0658 hhrtim->TimerParam[timer_idx].DMASize = 0U;
0659 }
0660
0661 return HAL_OK;
0662 }
0663
0664
0665
0666
0667
0668
0669 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
0670 {
0671
0672 if(hhrtim == NULL)
0673 {
0674 return HAL_ERROR;
0675 }
0676
0677
0678 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
0679
0680
0681 hhrtim->State = HAL_HRTIM_STATE_BUSY;
0682
0683
0684 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
0685 if (hhrtim->MspDeInitCallback == NULL)
0686 {
0687 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
0688 }
0689
0690 hhrtim->MspDeInitCallback(hhrtim);
0691 #else
0692 HAL_HRTIM_MspDeInit(hhrtim);
0693 #endif
0694
0695 hhrtim->State = HAL_HRTIM_STATE_READY;
0696
0697 return HAL_OK;
0698 }
0699
0700
0701
0702
0703
0704
0705 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
0706 {
0707
0708 UNUSED(hhrtim);
0709
0710
0711
0712
0713 }
0714
0715
0716
0717
0718
0719
0720 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
0721 {
0722
0723 UNUSED(hhrtim);
0724
0725
0726
0727
0728 }
0729
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0749
0750 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
0751 uint32_t TimerIdx,
0752 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
0753 {
0754
0755 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
0756 assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
0757 assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
0758
0759 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
0760 {
0761 return HAL_BUSY;
0762 }
0763
0764
0765 hhrtim->State = HAL_HRTIM_STATE_BUSY;
0766
0767 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
0768 {
0769
0770 HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
0771 }
0772 else
0773 {
0774
0775 HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
0776 }
0777
0778
0779 hhrtim->State = HAL_HRTIM_STATE_READY;
0780
0781 return HAL_OK;
0782 }
0783
0784
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0791
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0820
0821
0822 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
0823 uint32_t TimerIdx)
0824 {
0825
0826 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
0827
0828
0829 __HAL_LOCK(hhrtim);
0830
0831 hhrtim->State = HAL_HRTIM_STATE_BUSY;
0832
0833
0834 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
0835
0836 hhrtim->State = HAL_HRTIM_STATE_READY;
0837
0838
0839 __HAL_UNLOCK(hhrtim);
0840
0841 return HAL_OK;
0842 }
0843
0844
0845
0846
0847
0848
0849
0850
0851
0852
0853
0854
0855
0856
0857 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
0858 uint32_t TimerIdx)
0859 {
0860
0861 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
0862
0863
0864 __HAL_LOCK(hhrtim);
0865
0866 hhrtim->State = HAL_HRTIM_STATE_BUSY;
0867
0868
0869 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
0870
0871 hhrtim->State = HAL_HRTIM_STATE_READY;
0872
0873
0874 __HAL_UNLOCK(hhrtim);
0875
0876 return HAL_OK;
0877 }
0878
0879
0880
0881
0882
0883
0884
0885
0886
0887
0888
0889
0890
0891
0892
0893 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
0894 uint32_t TimerIdx)
0895 {
0896
0897 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
0898
0899
0900 __HAL_LOCK(hhrtim);
0901
0902 hhrtim->State = HAL_HRTIM_STATE_BUSY;
0903
0904
0905 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
0906 {
0907 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
0908 }
0909 else
0910 {
0911 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
0912 }
0913
0914
0915 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
0916
0917 hhrtim->State = HAL_HRTIM_STATE_READY;
0918
0919
0920 __HAL_UNLOCK(hhrtim);
0921
0922 return HAL_OK;
0923 }
0924
0925
0926
0927
0928
0929
0930
0931
0932
0933
0934
0935
0936
0937
0938
0939 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
0940 uint32_t TimerIdx)
0941 {
0942
0943 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
0944
0945
0946 __HAL_LOCK(hhrtim);
0947
0948 hhrtim->State = HAL_HRTIM_STATE_BUSY;
0949
0950
0951 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
0952 {
0953 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
0954 }
0955 else
0956 {
0957 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
0958 }
0959
0960
0961 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
0962
0963 hhrtim->State = HAL_HRTIM_STATE_READY;
0964
0965
0966 __HAL_UNLOCK(hhrtim);
0967
0968 return HAL_OK;
0969 }
0970
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0972
0973
0974
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0976
0977
0978
0979
0980
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0985
0986
0987
0988 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
0989 uint32_t TimerIdx,
0990 uint32_t SrcAddr,
0991 uint32_t DestAddr,
0992 uint32_t Length)
0993 {
0994 DMA_HandleTypeDef * hdma;
0995
0996
0997 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
0998
0999 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1000 {
1001 return HAL_BUSY;
1002 }
1003 if(hhrtim->State == HAL_HRTIM_STATE_READY)
1004 {
1005 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1006 {
1007 return HAL_ERROR;
1008 }
1009 else
1010 {
1011 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1012 }
1013 }
1014
1015
1016 __HAL_LOCK(hhrtim);
1017
1018
1019 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1020
1021 if (hdma == NULL)
1022 {
1023 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1024
1025
1026 __HAL_UNLOCK(hhrtim);
1027
1028 return HAL_ERROR;
1029 }
1030
1031
1032 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1033 {
1034 hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
1035 }
1036 else
1037 {
1038 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1039 }
1040
1041
1042 hdma->XferErrorCallback = HRTIM_DMAError ;
1043
1044
1045 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1046 {
1047 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1048
1049
1050 __HAL_UNLOCK(hhrtim);
1051
1052 return HAL_ERROR;
1053 }
1054
1055
1056 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1057 {
1058 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1059 }
1060 else
1061 {
1062 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1063 }
1064
1065
1066 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1067
1068 hhrtim->State = HAL_HRTIM_STATE_READY;
1069
1070
1071 __HAL_UNLOCK(hhrtim);
1072
1073 return HAL_OK;
1074 }
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1091 uint32_t TimerIdx)
1092 {
1093 DMA_HandleTypeDef * hdma;
1094
1095
1096 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1097
1098
1099 __HAL_LOCK(hhrtim);
1100
1101 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1102 {
1103 hhrtim->State = HAL_HRTIM_STATE_READY;
1104
1105
1106 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
1107 {
1108 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1109 }
1110
1111 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1112 }
1113 else
1114 {
1115
1116 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1117
1118 if (hdma == NULL)
1119 {
1120 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1121 }
1122 else
1123 {
1124 hhrtim->State = HAL_HRTIM_STATE_READY;
1125
1126
1127 if (HAL_DMA_Abort(hdma) != HAL_OK)
1128 {
1129 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1130 }
1131
1132
1133 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1134 }
1135 }
1136
1137
1138 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1139
1140
1141 __HAL_UNLOCK(hhrtim);
1142
1143 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1144 {
1145 return HAL_ERROR;
1146 }
1147 else
1148 {
1149 return HAL_OK;
1150 }
1151 }
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1214 uint32_t TimerIdx,
1215 uint32_t OCChannel,
1216 const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
1217 {
1218 uint32_t CompareUnit = (uint32_t)RESET;
1219 HRTIM_OutputCfgTypeDef OutputCfg;
1220
1221
1222 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1223 assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
1224 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOCChannelCfg->Pulse));
1225 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
1226 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
1227
1228 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1229 {
1230 return HAL_BUSY;
1231 }
1232
1233
1234 __HAL_LOCK(hhrtim);
1235
1236
1237 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1238
1239
1240 switch (OCChannel)
1241 {
1242 case HRTIM_OUTPUT_TA1:
1243 case HRTIM_OUTPUT_TB1:
1244 case HRTIM_OUTPUT_TC1:
1245 case HRTIM_OUTPUT_TD1:
1246 case HRTIM_OUTPUT_TE1:
1247 {
1248 CompareUnit = HRTIM_COMPAREUNIT_1;
1249 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse;
1250 break;
1251 }
1252 case HRTIM_OUTPUT_TA2:
1253 case HRTIM_OUTPUT_TB2:
1254 case HRTIM_OUTPUT_TC2:
1255 case HRTIM_OUTPUT_TD2:
1256 case HRTIM_OUTPUT_TE2:
1257 {
1258 CompareUnit = HRTIM_COMPAREUNIT_2;
1259 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse;
1260 break;
1261 }
1262 default:
1263 {
1264 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1265
1266
1267 __HAL_UNLOCK(hhrtim);
1268
1269 break;
1270 }
1271 }
1272
1273 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1274 {
1275 return HAL_ERROR;
1276 }
1277
1278
1279 OutputCfg.Polarity = (pSimpleOCChannelCfg->Polarity & HRTIM_OUTR_POL1);
1280 OutputCfg.IdleLevel = (pSimpleOCChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
1281 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1282 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1283 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1284 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1285
1286 switch (pSimpleOCChannelCfg->Mode)
1287 {
1288 case HRTIM_BASICOCMODE_TOGGLE:
1289 {
1290 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1291 {
1292 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1293 }
1294 else
1295 {
1296 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1297 }
1298 OutputCfg.ResetSource = OutputCfg.SetSource;
1299 break;
1300 }
1301
1302 case HRTIM_BASICOCMODE_ACTIVE:
1303 {
1304 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1305 {
1306 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1307 }
1308 else
1309 {
1310 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1311 }
1312 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1313 break;
1314 }
1315
1316 case HRTIM_BASICOCMODE_INACTIVE:
1317 {
1318 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1319 {
1320 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
1321 }
1322 else
1323 {
1324 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
1325 }
1326 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1327 break;
1328 }
1329
1330 default:
1331 {
1332 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1333 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1334
1335 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1336
1337
1338 __HAL_UNLOCK(hhrtim);
1339
1340 break;
1341 }
1342 }
1343
1344 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1345 {
1346 return HAL_ERROR;
1347 }
1348
1349 HRTIM_OutputConfig(hhrtim,
1350 TimerIdx,
1351 OCChannel,
1352 &OutputCfg);
1353
1354
1355 hhrtim->State = HAL_HRTIM_STATE_READY;
1356
1357
1358 __HAL_UNLOCK(hhrtim);
1359
1360 return HAL_OK;
1361 }
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
1388 uint32_t TimerIdx,
1389 uint32_t OCChannel)
1390 {
1391
1392 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1393
1394
1395 __HAL_LOCK(hhrtim);
1396
1397 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1398
1399
1400 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1401
1402
1403 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1404
1405 hhrtim->State = HAL_HRTIM_STATE_READY;
1406
1407
1408 __HAL_UNLOCK(hhrtim);
1409
1410 return HAL_OK;
1411 }
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
1438 uint32_t TimerIdx,
1439 uint32_t OCChannel)
1440 {
1441
1442 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1443
1444
1445 __HAL_LOCK(hhrtim);
1446
1447 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1448
1449
1450 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1451
1452
1453 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1454
1455 hhrtim->State = HAL_HRTIM_STATE_READY;
1456
1457
1458 __HAL_UNLOCK(hhrtim);
1459
1460 return HAL_OK;
1461 }
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
1493 uint32_t TimerIdx,
1494 uint32_t OCChannel)
1495 {
1496 uint32_t interrupt;
1497
1498
1499 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1500
1501
1502 __HAL_LOCK(hhrtim);
1503
1504 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1505
1506
1507 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1508
1509
1510 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1511
1512
1513 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
1514
1515
1516 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1517
1518 hhrtim->State = HAL_HRTIM_STATE_READY;
1519
1520
1521 __HAL_UNLOCK(hhrtim);
1522
1523 return HAL_OK;
1524 }
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
1552 uint32_t TimerIdx,
1553 uint32_t OCChannel)
1554 {
1555 uint32_t interrupt;
1556
1557
1558 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1559
1560
1561 __HAL_LOCK(hhrtim);
1562
1563 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1564
1565
1566 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1567
1568
1569 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1570
1571
1572 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
1573
1574
1575 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1576
1577 hhrtim->State = HAL_HRTIM_STATE_READY;
1578
1579
1580 __HAL_UNLOCK(hhrtim);
1581
1582 return HAL_OK;
1583 }
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1619 uint32_t TimerIdx,
1620 uint32_t OCChannel,
1621 uint32_t SrcAddr,
1622 uint32_t DestAddr,
1623 uint32_t Length)
1624 {
1625 DMA_HandleTypeDef * hdma;
1626 uint32_t dma_request;
1627
1628
1629 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1630
1631 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1632 {
1633 return HAL_BUSY;
1634 }
1635 if(hhrtim->State == HAL_HRTIM_STATE_READY)
1636 {
1637 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1638 {
1639 return HAL_ERROR;
1640 }
1641 else
1642 {
1643 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1644 }
1645 }
1646
1647
1648 __HAL_LOCK(hhrtim);
1649
1650
1651 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1652
1653
1654 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1655
1656
1657 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1658
1659 if (hdma == NULL)
1660 {
1661 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1662
1663
1664 __HAL_UNLOCK(hhrtim);
1665
1666 return HAL_ERROR;
1667 }
1668
1669
1670 hdma->XferErrorCallback = HRTIM_DMAError ;
1671
1672
1673 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1674
1675
1676 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1677 {
1678 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1679
1680
1681 __HAL_UNLOCK(hhrtim);
1682
1683 return HAL_ERROR;
1684 }
1685
1686
1687 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
1688
1689
1690 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1691
1692 hhrtim->State = HAL_HRTIM_STATE_READY;
1693
1694
1695 __HAL_UNLOCK(hhrtim);
1696
1697 return HAL_OK;
1698 }
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1726 uint32_t TimerIdx,
1727 uint32_t OCChannel)
1728 {
1729 uint32_t dma_request;
1730
1731
1732 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1733
1734
1735 __HAL_LOCK(hhrtim);
1736
1737 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1738
1739
1740 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1741
1742
1743
1744 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
1745 {
1746 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1747
1748
1749 __HAL_UNLOCK(hhrtim);
1750
1751 return HAL_ERROR;
1752 }
1753
1754
1755 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1756
1757
1758 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
1759
1760
1761 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1762
1763 hhrtim->State = HAL_HRTIM_STATE_READY;
1764
1765
1766 __HAL_UNLOCK(hhrtim);
1767
1768 return HAL_OK;
1769 }
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1835 uint32_t TimerIdx,
1836 uint32_t PWMChannel,
1837 const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
1838 {
1839 HRTIM_OutputCfgTypeDef OutputCfg;
1840 uint32_t hrtim_timcr;
1841
1842
1843 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1844 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
1845 assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse));
1846 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
1847
1848 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1849 {
1850 return HAL_BUSY;
1851 }
1852
1853
1854 __HAL_LOCK(hhrtim);
1855
1856 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1857
1858
1859 switch (PWMChannel)
1860 {
1861 case HRTIM_OUTPUT_TA1:
1862 case HRTIM_OUTPUT_TB1:
1863 case HRTIM_OUTPUT_TC1:
1864 case HRTIM_OUTPUT_TD1:
1865 case HRTIM_OUTPUT_TE1:
1866 {
1867 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse;
1868 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1869 break;
1870 }
1871
1872 case HRTIM_OUTPUT_TA2:
1873 case HRTIM_OUTPUT_TB2:
1874 case HRTIM_OUTPUT_TC2:
1875 case HRTIM_OUTPUT_TD2:
1876 case HRTIM_OUTPUT_TE2:
1877 {
1878 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse;
1879 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1880 break;
1881 }
1882 default:
1883 {
1884 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1885 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1886
1887 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1888
1889
1890 __HAL_UNLOCK(hhrtim);
1891
1892 break;
1893 }
1894 }
1895
1896 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1897 {
1898 return HAL_ERROR;
1899 }
1900
1901
1902 OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1);
1903 OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1);
1904 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1905 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1906 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1907 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1908 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
1909
1910 HRTIM_OutputConfig(hhrtim,
1911 TimerIdx,
1912 PWMChannel,
1913 &OutputCfg);
1914
1915
1916 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
1917 hrtim_timcr |= HRTIM_TIMCR_PREEN;
1918 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
1919
1920 hhrtim->State = HAL_HRTIM_STATE_READY;
1921
1922
1923 __HAL_UNLOCK(hhrtim);
1924
1925 return HAL_OK;
1926 }
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
1953 uint32_t TimerIdx,
1954 uint32_t PWMChannel)
1955 {
1956
1957 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1958
1959
1960 __HAL_LOCK(hhrtim);
1961
1962 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1963
1964
1965 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
1966
1967
1968 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1969
1970 hhrtim->State = HAL_HRTIM_STATE_READY;
1971
1972
1973 __HAL_UNLOCK(hhrtim);
1974
1975 return HAL_OK;
1976 }
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
2003 uint32_t TimerIdx,
2004 uint32_t PWMChannel)
2005 {
2006
2007 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2008
2009
2010 __HAL_LOCK(hhrtim);
2011
2012 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2013
2014
2015 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2016
2017
2018 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2019
2020 hhrtim->State = HAL_HRTIM_STATE_READY;
2021
2022
2023 __HAL_UNLOCK(hhrtim);
2024
2025 return HAL_OK;
2026 }
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
2054 uint32_t TimerIdx,
2055 uint32_t PWMChannel)
2056 {
2057
2058 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2059
2060
2061 __HAL_LOCK(hhrtim);
2062
2063 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2064
2065
2066 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2067
2068
2069 switch (PWMChannel)
2070 {
2071 case HRTIM_OUTPUT_TA1:
2072 case HRTIM_OUTPUT_TB1:
2073 case HRTIM_OUTPUT_TC1:
2074 case HRTIM_OUTPUT_TD1:
2075 case HRTIM_OUTPUT_TE1:
2076 {
2077 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2078 break;
2079 }
2080
2081 case HRTIM_OUTPUT_TA2:
2082 case HRTIM_OUTPUT_TB2:
2083 case HRTIM_OUTPUT_TC2:
2084 case HRTIM_OUTPUT_TD2:
2085 case HRTIM_OUTPUT_TE2:
2086 {
2087 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2088 break;
2089 }
2090
2091 default:
2092 {
2093 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2094
2095
2096 __HAL_UNLOCK(hhrtim);
2097
2098 break;
2099 }
2100 }
2101
2102 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2103 {
2104 return HAL_ERROR;
2105 }
2106
2107
2108 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2109
2110 hhrtim->State = HAL_HRTIM_STATE_READY;
2111
2112
2113 __HAL_UNLOCK(hhrtim);
2114
2115 return HAL_OK;
2116 }
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
2144 uint32_t TimerIdx,
2145 uint32_t PWMChannel)
2146 {
2147
2148 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2149
2150
2151 __HAL_LOCK(hhrtim);
2152
2153 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2154
2155
2156 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2157
2158
2159 switch (PWMChannel)
2160 {
2161 case HRTIM_OUTPUT_TA1:
2162 case HRTIM_OUTPUT_TB1:
2163 case HRTIM_OUTPUT_TC1:
2164 case HRTIM_OUTPUT_TD1:
2165 case HRTIM_OUTPUT_TE1:
2166 {
2167 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2168 break;
2169 }
2170
2171 case HRTIM_OUTPUT_TA2:
2172 case HRTIM_OUTPUT_TB2:
2173 case HRTIM_OUTPUT_TC2:
2174 case HRTIM_OUTPUT_TD2:
2175 case HRTIM_OUTPUT_TE2:
2176 {
2177 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2178 break;
2179 }
2180
2181 default:
2182 {
2183 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2184
2185
2186 __HAL_UNLOCK(hhrtim);
2187
2188 break;
2189 }
2190 }
2191
2192 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2193 {
2194 return HAL_ERROR;
2195 }
2196
2197
2198 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2199
2200 hhrtim->State = HAL_HRTIM_STATE_READY;
2201
2202
2203 __HAL_UNLOCK(hhrtim);
2204
2205 return HAL_OK;
2206 }
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2238 uint32_t TimerIdx,
2239 uint32_t PWMChannel,
2240 uint32_t SrcAddr,
2241 uint32_t DestAddr,
2242 uint32_t Length)
2243 {
2244 DMA_HandleTypeDef * hdma;
2245
2246
2247 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2248
2249 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2250 {
2251 return HAL_BUSY;
2252 }
2253 if(hhrtim->State == HAL_HRTIM_STATE_READY)
2254 {
2255 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
2256 {
2257 return HAL_ERROR;
2258 }
2259 else
2260 {
2261 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2262 }
2263 }
2264
2265
2266 __HAL_LOCK(hhrtim);
2267
2268
2269 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2270
2271
2272 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2273
2274 if (hdma == NULL)
2275 {
2276 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2277
2278
2279 __HAL_UNLOCK(hhrtim);
2280
2281 return HAL_ERROR;
2282 }
2283
2284
2285 hdma->XferErrorCallback = HRTIM_DMAError ;
2286
2287
2288 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2289
2290
2291 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
2292 {
2293 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2294
2295
2296 __HAL_UNLOCK(hhrtim);
2297
2298 return HAL_ERROR;
2299 }
2300
2301
2302 switch (PWMChannel)
2303 {
2304 case HRTIM_OUTPUT_TA1:
2305 case HRTIM_OUTPUT_TB1:
2306 case HRTIM_OUTPUT_TC1:
2307 case HRTIM_OUTPUT_TD1:
2308 case HRTIM_OUTPUT_TE1:
2309 {
2310 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2311 break;
2312 }
2313
2314 case HRTIM_OUTPUT_TA2:
2315 case HRTIM_OUTPUT_TB2:
2316 case HRTIM_OUTPUT_TC2:
2317 case HRTIM_OUTPUT_TD2:
2318 case HRTIM_OUTPUT_TE2:
2319 {
2320 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2321 break;
2322 }
2323
2324 default:
2325 {
2326 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2327
2328
2329 __HAL_UNLOCK(hhrtim);
2330
2331 break;
2332 }
2333 }
2334
2335 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2336 {
2337 return HAL_ERROR;
2338 }
2339
2340
2341 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2342
2343 hhrtim->State = HAL_HRTIM_STATE_READY;
2344
2345
2346 __HAL_UNLOCK(hhrtim);
2347
2348 return HAL_OK;
2349 }
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
2377 uint32_t TimerIdx,
2378 uint32_t PWMChannel)
2379 {
2380
2381 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2382
2383
2384 __HAL_LOCK(hhrtim);
2385
2386 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2387
2388
2389 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2390
2391
2392
2393 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
2394 {
2395 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2396
2397
2398 __HAL_UNLOCK(hhrtim);
2399
2400 return HAL_ERROR;
2401 }
2402
2403
2404 switch (PWMChannel)
2405 {
2406 case HRTIM_OUTPUT_TA1:
2407 case HRTIM_OUTPUT_TB1:
2408 case HRTIM_OUTPUT_TC1:
2409 case HRTIM_OUTPUT_TD1:
2410 case HRTIM_OUTPUT_TE1:
2411 {
2412 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2413 break;
2414 }
2415
2416 case HRTIM_OUTPUT_TA2:
2417 case HRTIM_OUTPUT_TB2:
2418 case HRTIM_OUTPUT_TC2:
2419 case HRTIM_OUTPUT_TD2:
2420 case HRTIM_OUTPUT_TE2:
2421 {
2422 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2423 break;
2424 }
2425
2426 default:
2427 {
2428 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2429
2430
2431 __HAL_UNLOCK(hhrtim);
2432
2433 break;
2434 }
2435 }
2436
2437 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2438 {
2439 return HAL_ERROR;
2440 }
2441
2442
2443 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2444
2445 hhrtim->State = HAL_HRTIM_STATE_READY;
2446
2447
2448 __HAL_UNLOCK(hhrtim);
2449
2450 return HAL_OK;
2451 }
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
2502 uint32_t TimerIdx,
2503 uint32_t CaptureChannel,
2504 const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
2505 {
2506 HRTIM_EventCfgTypeDef EventCfg;
2507
2508
2509 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2510 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2511 assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
2512 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
2513 pSimpleCaptureChannelCfg->EventPolarity));
2514 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
2515 assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
2516 pSimpleCaptureChannelCfg->EventFilter));
2517
2518 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2519 {
2520 return HAL_BUSY;
2521 }
2522
2523
2524 __HAL_LOCK(hhrtim);
2525
2526 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2527
2528
2529 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
2530 EventCfg.Filter = (pSimpleCaptureChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
2531 EventCfg.Polarity = (pSimpleCaptureChannelCfg->EventPolarity & HRTIM_EECR1_EE1POL);
2532 EventCfg.Sensitivity = (pSimpleCaptureChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
2533 EventCfg.Source = HRTIM_EVENTSRC_1;
2534
2535 HRTIM_EventConfig(hhrtim,
2536 pSimpleCaptureChannelCfg->Event,
2537 &EventCfg);
2538
2539
2540 HRTIM_CaptureUnitConfig(hhrtim,
2541 TimerIdx,
2542 CaptureChannel,
2543 pSimpleCaptureChannelCfg->Event);
2544
2545 hhrtim->State = HAL_HRTIM_STATE_READY;
2546
2547
2548 __HAL_UNLOCK(hhrtim);
2549
2550 return HAL_OK;
2551 }
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
2573 uint32_t TimerIdx,
2574 uint32_t CaptureChannel)
2575 {
2576
2577 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2578 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2579
2580
2581 __HAL_LOCK(hhrtim);
2582
2583 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2584
2585
2586 switch (CaptureChannel)
2587 {
2588 case HRTIM_CAPTUREUNIT_1:
2589 {
2590 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2591 break;
2592 }
2593
2594 case HRTIM_CAPTUREUNIT_2:
2595 {
2596 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2597 break;
2598 }
2599
2600 default:
2601 {
2602 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2603
2604
2605 __HAL_UNLOCK(hhrtim);
2606
2607 break;
2608 }
2609 }
2610
2611 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2612 {
2613 return HAL_ERROR;
2614 }
2615
2616
2617 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2618
2619 hhrtim->State = HAL_HRTIM_STATE_READY;
2620
2621
2622 __HAL_UNLOCK(hhrtim);
2623
2624 return HAL_OK;
2625 }
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
2644 uint32_t TimerIdx,
2645 uint32_t CaptureChannel)
2646 {
2647 uint32_t hrtim_cpt1cr;
2648 uint32_t hrtim_cpt2cr;
2649
2650
2651 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2652 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2653
2654
2655 __HAL_LOCK(hhrtim);
2656
2657 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2658
2659
2660 switch (CaptureChannel)
2661 {
2662 case HRTIM_CAPTUREUNIT_1:
2663 {
2664 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2665 break;
2666 }
2667
2668 case HRTIM_CAPTUREUNIT_2:
2669 {
2670 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2671 break;
2672 }
2673
2674 default:
2675 {
2676 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2677
2678
2679 __HAL_UNLOCK(hhrtim);
2680
2681 break;
2682 }
2683 }
2684
2685 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2686 {
2687 return HAL_ERROR;
2688 }
2689
2690 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
2691 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
2692
2693
2694 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
2695 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
2696 {
2697 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2698 }
2699
2700 hhrtim->State = HAL_HRTIM_STATE_READY;
2701
2702
2703 __HAL_UNLOCK(hhrtim);
2704
2705 return HAL_OK;
2706 }
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
2726 uint32_t TimerIdx,
2727 uint32_t CaptureChannel)
2728 {
2729
2730 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2731 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2732
2733
2734 __HAL_LOCK(hhrtim);
2735
2736 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2737
2738
2739 switch (CaptureChannel)
2740 {
2741 case HRTIM_CAPTUREUNIT_1:
2742 {
2743 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2744
2745
2746 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2747 break;
2748 }
2749
2750 case HRTIM_CAPTUREUNIT_2:
2751 {
2752 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2753
2754
2755 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2756 break;
2757 }
2758
2759 default:
2760 {
2761 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2762
2763
2764 __HAL_UNLOCK(hhrtim);
2765
2766 break;
2767 }
2768 }
2769
2770 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2771 {
2772 return HAL_ERROR;
2773 }
2774
2775
2776 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2777
2778 hhrtim->State = HAL_HRTIM_STATE_READY;
2779
2780
2781 __HAL_UNLOCK(hhrtim);
2782
2783 return HAL_OK;
2784 }
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
2804 uint32_t TimerIdx,
2805 uint32_t CaptureChannel)
2806 {
2807
2808 uint32_t hrtim_cpt1cr;
2809 uint32_t hrtim_cpt2cr;
2810
2811
2812 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2813 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2814
2815
2816 __HAL_LOCK(hhrtim);
2817
2818 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2819
2820
2821 switch (CaptureChannel)
2822 {
2823 case HRTIM_CAPTUREUNIT_1:
2824 {
2825 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2826
2827
2828 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2829 break;
2830 }
2831
2832 case HRTIM_CAPTUREUNIT_2:
2833 {
2834 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2835
2836
2837 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2838 break;
2839 }
2840
2841 default:
2842 {
2843 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2844
2845
2846 __HAL_UNLOCK(hhrtim);
2847
2848 break;
2849 }
2850 }
2851
2852 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2853 {
2854 return HAL_ERROR;
2855 }
2856
2857 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
2858 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
2859
2860
2861 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
2862 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
2863 {
2864 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2865 }
2866
2867 hhrtim->State = HAL_HRTIM_STATE_READY;
2868
2869
2870 __HAL_UNLOCK(hhrtim);
2871
2872 return HAL_OK;
2873 }
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2897 uint32_t TimerIdx,
2898 uint32_t CaptureChannel,
2899 uint32_t SrcAddr,
2900 uint32_t DestAddr,
2901 uint32_t Length)
2902 {
2903 DMA_HandleTypeDef * hdma;
2904
2905
2906 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2907 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2908
2909
2910 __HAL_LOCK(hhrtim);
2911
2912 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2913
2914
2915 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2916
2917 if (hdma == NULL)
2918 {
2919 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2920
2921
2922 __HAL_UNLOCK(hhrtim);
2923
2924 return HAL_ERROR;
2925 }
2926
2927
2928 hdma->XferErrorCallback = HRTIM_DMAError ;
2929
2930
2931 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2932
2933
2934 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
2935 {
2936 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2937
2938
2939 __HAL_UNLOCK(hhrtim);
2940
2941 return HAL_ERROR;
2942 }
2943
2944 switch (CaptureChannel)
2945 {
2946 case HRTIM_CAPTUREUNIT_1:
2947 {
2948
2949 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2950
2951 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
2952 break;
2953 }
2954
2955 case HRTIM_CAPTUREUNIT_2:
2956 {
2957
2958 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2959
2960
2961 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
2962 break;
2963 }
2964
2965 default:
2966 {
2967 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2968
2969
2970 __HAL_UNLOCK(hhrtim);
2971
2972 break;
2973 }
2974 }
2975
2976 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2977 {
2978 return HAL_ERROR;
2979 }
2980
2981
2982 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2983
2984 hhrtim->State = HAL_HRTIM_STATE_READY;
2985
2986
2987 __HAL_UNLOCK(hhrtim);
2988
2989 return HAL_OK;
2990 }
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
3010 uint32_t TimerIdx,
3011 uint32_t CaptureChannel)
3012 {
3013
3014 uint32_t hrtim_cpt1cr;
3015 uint32_t hrtim_cpt2cr;
3016
3017
3018 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3019 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3020
3021
3022 __HAL_LOCK(hhrtim);
3023
3024 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3025
3026
3027
3028 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
3029 {
3030 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3031
3032
3033 __HAL_UNLOCK(hhrtim);
3034
3035 return HAL_ERROR;
3036 }
3037
3038 switch (CaptureChannel)
3039 {
3040 case HRTIM_CAPTUREUNIT_1:
3041 {
3042
3043 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
3044
3045
3046 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3047 break;
3048 }
3049
3050 case HRTIM_CAPTUREUNIT_2:
3051 {
3052
3053 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
3054
3055
3056 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3057 break;
3058 }
3059
3060 default:
3061 {
3062 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3063
3064
3065 __HAL_UNLOCK(hhrtim);
3066
3067 break;
3068 }
3069 }
3070
3071 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3072 {
3073 return HAL_ERROR;
3074 }
3075
3076 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3077 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3078
3079
3080 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3081 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3082 {
3083 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3084 }
3085
3086 hhrtim->State = HAL_HRTIM_STATE_READY;
3087
3088
3089 __HAL_UNLOCK(hhrtim);
3090
3091 return HAL_OK;
3092 }
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
3158 uint32_t TimerIdx,
3159 uint32_t OnePulseChannel,
3160 const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
3161 {
3162 HRTIM_OutputCfgTypeDef OutputCfg;
3163 HRTIM_EventCfgTypeDef EventCfg;
3164
3165
3166 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3167 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOnePulseChannelCfg->Pulse));
3168 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
3169 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
3170 assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
3171 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
3172 pSimpleOnePulseChannelCfg->EventPolarity));
3173 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
3174 assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
3175 pSimpleOnePulseChannelCfg->EventFilter));
3176
3177 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3178 {
3179 return HAL_BUSY;
3180 }
3181
3182
3183 __HAL_LOCK(hhrtim);
3184
3185 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3186
3187
3188 switch (OnePulseChannel)
3189 {
3190 case HRTIM_OUTPUT_TA1:
3191 case HRTIM_OUTPUT_TB1:
3192 case HRTIM_OUTPUT_TC1:
3193 case HRTIM_OUTPUT_TD1:
3194 case HRTIM_OUTPUT_TE1:
3195 {
3196 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse;
3197 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
3198 break;
3199 }
3200
3201 case HRTIM_OUTPUT_TA2:
3202 case HRTIM_OUTPUT_TB2:
3203 case HRTIM_OUTPUT_TC2:
3204 case HRTIM_OUTPUT_TD2:
3205 case HRTIM_OUTPUT_TE2:
3206 {
3207 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse;
3208 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
3209 break;
3210 }
3211
3212 default:
3213 {
3214 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
3215 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
3216
3217 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3218
3219
3220 __HAL_UNLOCK(hhrtim);
3221
3222 break;
3223 }
3224 }
3225
3226 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3227 {
3228 return HAL_ERROR;
3229 }
3230
3231
3232 OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1);
3233 OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1);
3234 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
3235 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
3236 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
3237 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
3238 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
3239
3240 HRTIM_OutputConfig(hhrtim,
3241 TimerIdx,
3242 OnePulseChannel,
3243 &OutputCfg);
3244
3245
3246 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
3247 EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
3248 EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1);
3249 EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS);
3250 EventCfg.Source = HRTIM_EVENTSRC_1;
3251
3252 HRTIM_EventConfig(hhrtim,
3253 pSimpleOnePulseChannelCfg->Event,
3254 &EventCfg);
3255
3256
3257 HRTIM_TIM_ResetConfig(hhrtim,
3258 TimerIdx,
3259 pSimpleOnePulseChannelCfg->Event);
3260
3261 hhrtim->State = HAL_HRTIM_STATE_READY;
3262
3263
3264 __HAL_UNLOCK(hhrtim);
3265
3266 return HAL_OK;
3267 }
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
3294 uint32_t TimerIdx,
3295 uint32_t OnePulseChannel)
3296 {
3297
3298 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3299
3300
3301 __HAL_LOCK(hhrtim);
3302
3303 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3304
3305
3306 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3307
3308
3309 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3310
3311 hhrtim->State = HAL_HRTIM_STATE_READY;
3312
3313
3314 __HAL_UNLOCK(hhrtim);
3315
3316 return HAL_OK;
3317 }
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
3344 uint32_t TimerIdx,
3345 uint32_t OnePulseChannel)
3346 {
3347
3348 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3349
3350
3351 __HAL_LOCK(hhrtim);
3352
3353 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3354
3355
3356 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3357
3358
3359 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3360
3361 hhrtim->State = HAL_HRTIM_STATE_READY;
3362
3363
3364 __HAL_UNLOCK(hhrtim);
3365
3366 return HAL_OK;
3367 }
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
3395 uint32_t TimerIdx,
3396 uint32_t OnePulseChannel)
3397 {
3398
3399 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3400
3401
3402 __HAL_LOCK(hhrtim);
3403
3404 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3405
3406
3407 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3408
3409
3410 switch (OnePulseChannel)
3411 {
3412 case HRTIM_OUTPUT_TA1:
3413 case HRTIM_OUTPUT_TB1:
3414 case HRTIM_OUTPUT_TC1:
3415 case HRTIM_OUTPUT_TD1:
3416 case HRTIM_OUTPUT_TE1:
3417 {
3418 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3419 break;
3420 }
3421
3422 case HRTIM_OUTPUT_TA2:
3423 case HRTIM_OUTPUT_TB2:
3424 case HRTIM_OUTPUT_TC2:
3425 case HRTIM_OUTPUT_TD2:
3426 case HRTIM_OUTPUT_TE2:
3427 {
3428 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3429 break;
3430 }
3431
3432 default:
3433 {
3434 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3435
3436
3437 __HAL_UNLOCK(hhrtim);
3438
3439 break;
3440 }
3441 }
3442
3443 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3444 {
3445 return HAL_ERROR;
3446 }
3447
3448
3449 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3450
3451 hhrtim->State = HAL_HRTIM_STATE_READY;
3452
3453
3454 __HAL_UNLOCK(hhrtim);
3455
3456 return HAL_OK;
3457 }
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
3485 uint32_t TimerIdx,
3486 uint32_t OnePulseChannel)
3487 {
3488
3489 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3490
3491
3492 __HAL_LOCK(hhrtim);
3493
3494 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3495
3496
3497 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3498
3499
3500 switch (OnePulseChannel)
3501 {
3502 case HRTIM_OUTPUT_TA1:
3503 case HRTIM_OUTPUT_TB1:
3504 case HRTIM_OUTPUT_TC1:
3505 case HRTIM_OUTPUT_TD1:
3506 case HRTIM_OUTPUT_TE1:
3507 {
3508 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3509 break;
3510 }
3511
3512 case HRTIM_OUTPUT_TA2:
3513 case HRTIM_OUTPUT_TB2:
3514 case HRTIM_OUTPUT_TC2:
3515 case HRTIM_OUTPUT_TD2:
3516 case HRTIM_OUTPUT_TE2:
3517 {
3518 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3519 break;
3520 }
3521
3522 default:
3523 {
3524 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3525
3526
3527 __HAL_UNLOCK(hhrtim);
3528
3529 break;
3530 }
3531 }
3532
3533 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3534 {
3535 return HAL_ERROR;
3536 }
3537
3538
3539 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3540
3541 hhrtim->State = HAL_HRTIM_STATE_READY;
3542
3543
3544 __HAL_UNLOCK(hhrtim);
3545
3546 return HAL_OK;
3547 }
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
3583 const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
3584 {
3585 uint32_t hrtim_bmcr;
3586
3587
3588 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
3589 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
3590 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
3591 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
3592 assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
3593
3594 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3595 {
3596 return HAL_BUSY;
3597 }
3598
3599
3600 __HAL_LOCK(hhrtim);
3601
3602 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3603
3604 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
3605
3606
3607 hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
3608 hrtim_bmcr |= (pBurstModeCfg->Mode & HRTIM_BMCR_BMOM);
3609
3610
3611 hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
3612 hrtim_bmcr |= (pBurstModeCfg->ClockSource & HRTIM_BMCR_BMCLK);
3613
3614
3615 hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
3616 hrtim_bmcr |= pBurstModeCfg->Prescaler;
3617
3618
3619 hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
3620 hrtim_bmcr |= (pBurstModeCfg->PreloadEnable & HRTIM_BMCR_BMPREN);
3621
3622
3623 hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
3624
3625
3626 hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
3627
3628
3629 hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
3630
3631
3632 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
3633
3634 hhrtim->State = HAL_HRTIM_STATE_READY;
3635
3636
3637 __HAL_UNLOCK(hhrtim);
3638
3639 return HAL_OK;
3640 }
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
3663 uint32_t Event,
3664 const HRTIM_EventCfgTypeDef* pEventCfg)
3665 {
3666
3667 assert_param(IS_HRTIM_EVENT(Event));
3668 assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
3669 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
3670 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
3671 assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
3672 assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
3673
3674 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3675 {
3676 return HAL_BUSY;
3677 }
3678
3679
3680 __HAL_LOCK(hhrtim);
3681
3682 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3683
3684
3685 HRTIM_EventConfig(hhrtim, Event, pEventCfg);
3686
3687 hhrtim->State = HAL_HRTIM_STATE_READY;
3688
3689
3690 __HAL_UNLOCK(hhrtim);
3691
3692 return HAL_OK;
3693 }
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3708 uint32_t Prescaler)
3709 {
3710
3711 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
3712
3713 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3714 {
3715 return HAL_BUSY;
3716 }
3717
3718
3719 __HAL_LOCK(hhrtim);
3720
3721 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3722
3723
3724 MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD));
3725
3726 hhrtim->State = HAL_HRTIM_STATE_READY;
3727
3728
3729 __HAL_UNLOCK(hhrtim);
3730
3731 return HAL_OK;
3732 }
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
3750 uint32_t Fault,
3751 const HRTIM_FaultCfgTypeDef* pFaultCfg)
3752 {
3753 uint32_t hrtim_fltinr1;
3754 uint32_t hrtim_fltinr2;
3755
3756
3757 assert_param(IS_HRTIM_FAULT(Fault));
3758 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
3759 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
3760 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
3761 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
3762
3763 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3764 {
3765 return HAL_BUSY;
3766 }
3767
3768
3769 __HAL_LOCK(hhrtim);
3770
3771 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3772
3773
3774 hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
3775 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
3776
3777 switch (Fault)
3778 {
3779 case HRTIM_FAULT_1:
3780 {
3781 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
3782 hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P);
3783 hrtim_fltinr1 |= (pFaultCfg->Source & HRTIM_FLTINR1_FLT1SRC);
3784 hrtim_fltinr1 |= (pFaultCfg->Filter & HRTIM_FLTINR1_FLT1F);
3785 hrtim_fltinr1 |= (pFaultCfg->Lock & HRTIM_FLTINR1_FLT1LCK);
3786 break;
3787 }
3788
3789 case HRTIM_FAULT_2:
3790 {
3791 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
3792 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P);
3793 hrtim_fltinr1 |= ((pFaultCfg->Source << 8U) & HRTIM_FLTINR1_FLT2SRC);
3794 hrtim_fltinr1 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR1_FLT2F);
3795 hrtim_fltinr1 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR1_FLT2LCK);
3796 break;
3797 }
3798
3799 case HRTIM_FAULT_3:
3800 {
3801 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
3802 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P);
3803 hrtim_fltinr1 |= ((pFaultCfg->Source << 16U) & HRTIM_FLTINR1_FLT3SRC);
3804 hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F);
3805 hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK);
3806 break;
3807 }
3808
3809 case HRTIM_FAULT_4:
3810 {
3811 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
3812 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P);
3813 hrtim_fltinr1 |= ((pFaultCfg->Source << 24U) & HRTIM_FLTINR1_FLT4SRC);
3814 hrtim_fltinr1 |= ((pFaultCfg->Filter << 24U) & HRTIM_FLTINR1_FLT4F);
3815 hrtim_fltinr1 |= ((pFaultCfg->Lock << 24U) & HRTIM_FLTINR1_FLT4LCK);
3816 break;
3817 }
3818
3819 case HRTIM_FAULT_5:
3820 {
3821 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
3822 hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P);
3823 hrtim_fltinr2 |= (pFaultCfg->Source & HRTIM_FLTINR2_FLT5SRC);
3824 hrtim_fltinr2 |= (pFaultCfg->Filter & HRTIM_FLTINR2_FLT5F);
3825 hrtim_fltinr2 |= (pFaultCfg->Lock & HRTIM_FLTINR2_FLT5LCK);
3826 break;
3827 }
3828
3829 default:
3830 {
3831 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3832
3833
3834 __HAL_UNLOCK(hhrtim);
3835
3836 break;
3837 }
3838 }
3839
3840 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3841 {
3842 return HAL_ERROR;
3843 }
3844
3845
3846 hhrtim->Instance->sCommonRegs.FLTINR1 = (hrtim_fltinr1 & (~(HRTIM_FLTINR1_FLTxLCK)));
3847 hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK)));
3848
3849
3850 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK));
3851 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK));
3852
3853 hhrtim->State = HAL_HRTIM_STATE_READY;
3854
3855
3856 __HAL_UNLOCK(hhrtim);
3857
3858 return HAL_OK;
3859 }
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3875 uint32_t Prescaler)
3876 {
3877
3878 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
3879
3880 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3881 {
3882 return HAL_BUSY;
3883 }
3884
3885
3886 __HAL_LOCK(hhrtim);
3887
3888 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3889
3890
3891 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, (Prescaler & HRTIM_FLTINR2_FLTSD));
3892
3893 hhrtim->State = HAL_HRTIM_STATE_READY;
3894
3895
3896 __HAL_UNLOCK(hhrtim);
3897
3898 return HAL_OK;
3899 }
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
3918 uint32_t Faults,
3919 uint32_t Enable)
3920 {
3921
3922 assert_param(IS_HRTIM_FAULT(Faults));
3923 assert_param(IS_HRTIM_FAULTMODECTL(Enable));
3924
3925 if ((Faults & HRTIM_FAULT_1) != (uint32_t)RESET)
3926 {
3927 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT1E, (Enable & HRTIM_FLTINR1_FLT1E));
3928 }
3929 if ((Faults & HRTIM_FAULT_2) != (uint32_t)RESET)
3930 {
3931 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT2E, ((Enable << 8U) & HRTIM_FLTINR1_FLT2E));
3932 }
3933 if ((Faults & HRTIM_FAULT_3) != (uint32_t)RESET)
3934 {
3935 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT3E, ((Enable << 16U) & HRTIM_FLTINR1_FLT3E));
3936 }
3937 if ((Faults & HRTIM_FAULT_4) != (uint32_t)RESET)
3938 {
3939 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT4E, ((Enable << 24U) & HRTIM_FLTINR1_FLT4E));
3940 }
3941 if ((Faults & HRTIM_FAULT_5) != (uint32_t)RESET)
3942 {
3943 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT5E, ((Enable) & HRTIM_FLTINR2_FLT5E));
3944 }
3945 }
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
3962 uint32_t ADCTrigger,
3963 const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
3964 {
3965 uint32_t hrtim_cr1;
3966
3967
3968 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
3969 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
3970
3971 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3972 {
3973 return HAL_BUSY;
3974 }
3975
3976
3977 __HAL_LOCK(hhrtim);
3978
3979 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3980
3981
3982 hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
3983
3984 switch (ADCTrigger)
3985 {
3986 case HRTIM_ADCTRIGGER_1:
3987 {
3988 hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
3989 hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
3990
3991
3992 hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
3993 break;
3994 }
3995
3996 case HRTIM_ADCTRIGGER_2:
3997 {
3998 hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
3999 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
4000
4001
4002 hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
4003 break;
4004 }
4005
4006 case HRTIM_ADCTRIGGER_3:
4007 {
4008 hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
4009 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
4010
4011
4012 hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
4013 break;
4014 }
4015
4016 case HRTIM_ADCTRIGGER_4:
4017 {
4018 hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
4019 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
4020
4021
4022 hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
4023 break;
4024 }
4025
4026 default:
4027 {
4028 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4029
4030
4031 __HAL_UNLOCK(hhrtim);
4032
4033 break;
4034 }
4035 }
4036
4037 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4038 {
4039 return HAL_ERROR;
4040 }
4041
4042
4043 hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
4044
4045 hhrtim->State = HAL_HRTIM_STATE_READY;
4046
4047
4048 __HAL_UNLOCK(hhrtim);
4049
4050 return HAL_OK;
4051 }
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
4115 uint32_t TimerIdx,
4116 const HRTIM_TimerCfgTypeDef * pTimerCfg)
4117 {
4118
4119 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4120
4121
4122 assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
4123 assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
4124 assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
4125 assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
4126 assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
4127 assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
4128 assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
4129
4130 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4131 {
4132 return HAL_BUSY;
4133 }
4134
4135
4136 __HAL_LOCK(hhrtim);
4137
4138 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4139
4140 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4141 {
4142
4143 assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
4144 assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
4145 assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
4146
4147
4148 HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
4149 }
4150 else
4151 {
4152
4153 assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
4154 assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
4155 assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
4156 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
4157 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
4158 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
4159 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
4160 pTimerCfg->DeadTimeInsertion));
4161 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
4162 pTimerCfg->DelayedProtectionMode));
4163 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
4164 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
4165 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
4166
4167
4168 HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
4169 }
4170
4171
4172 hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
4173 hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
4174 hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
4175 hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
4176 hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
4177
4178
4179 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
4180
4181 hhrtim->State = HAL_HRTIM_STATE_READY;
4182
4183
4184 __HAL_UNLOCK(hhrtim);
4185
4186 return HAL_OK;
4187 }
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
4216 uint32_t TimerIdx,
4217 uint32_t Event,
4218 const HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
4219 {
4220
4221 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4222 assert_param(IS_HRTIM_EVENT(Event));
4223 assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
4224
4225 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
4226
4227 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4228 {
4229 return HAL_BUSY;
4230 }
4231
4232
4233 __HAL_LOCK(hhrtim);
4234
4235 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4236
4237
4238 switch (Event)
4239 {
4240 case HRTIM_EVENT_NONE:
4241 {
4242 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1);
4243 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2);
4244 break;
4245 }
4246
4247 case HRTIM_EVENT_1:
4248 {
4249 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
4250 break;
4251 }
4252
4253 case HRTIM_EVENT_2:
4254 {
4255 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
4256 break;
4257 }
4258
4259 case HRTIM_EVENT_3:
4260 {
4261 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
4262 break;
4263 }
4264
4265 case HRTIM_EVENT_4:
4266 {
4267 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
4268 break;
4269 }
4270
4271 case HRTIM_EVENT_5:
4272 {
4273 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
4274 break;
4275 }
4276
4277 case HRTIM_EVENT_6:
4278 {
4279 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) );
4280 break;
4281 }
4282
4283 case HRTIM_EVENT_7:
4284 {
4285 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
4286 break;
4287 }
4288
4289 case HRTIM_EVENT_8:
4290 {
4291 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
4292 break;
4293 }
4294
4295 case HRTIM_EVENT_9:
4296 {
4297 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
4298 break;
4299 }
4300
4301 case HRTIM_EVENT_10:
4302 {
4303 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
4304 break;
4305 }
4306
4307 default:
4308 {
4309 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4310
4311
4312 __HAL_UNLOCK(hhrtim);
4313
4314 break;
4315 }
4316 }
4317
4318 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4319 {
4320 return HAL_ERROR;
4321 }
4322
4323 hhrtim->State = HAL_HRTIM_STATE_READY;
4324
4325
4326 __HAL_UNLOCK(hhrtim);
4327
4328 return HAL_OK;
4329 }
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
4346 uint32_t TimerIdx,
4347 const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
4348 {
4349 uint32_t hrtim_dtr;
4350
4351
4352 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4353 assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
4354 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
4355 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
4356 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
4357 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
4358 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
4359 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
4360
4361 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4362 {
4363 return HAL_BUSY;
4364 }
4365
4366
4367 __HAL_LOCK(hhrtim);
4368
4369 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4370
4371
4372 hrtim_dtr = (pDeadTimeCfg->Prescaler & HRTIM_DTR_DTPRSC);
4373 hrtim_dtr |= (pDeadTimeCfg->RisingValue & HRTIM_DTR_DTR);
4374 hrtim_dtr |= (pDeadTimeCfg->RisingSign & HRTIM_DTR_SDTR);
4375 hrtim_dtr |= (pDeadTimeCfg->RisingSignLock & HRTIM_DTR_DTRSLK);
4376 hrtim_dtr |= (pDeadTimeCfg->RisingLock & HRTIM_DTR_DTRLK);
4377 hrtim_dtr |= ((pDeadTimeCfg->FallingValue << 16U) & HRTIM_DTR_DTF);
4378 hrtim_dtr |= (pDeadTimeCfg->FallingSign & HRTIM_DTR_SDTF);
4379 hrtim_dtr |= (pDeadTimeCfg->FallingSignLock & HRTIM_DTR_DTFSLK);
4380 hrtim_dtr |= (pDeadTimeCfg->FallingLock & HRTIM_DTR_DTFLK);
4381
4382
4383 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, (
4384 HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
4385 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
4386 HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr);
4387
4388 hhrtim->State = HAL_HRTIM_STATE_READY;
4389
4390
4391 __HAL_UNLOCK(hhrtim);
4392
4393 return HAL_OK;
4394 }
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
4411 uint32_t TimerIdx,
4412 const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
4413 {
4414 uint32_t hrtim_chpr;
4415
4416
4417 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4418 assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
4419 assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
4420 assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
4421
4422 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4423 {
4424 return HAL_BUSY;
4425 }
4426
4427
4428 __HAL_LOCK(hhrtim);
4429
4430 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4431
4432
4433 hrtim_chpr = (pChopperModeCfg->CarrierFreq & HRTIM_CHPR_CARFRQ);
4434 hrtim_chpr |= (pChopperModeCfg->DutyCycle & HRTIM_CHPR_CARDTY);
4435 hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW);
4436
4437
4438 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR,
4439 (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW),
4440 hrtim_chpr);
4441
4442 hhrtim->State = HAL_HRTIM_STATE_READY;
4443
4444
4445 __HAL_UNLOCK(hhrtim);
4446
4447 return HAL_OK;
4448 }
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
4488 uint32_t TimerIdx,
4489 uint32_t RegistersToUpdate)
4490 {
4491
4492 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
4493
4494 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4495 {
4496 return HAL_BUSY;
4497 }
4498
4499
4500 __HAL_LOCK(hhrtim);
4501
4502 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4503
4504
4505 switch (TimerIdx)
4506 {
4507 case HRTIM_TIMERINDEX_TIMER_A:
4508 {
4509 hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
4510 break;
4511 }
4512
4513 case HRTIM_TIMERINDEX_TIMER_B:
4514 {
4515 hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
4516 break;
4517 }
4518
4519 case HRTIM_TIMERINDEX_TIMER_C:
4520 {
4521 hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
4522 break;
4523 }
4524
4525 case HRTIM_TIMERINDEX_TIMER_D:
4526 {
4527 hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
4528 break;
4529 }
4530
4531 case HRTIM_TIMERINDEX_TIMER_E:
4532 {
4533 hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
4534 break;
4535 }
4536
4537 case HRTIM_TIMERINDEX_MASTER:
4538 {
4539 hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
4540 break;
4541 }
4542
4543 default:
4544 {
4545 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4546
4547
4548 __HAL_UNLOCK(hhrtim);
4549
4550 break;
4551 }
4552 }
4553
4554 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4555 {
4556 return HAL_ERROR;
4557 }
4558
4559 hhrtim->State = HAL_HRTIM_STATE_READY;
4560
4561
4562 __HAL_UNLOCK(hhrtim);
4563
4564 return HAL_OK;
4565 }
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
4595 uint32_t TimerIdx,
4596 uint32_t CompareUnit,
4597 const HRTIM_CompareCfgTypeDef* pCompareCfg)
4598 {
4599
4600 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4601
4602 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4603 {
4604 return HAL_BUSY;
4605 }
4606
4607
4608 __HAL_LOCK(hhrtim);
4609
4610 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4611
4612
4613 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4614 {
4615 switch (CompareUnit)
4616 {
4617 case HRTIM_COMPAREUNIT_1:
4618 {
4619 hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
4620 break;
4621 }
4622
4623 case HRTIM_COMPAREUNIT_2:
4624 {
4625 hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
4626 break;
4627 }
4628
4629 case HRTIM_COMPAREUNIT_3:
4630 {
4631 hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
4632 break;
4633 }
4634
4635 case HRTIM_COMPAREUNIT_4:
4636 {
4637 hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
4638 break;
4639 }
4640
4641 default:
4642 {
4643 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4644
4645
4646 __HAL_UNLOCK(hhrtim);
4647
4648 break;
4649 }
4650 }
4651
4652 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4653 {
4654 return HAL_ERROR;
4655 }
4656
4657 }
4658 else
4659 {
4660 switch (CompareUnit)
4661 {
4662 case HRTIM_COMPAREUNIT_1:
4663 {
4664
4665 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
4666 break;
4667 }
4668
4669 case HRTIM_COMPAREUNIT_2:
4670 {
4671
4672 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4673
4674
4675 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
4676
4677 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4678 {
4679
4680
4681
4682 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
4683 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
4684
4685
4686 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4687 {
4688 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4689 }
4690 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4691 {
4692 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4693 }
4694 else
4695 {
4696
4697 }
4698 }
4699 else
4700 {
4701
4702 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
4703 }
4704 break;
4705 }
4706
4707 case HRTIM_COMPAREUNIT_3:
4708 {
4709
4710 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
4711 break;
4712 }
4713
4714 case HRTIM_COMPAREUNIT_4:
4715 {
4716
4717 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4718
4719
4720 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
4721
4722 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4723 {
4724
4725
4726
4727 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
4728 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
4729
4730
4731 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4732 {
4733 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4734 }
4735 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4736 {
4737 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4738 }
4739 else
4740 {
4741
4742 }
4743 }
4744 else
4745 {
4746
4747 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
4748 }
4749 break;
4750 }
4751
4752 default:
4753 {
4754 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4755
4756
4757 __HAL_UNLOCK(hhrtim);
4758
4759 break;
4760 }
4761 }
4762
4763 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4764 {
4765 return HAL_ERROR;
4766 }
4767
4768 }
4769 hhrtim->State = HAL_HRTIM_STATE_READY;
4770
4771
4772 __HAL_UNLOCK(hhrtim);
4773
4774 return HAL_OK;
4775 }
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
4796 uint32_t TimerIdx,
4797 uint32_t CaptureUnit,
4798 const HRTIM_CaptureCfgTypeDef* pCaptureCfg)
4799 {
4800
4801 assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
4802
4803
4804 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4805 {
4806 return HAL_BUSY;
4807 }
4808
4809
4810 __HAL_LOCK(hhrtim);
4811
4812 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4813
4814
4815 switch (CaptureUnit)
4816 {
4817 case HRTIM_CAPTUREUNIT_1:
4818 {
4819 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, pCaptureCfg->Trigger);
4820 break;
4821 }
4822
4823 case HRTIM_CAPTUREUNIT_2:
4824 {
4825 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, pCaptureCfg->Trigger);
4826 break;
4827 }
4828
4829 default:
4830 {
4831 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4832
4833
4834 __HAL_UNLOCK(hhrtim);
4835
4836 break;
4837 }
4838 }
4839
4840 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4841 {
4842 return HAL_ERROR;
4843 }
4844
4845
4846 hhrtim->State = HAL_HRTIM_STATE_READY;
4847
4848
4849 __HAL_UNLOCK(hhrtim);
4850
4851 return HAL_OK;
4852 }
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
4882 uint32_t TimerIdx,
4883 uint32_t Output,
4884 const HRTIM_OutputCfgTypeDef * pOutputCfg)
4885 {
4886
4887 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
4888 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
4889 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
4890 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
4891 assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
4892 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
4893 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
4894
4895 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4896 {
4897 return HAL_BUSY;
4898 }
4899
4900
4901 __HAL_LOCK(hhrtim);
4902
4903 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4904
4905
4906 HRTIM_OutputConfig(hhrtim,
4907 TimerIdx,
4908 Output,
4909 pOutputCfg);
4910
4911 hhrtim->State = HAL_HRTIM_STATE_READY;
4912
4913
4914 __HAL_UNLOCK(hhrtim);
4915
4916 return HAL_OK;
4917 }
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
4950 uint32_t TimerIdx,
4951 uint32_t Output,
4952 uint32_t OutputLevel)
4953 {
4954
4955 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
4956 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
4957
4958 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4959 {
4960 return HAL_BUSY;
4961 }
4962
4963
4964 __HAL_LOCK(hhrtim);
4965
4966 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4967
4968
4969 switch (Output)
4970 {
4971 case HRTIM_OUTPUT_TA1:
4972 case HRTIM_OUTPUT_TB1:
4973 case HRTIM_OUTPUT_TC1:
4974 case HRTIM_OUTPUT_TD1:
4975 case HRTIM_OUTPUT_TE1:
4976 {
4977 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
4978 {
4979
4980 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST);
4981 }
4982 else
4983 {
4984
4985 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R, HRTIM_RST1R_SRT);
4986 }
4987 break;
4988 }
4989
4990 case HRTIM_OUTPUT_TA2:
4991 case HRTIM_OUTPUT_TB2:
4992 case HRTIM_OUTPUT_TC2:
4993 case HRTIM_OUTPUT_TD2:
4994 case HRTIM_OUTPUT_TE2:
4995 {
4996 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
4997 {
4998
4999 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R, HRTIM_SET2R_SST);
5000 }
5001 else
5002 {
5003
5004 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R, HRTIM_RST2R_SRT);
5005 }
5006 break;
5007 }
5008
5009 default:
5010 {
5011 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5012
5013
5014 __HAL_UNLOCK(hhrtim);
5015
5016 break;
5017 }
5018 }
5019
5020 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5021 {
5022 return HAL_ERROR;
5023 }
5024
5025 hhrtim->State = HAL_HRTIM_STATE_READY;
5026
5027
5028 __HAL_UNLOCK(hhrtim);
5029
5030 return HAL_OK;
5031 }
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
5052 uint32_t OutputsToStart)
5053 {
5054
5055 assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
5056
5057
5058 __HAL_LOCK(hhrtim);
5059
5060 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5061
5062
5063 hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
5064
5065 hhrtim->State = HAL_HRTIM_STATE_READY;
5066
5067
5068 __HAL_UNLOCK(hhrtim);
5069
5070 return HAL_OK;
5071 }
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
5092 uint32_t OutputsToStop)
5093 {
5094
5095 assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
5096
5097
5098 __HAL_LOCK(hhrtim);
5099
5100 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5101
5102
5103 hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
5104
5105 hhrtim->State = HAL_HRTIM_STATE_READY;
5106
5107
5108 __HAL_UNLOCK(hhrtim);
5109
5110 return HAL_OK;
5111 }
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,
5128 uint32_t Timers)
5129 {
5130
5131 assert_param(IS_HRTIM_TIMERID(Timers));
5132
5133
5134 __HAL_LOCK(hhrtim);
5135
5136 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5137
5138
5139 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
5140
5141 hhrtim->State = HAL_HRTIM_STATE_READY;
5142
5143
5144 __HAL_UNLOCK(hhrtim);
5145
5146 return HAL_OK;
5147 }
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,
5165 uint32_t Timers)
5166 {
5167
5168 assert_param(IS_HRTIM_TIMERID(Timers));
5169
5170
5171 __HAL_LOCK(hhrtim);
5172
5173 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5174
5175
5176 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
5177
5178 hhrtim->State = HAL_HRTIM_STATE_READY;
5179
5180
5181 __HAL_UNLOCK(hhrtim);
5182
5183 return HAL_OK;
5184 }
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,
5205 uint32_t Timers)
5206 {
5207 uint8_t timer_idx;
5208
5209
5210 assert_param(IS_HRTIM_TIMERID(Timers));
5211
5212
5213 __HAL_LOCK(hhrtim);
5214
5215 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5216
5217
5218 __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
5219
5220
5221 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
5222 {
5223 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
5224 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
5225 }
5226
5227
5228 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5229 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5230 timer_idx++)
5231 {
5232 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
5233 {
5234 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
5235 timer_idx,
5236 hhrtim->TimerParam[timer_idx].InterruptRequests);
5237 }
5238 }
5239
5240
5241 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
5242
5243 hhrtim->State = HAL_HRTIM_STATE_READY;
5244
5245
5246 __HAL_UNLOCK(hhrtim);
5247
5248 return HAL_OK;}
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,
5267 uint32_t Timers)
5268 {
5269
5270 __IO uint32_t delai = (uint32_t)(0x17FU);
5271
5272
5273 uint8_t timer_idx;
5274
5275
5276 assert_param(IS_HRTIM_TIMERID(Timers));
5277
5278
5279 __HAL_LOCK(hhrtim);
5280
5281 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5282
5283
5284 __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
5285
5286
5287 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
5288 {
5289
5290 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
5291 }
5292
5293
5294 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5295 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5296 timer_idx++)
5297 {
5298 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
5299 {
5300 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
5301 }
5302 }
5303
5304
5305 do { delai--; } while (delai != 0U);
5306
5307
5308
5309 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
5310
5311 hhrtim->State = HAL_HRTIM_STATE_READY;
5312
5313
5314 __HAL_UNLOCK(hhrtim);
5315
5316 return HAL_OK;
5317 }
5318
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,
5339 uint32_t Timers)
5340 {
5341 uint8_t timer_idx;
5342 DMA_HandleTypeDef * hdma;
5343
5344
5345 assert_param(IS_HRTIM_TIMERID(Timers));
5346
5347 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5348 {
5349 return HAL_BUSY;
5350 }
5351
5352 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5353
5354
5355 __HAL_LOCK(hhrtim);
5356
5357 if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) &&
5358 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5359 {
5360
5361 hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
5362
5363
5364 hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
5365
5366
5367 if (HAL_DMA_Start_IT(hhrtim->hdmaMaster,
5368 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
5369 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
5370 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK)
5371 {
5372 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5373
5374
5375 __HAL_UNLOCK(hhrtim);
5376
5377 return HAL_ERROR;
5378 }
5379
5380
5381 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
5382 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5383 }
5384
5385 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5386 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5387 timer_idx++)
5388 {
5389 if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) &&
5390 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5391 {
5392
5393 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
5394
5395 if (hdma == NULL)
5396 {
5397 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5398
5399
5400 __HAL_UNLOCK(hhrtim);
5401
5402 return HAL_ERROR;
5403 }
5404
5405
5406 hdma->XferErrorCallback = HRTIM_DMAError ;
5407
5408
5409 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
5410
5411
5412 if (HAL_DMA_Start_IT(hdma,
5413 hhrtim->TimerParam[timer_idx].DMASrcAddress,
5414 hhrtim->TimerParam[timer_idx].DMADstAddress,
5415 hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK)
5416 {
5417 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5418
5419
5420 __HAL_UNLOCK(hhrtim);
5421
5422 return HAL_ERROR;
5423 }
5424
5425
5426 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
5427 timer_idx,
5428 hhrtim->TimerParam[timer_idx].DMARequests);
5429 }
5430 }
5431
5432
5433 __HAL_HRTIM_ENABLE(hhrtim, Timers);
5434
5435 hhrtim->State = HAL_HRTIM_STATE_READY;
5436
5437
5438 __HAL_UNLOCK(hhrtim);
5439
5440 return HAL_OK;
5441 }
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,
5460 uint32_t Timers)
5461 {
5462 uint8_t timer_idx;
5463
5464
5465 assert_param(IS_HRTIM_TIMERID(Timers));
5466
5467 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5468
5469 if (((Timers & HRTIM_TIMERID_MASTER) != 0U) &&
5470 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5471 {
5472
5473 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
5474 {
5475 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5476 }
5477 else
5478 {
5479 hhrtim->State = HAL_HRTIM_STATE_READY;
5480
5481 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
5482 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5483 }
5484 }
5485
5486 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5487 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5488 timer_idx++)
5489 {
5490 if (((Timers & TimerIdxToTimerId[timer_idx]) != 0U) &&
5491 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5492 {
5493
5494
5495 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx)) != HAL_OK)
5496 {
5497 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5498 }
5499 else
5500 {
5501 hhrtim->State = HAL_HRTIM_STATE_READY;
5502
5503
5504 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
5505 timer_idx,
5506 hhrtim->TimerParam[timer_idx].DMARequests);
5507 }
5508 }
5509 }
5510
5511
5512 __HAL_HRTIM_DISABLE(hhrtim, Timers);
5513
5514 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
5515 {
5516 return HAL_ERROR;
5517 }
5518 else
5519 {
5520 return HAL_OK;
5521 }
5522 }
5523
5524
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
5535 uint32_t Enable)
5536 {
5537
5538 assert_param(IS_HRTIM_BURSTMODECTL(Enable));
5539
5540 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5541 {
5542 return HAL_BUSY;
5543 }
5544
5545
5546 __HAL_LOCK(hhrtim);
5547
5548 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5549
5550
5551 MODIFY_REG(hhrtim->Instance->sCommonRegs.BMCR, HRTIM_BMCR_BME, Enable);
5552
5553 hhrtim->State = HAL_HRTIM_STATE_READY;
5554
5555
5556 __HAL_UNLOCK(hhrtim);
5557
5558 return HAL_OK;
5559 }
5560
5561
5562
5563
5564
5565
5566 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
5567 {
5568 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5569 {
5570 return HAL_BUSY;
5571 }
5572
5573
5574 __HAL_LOCK(hhrtim);
5575
5576 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5577
5578
5579 SET_BIT(hhrtim->Instance->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
5580
5581 hhrtim->State = HAL_HRTIM_STATE_READY;
5582
5583
5584 __HAL_UNLOCK(hhrtim);
5585
5586 return HAL_OK;
5587 }
5588
5589
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
5608 uint32_t TimerIdx,
5609 uint32_t CaptureUnit)
5610 {
5611
5612 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5613 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5614
5615 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5616 {
5617 return HAL_BUSY;
5618 }
5619
5620
5621 __HAL_LOCK(hhrtim);
5622
5623 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5624
5625
5626 switch (CaptureUnit)
5627 {
5628 case HRTIM_CAPTUREUNIT_1:
5629 {
5630 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT);
5631 break;
5632 }
5633
5634 case HRTIM_CAPTUREUNIT_2:
5635 {
5636 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT);
5637 break;
5638 }
5639
5640 default:
5641 {
5642 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5643
5644
5645 __HAL_UNLOCK(hhrtim);
5646
5647 break;
5648 }
5649 }
5650
5651 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5652 {
5653 return HAL_ERROR;
5654 }
5655
5656 hhrtim->State = HAL_HRTIM_STATE_READY;
5657
5658
5659 __HAL_UNLOCK(hhrtim);
5660
5661 return HAL_OK;
5662 }
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672
5673
5674
5675
5676
5677
5678
5679 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
5680 uint32_t Timers)
5681 {
5682
5683 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5684
5685 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5686 {
5687 return HAL_BUSY;
5688 }
5689
5690
5691 __HAL_LOCK(hhrtim);
5692
5693 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5694
5695
5696 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
5697
5698 hhrtim->State = HAL_HRTIM_STATE_READY;
5699
5700
5701 __HAL_UNLOCK(hhrtim);
5702
5703 return HAL_OK;
5704 }
5705
5706
5707
5708
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
5722 uint32_t Timers)
5723 {
5724
5725 assert_param(IS_HRTIM_TIMERRESET(Timers));
5726
5727 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5728 {
5729 return HAL_BUSY;
5730 }
5731
5732
5733 __HAL_LOCK(hhrtim);
5734
5735 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5736
5737
5738 hhrtim->Instance->sCommonRegs.CR2 = Timers;
5739
5740 hhrtim->State = HAL_HRTIM_STATE_READY;
5741
5742
5743 __HAL_UNLOCK(hhrtim);
5744
5745 return HAL_OK;
5746 }
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769
5770
5771
5772 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
5773 uint32_t TimerIdx,
5774 uint32_t BurstBufferAddress,
5775 uint32_t BurstBufferLength)
5776 {
5777 DMA_HandleTypeDef * hdma;
5778
5779
5780 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5781
5782 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5783 {
5784 return HAL_BUSY;
5785 }
5786 if(hhrtim->State == HAL_HRTIM_STATE_READY)
5787 {
5788 if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
5789 {
5790 return HAL_ERROR;
5791 }
5792 else
5793 {
5794 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5795 }
5796 }
5797
5798
5799 __HAL_LOCK(hhrtim);
5800
5801
5802 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
5803
5804 if (hdma == NULL)
5805 {
5806 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5807
5808
5809 __HAL_UNLOCK(hhrtim);
5810
5811 return HAL_ERROR;
5812 }
5813
5814
5815 hdma->XferCpltCallback = HRTIM_BurstDMACplt;
5816
5817
5818 hdma->XferErrorCallback = HRTIM_DMAError ;
5819
5820
5821 if (HAL_DMA_Start_IT(hdma,
5822 BurstBufferAddress,
5823 (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
5824 BurstBufferLength) != HAL_OK)
5825 {
5826 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5827
5828
5829 __HAL_UNLOCK(hhrtim);
5830
5831 return HAL_ERROR;
5832 }
5833
5834 hhrtim->State = HAL_HRTIM_STATE_READY;
5835
5836
5837 __HAL_UNLOCK(hhrtim);
5838
5839 return HAL_OK;
5840 }
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855
5856 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
5857 uint32_t Timers)
5858 {
5859
5860 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5861
5862
5863 __HAL_LOCK(hhrtim);
5864
5865 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5866
5867
5868 hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
5869
5870 hhrtim->State = HAL_HRTIM_STATE_READY;
5871
5872
5873 __HAL_UNLOCK(hhrtim);
5874
5875 return HAL_OK;
5876 }
5877
5878
5879
5880
5881
5882
5883
5884
5885
5886
5887
5888
5889
5890
5891
5892 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
5893 uint32_t Timers)
5894 {
5895
5896 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5897
5898
5899 __HAL_LOCK(hhrtim);
5900
5901 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5902
5903
5904 hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
5905
5906 hhrtim->State = HAL_HRTIM_STATE_READY;
5907
5908
5909 __HAL_UNLOCK(hhrtim);
5910
5911 return HAL_OK;
5912 }
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim)
5946 {
5947
5948 return hhrtim->State;
5949 }
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964
5965
5966
5967 uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,
5968 uint32_t TimerIdx,
5969 uint32_t CaptureUnit)
5970 {
5971 uint32_t captured_value;
5972
5973
5974 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5975 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5976
5977
5978 switch (CaptureUnit)
5979 {
5980 case HRTIM_CAPTUREUNIT_1:
5981 {
5982 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
5983 break;
5984 }
5985
5986 case HRTIM_CAPTUREUNIT_2:
5987 {
5988 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
5989 break;
5990 }
5991
5992 default:
5993 {
5994 captured_value = 0xFFFFFFFFUL;
5995 break;
5996 }
5997
5998 }
5999
6000 return captured_value;
6001 }
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030 uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim,
6031 uint32_t TimerIdx,
6032 uint32_t Output)
6033 {
6034 uint32_t output_level;
6035
6036
6037 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6038
6039
6040 switch (Output)
6041 {
6042 case HRTIM_OUTPUT_TA1:
6043 case HRTIM_OUTPUT_TB1:
6044 case HRTIM_OUTPUT_TC1:
6045 case HRTIM_OUTPUT_TD1:
6046 case HRTIM_OUTPUT_TE1:
6047 {
6048 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET)
6049 {
6050 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
6051 }
6052 else
6053 {
6054 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
6055 }
6056 break;
6057 }
6058
6059 case HRTIM_OUTPUT_TA2:
6060 case HRTIM_OUTPUT_TB2:
6061 case HRTIM_OUTPUT_TC2:
6062 case HRTIM_OUTPUT_TD2:
6063 case HRTIM_OUTPUT_TE2:
6064 {
6065 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET)
6066 {
6067 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
6068 }
6069 else
6070 {
6071 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
6072 }
6073 break;
6074 }
6075
6076 default:
6077 {
6078 output_level = 0xFFFFFFFFUL;
6079 break;
6080 }
6081 }
6082
6083 return output_level;
6084 }
6085
6086
6087
6088
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110 uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,
6111 uint32_t TimerIdx,
6112 uint32_t Output)
6113 {
6114 uint32_t output_bit;
6115 uint32_t output_state;
6116
6117
6118 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6119
6120
6121 UNUSED(TimerIdx);
6122
6123
6124 switch (Output)
6125 {
6126 case HRTIM_OUTPUT_TA1:
6127 {
6128 output_bit = HRTIM_OENR_TA1OEN;
6129 break;
6130 }
6131
6132 case HRTIM_OUTPUT_TA2:
6133 {
6134 output_bit = HRTIM_OENR_TA2OEN;
6135 break;
6136 }
6137
6138 case HRTIM_OUTPUT_TB1:
6139 {
6140 output_bit = HRTIM_OENR_TB1OEN;
6141 break;
6142 }
6143
6144 case HRTIM_OUTPUT_TB2:
6145 {
6146 output_bit = HRTIM_OENR_TB2OEN;
6147 break;
6148 }
6149
6150 case HRTIM_OUTPUT_TC1:
6151 {
6152 output_bit = HRTIM_OENR_TC1OEN;
6153 break;
6154 }
6155
6156 case HRTIM_OUTPUT_TC2:
6157 {
6158 output_bit = HRTIM_OENR_TC2OEN;
6159 break;
6160 }
6161
6162 case HRTIM_OUTPUT_TD1:
6163 {
6164 output_bit = HRTIM_OENR_TD1OEN;
6165 break;
6166 }
6167
6168 case HRTIM_OUTPUT_TD2:
6169 {
6170 output_bit = HRTIM_OENR_TD2OEN;
6171 break;
6172 }
6173
6174 case HRTIM_OUTPUT_TE1:
6175 {
6176 output_bit = HRTIM_OENR_TE1OEN;
6177 break;
6178 }
6179
6180 case HRTIM_OUTPUT_TE2:
6181 {
6182 output_bit = HRTIM_OENR_TE2OEN;
6183 break;
6184 }
6185
6186 default:
6187 {
6188 output_bit = 0UL;
6189 break;
6190 }
6191 }
6192
6193 if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
6194 {
6195
6196 output_state = HRTIM_OUTPUTSTATE_RUN;
6197 }
6198 else
6199 {
6200 if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != (uint32_t)RESET)
6201 {
6202
6203 output_state = HRTIM_OUTPUTSTATE_FAULT;
6204 }
6205 else
6206 {
6207
6208 output_state = HRTIM_OUTPUTSTATE_IDLE;
6209 }
6210 }
6211
6212 return(output_state);
6213 }
6214
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
6230
6231
6232
6233
6234
6235
6236
6237
6238
6239
6240 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim,
6241 uint32_t TimerIdx,
6242 uint32_t Output)
6243 {
6244 uint32_t delayed_protection_status;
6245
6246
6247 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6248
6249
6250 switch (Output)
6251 {
6252 case HRTIM_OUTPUT_TA1:
6253 case HRTIM_OUTPUT_TB1:
6254 case HRTIM_OUTPUT_TC1:
6255 case HRTIM_OUTPUT_TD1:
6256 case HRTIM_OUTPUT_TE1:
6257 {
6258 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET)
6259 {
6260
6261 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
6262 }
6263 else
6264 {
6265
6266 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
6267 }
6268 break;
6269 }
6270
6271 case HRTIM_OUTPUT_TA2:
6272 case HRTIM_OUTPUT_TB2:
6273 case HRTIM_OUTPUT_TC2:
6274 case HRTIM_OUTPUT_TD2:
6275 case HRTIM_OUTPUT_TE2:
6276 {
6277 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET)
6278 {
6279
6280 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
6281 }
6282 else
6283 {
6284
6285 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
6286 }
6287 break;
6288 }
6289
6290 default:
6291 {
6292 delayed_protection_status = 0xFFFFFFFFUL;
6293 break;
6294 }
6295 }
6296
6297 return delayed_protection_status;
6298 }
6299
6300
6301
6302
6303
6304
6305 uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim)
6306 {
6307 uint32_t burst_mode_status;
6308
6309
6310 burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
6311
6312 return burst_mode_status;
6313 }
6314
6315
6316
6317
6318
6319
6320
6321
6322
6323
6324
6325
6326
6327
6328 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim,
6329 uint32_t TimerIdx)
6330 {
6331 uint32_t current_pushpull_status;
6332
6333
6334 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6335
6336
6337 current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
6338
6339 return current_pushpull_status;
6340 }
6341
6342
6343
6344
6345
6346
6347
6348
6349
6350
6351
6352
6353
6354
6355
6356 uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim,
6357 uint32_t TimerIdx)
6358 {
6359 uint32_t idle_pushpull_status;
6360
6361
6362 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6363
6364
6365 idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
6366
6367 return idle_pushpull_status;
6368 }
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406
6407
6408
6409
6410
6411
6412
6413
6414
6415
6416
6417
6418
6419
6420
6421
6422
6423
6424
6425
6426
6427
6428
6429
6430
6431
6432
6433
6434
6435
6436
6437
6438
6439
6440
6441
6442 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
6443 uint32_t TimerIdx)
6444 {
6445
6446 if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
6447 {
6448 HRTIM_HRTIM_ISR(hhrtim);
6449 }
6450 else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
6451 {
6452
6453 HRTIM_Master_ISR(hhrtim);
6454 }
6455 else
6456 {
6457
6458 HRTIM_Timer_ISR(hhrtim, TimerIdx);
6459 }
6460
6461 }
6462
6463
6464
6465
6466
6467
6468 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
6469 {
6470
6471 UNUSED(hhrtim);
6472
6473
6474
6475
6476 }
6477
6478
6479
6480
6481
6482
6483 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
6484 {
6485
6486 UNUSED(hhrtim);
6487
6488
6489
6490
6491 }
6492
6493
6494
6495
6496
6497
6498 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
6499 {
6500
6501 UNUSED(hhrtim);
6502
6503
6504
6505
6506 }
6507
6508
6509
6510
6511
6512
6513 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
6514 {
6515
6516 UNUSED(hhrtim);
6517
6518
6519
6520
6521 }
6522
6523
6524
6525
6526
6527
6528 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
6529 {
6530
6531 UNUSED(hhrtim);
6532
6533
6534
6535
6536 }
6537
6538
6539
6540
6541
6542
6543 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
6544 {
6545
6546 UNUSED(hhrtim);
6547
6548
6549
6550
6551 }
6552
6553
6554
6555
6556
6557
6558 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
6559 {
6560
6561 UNUSED(hhrtim);
6562
6563
6564
6565
6566 }
6567
6568
6569
6570
6571
6572
6573 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
6574 {
6575
6576 UNUSED(hhrtim);
6577
6578
6579
6580
6581 }
6582
6583
6584
6585
6586
6587
6588
6589
6590
6591
6592
6593
6594
6595
6596 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
6597 uint32_t TimerIdx)
6598 {
6599
6600 UNUSED(hhrtim);
6601 UNUSED(TimerIdx);
6602
6603
6604
6605
6606 }
6607
6608
6609
6610
6611
6612
6613
6614
6615
6616
6617
6618
6619
6620
6621 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
6622 uint32_t TimerIdx)
6623 {
6624
6625 UNUSED(hhrtim);
6626 UNUSED(TimerIdx);
6627
6628
6629
6630
6631 }
6632
6633
6634
6635
6636
6637
6638
6639
6640
6641
6642
6643
6644
6645
6646
6647 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6648 uint32_t TimerIdx)
6649 {
6650
6651 UNUSED(hhrtim);
6652 UNUSED(TimerIdx);
6653
6654
6655
6656
6657 }
6658
6659
6660
6661
6662
6663
6664
6665
6666
6667
6668
6669
6670
6671
6672
6673 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6674 uint32_t TimerIdx)
6675 {
6676
6677 UNUSED(hhrtim);
6678 UNUSED(TimerIdx);
6679
6680
6681
6682
6683 }
6684
6685
6686
6687
6688
6689
6690
6691
6692
6693
6694
6695
6696
6697
6698
6699 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
6700 uint32_t TimerIdx)
6701 {
6702
6703 UNUSED(hhrtim);
6704 UNUSED(TimerIdx);
6705
6706
6707
6708
6709 }
6710
6711
6712
6713
6714
6715
6716
6717
6718
6719
6720
6721
6722
6723
6724
6725 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
6726 uint32_t TimerIdx)
6727 {
6728
6729 UNUSED(hhrtim);
6730 UNUSED(TimerIdx);
6731
6732
6733
6734
6735 }
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745
6746
6747
6748
6749 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6750 uint32_t TimerIdx)
6751 {
6752
6753 UNUSED(hhrtim);
6754 UNUSED(TimerIdx);
6755
6756
6757
6758
6759 }
6760
6761
6762
6763
6764
6765
6766
6767
6768
6769
6770
6771
6772
6773 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6774 uint32_t TimerIdx)
6775 {
6776
6777 UNUSED(hhrtim);
6778 UNUSED(TimerIdx);
6779
6780
6781
6782
6783 }
6784
6785
6786
6787
6788
6789
6790
6791
6792
6793
6794
6795
6796
6797
6798 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
6799 uint32_t TimerIdx)
6800 {
6801
6802 UNUSED(hhrtim);
6803 UNUSED(TimerIdx);
6804
6805
6806
6807
6808 }
6809
6810
6811
6812
6813
6814
6815
6816
6817
6818
6819
6820
6821
6822
6823 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
6824 uint32_t TimerIdx)
6825 {
6826
6827 UNUSED(hhrtim);
6828 UNUSED(TimerIdx);
6829
6830
6831
6832
6833 }
6834
6835
6836
6837
6838
6839
6840
6841
6842
6843
6844
6845
6846
6847 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
6848 uint32_t TimerIdx)
6849 {
6850
6851 UNUSED(hhrtim);
6852 UNUSED(TimerIdx);
6853
6854
6855
6856
6857 }
6858
6859
6860
6861
6862
6863
6864
6865
6866
6867
6868
6869
6870
6871 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
6872 uint32_t TimerIdx)
6873 {
6874
6875 UNUSED(hhrtim);
6876 UNUSED(TimerIdx);
6877
6878
6879
6880
6881 }
6882
6883
6884
6885
6886
6887
6888
6889
6890
6891
6892
6893
6894
6895 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
6896 uint32_t TimerIdx)
6897 {
6898
6899 UNUSED(hhrtim);
6900 UNUSED(TimerIdx);
6901
6902
6903
6904
6905 }
6906
6907
6908
6909
6910
6911
6912
6913
6914
6915
6916
6917
6918
6919 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
6920 uint32_t TimerIdx)
6921 {
6922
6923 UNUSED(hhrtim);
6924 UNUSED(TimerIdx);
6925
6926
6927
6928
6929 }
6930
6931
6932
6933
6934
6935
6936
6937
6938
6939
6940
6941
6942
6943
6944 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
6945 uint32_t TimerIdx)
6946 {
6947
6948 UNUSED(hhrtim);
6949 UNUSED(TimerIdx);
6950
6951
6952
6953
6954 }
6955
6956
6957
6958
6959
6960
6961 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
6962 {
6963
6964 UNUSED(hhrtim);
6965
6966
6967
6968
6969 }
6970
6971 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
6972
6973
6974
6975
6976
6977
6978
6979
6980
6981
6982
6983
6984
6985
6986
6987
6988
6989
6990
6991 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,
6992 HAL_HRTIM_CallbackIDTypeDef CallbackID,
6993 pHRTIM_CallbackTypeDef pCallback)
6994 {
6995 HAL_StatusTypeDef status = HAL_OK;
6996
6997 if (pCallback == NULL)
6998 {
6999
7000 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7001
7002 return HAL_ERROR;
7003 }
7004
7005
7006 __HAL_LOCK(hhrtim);
7007
7008 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7009 {
7010 switch (CallbackID)
7011 {
7012 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
7013 hhrtim->Fault1Callback = pCallback;
7014 break;
7015
7016 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
7017 hhrtim->Fault2Callback = pCallback;
7018 break;
7019
7020 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
7021 hhrtim->Fault3Callback = pCallback;
7022 break;
7023
7024 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
7025 hhrtim->Fault4Callback = pCallback;
7026 break;
7027
7028 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
7029 hhrtim->Fault5Callback = pCallback;
7030 break;
7031
7032 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
7033 hhrtim->SystemFaultCallback = pCallback;
7034 break;
7035
7036
7037 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
7038 hhrtim->BurstModePeriodCallback = pCallback;
7039 break;
7040
7041 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
7042 hhrtim->SynchronizationEventCallback = pCallback;
7043 break;
7044
7045 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
7046 hhrtim->ErrorCallback = pCallback;
7047 break;
7048
7049 case HAL_HRTIM_MSPINIT_CB_ID :
7050 hhrtim->MspInitCallback = pCallback;
7051 break;
7052
7053 case HAL_HRTIM_MSPDEINIT_CB_ID :
7054 hhrtim->MspDeInitCallback = pCallback;
7055 break;
7056
7057 default :
7058
7059 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7060
7061
7062 status = HAL_ERROR;
7063 break;
7064 }
7065 }
7066 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
7067 {
7068 switch (CallbackID)
7069 {
7070 case HAL_HRTIM_MSPINIT_CB_ID :
7071 hhrtim->MspInitCallback = pCallback;
7072 break;
7073
7074 case HAL_HRTIM_MSPDEINIT_CB_ID :
7075 hhrtim->MspDeInitCallback = pCallback;
7076 break;
7077
7078 default :
7079
7080 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7081
7082
7083 status = HAL_ERROR;
7084 break;
7085 }
7086 }
7087 else
7088 {
7089
7090 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7091
7092
7093 status = HAL_ERROR;
7094 }
7095
7096
7097 __HAL_UNLOCK(hhrtim);
7098
7099 return status;
7100 }
7101
7102
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115
7116
7117
7118
7119
7120 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7121 HAL_HRTIM_CallbackIDTypeDef CallbackID)
7122 {
7123 HAL_StatusTypeDef status = HAL_OK;
7124
7125
7126 __HAL_LOCK(hhrtim);
7127
7128 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7129 {
7130 switch (CallbackID)
7131 {
7132 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
7133 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
7134 break;
7135
7136 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
7137 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
7138 break;
7139
7140 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
7141 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
7142 break;
7143
7144 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
7145 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
7146 break;
7147
7148 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
7149 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
7150 break;
7151
7152 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
7153 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
7154 break;
7155
7156
7157 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
7158 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
7159 break;
7160
7161 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
7162 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
7163 break;
7164
7165 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
7166 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
7167 break;
7168
7169 case HAL_HRTIM_MSPINIT_CB_ID :
7170 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
7171 break;
7172
7173 case HAL_HRTIM_MSPDEINIT_CB_ID :
7174 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
7175 break;
7176
7177 default :
7178
7179 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7180
7181
7182 status = HAL_ERROR;
7183 break;
7184 }
7185 }
7186 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
7187 {
7188 switch (CallbackID)
7189 {
7190 case HAL_HRTIM_MSPINIT_CB_ID :
7191 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
7192 break;
7193
7194 case HAL_HRTIM_MSPDEINIT_CB_ID :
7195 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
7196 break;
7197
7198 default :
7199
7200 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7201
7202
7203 status = HAL_ERROR;
7204 break;
7205 }
7206 }
7207 else
7208 {
7209
7210 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7211
7212
7213 status = HAL_ERROR;
7214 }
7215
7216
7217 __HAL_UNLOCK(hhrtim);
7218
7219 return status;
7220 }
7221
7222
7223
7224
7225
7226
7227
7228
7229
7230
7231
7232
7233
7234
7235
7236
7237
7238
7239
7240
7241
7242
7243
7244
7245 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7246 HAL_HRTIM_CallbackIDTypeDef CallbackID,
7247 pHRTIM_TIMxCallbackTypeDef pCallback)
7248 {
7249 HAL_StatusTypeDef status = HAL_OK;
7250
7251 if (pCallback == NULL)
7252 {
7253
7254 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7255
7256 return HAL_ERROR;
7257 }
7258
7259
7260 __HAL_LOCK(hhrtim);
7261
7262 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7263 {
7264 switch (CallbackID)
7265 {
7266 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
7267 hhrtim->RegistersUpdateCallback = pCallback;
7268 break;
7269
7270 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
7271 hhrtim->RepetitionEventCallback = pCallback;
7272 break;
7273
7274 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
7275 hhrtim->Compare1EventCallback = pCallback;
7276 break;
7277
7278 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
7279 hhrtim->Compare2EventCallback = pCallback;
7280 break;
7281
7282 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
7283 hhrtim->Compare3EventCallback = pCallback;
7284 break;
7285
7286 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
7287 hhrtim->Compare4EventCallback = pCallback;
7288 break;
7289
7290 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
7291 hhrtim->Capture1EventCallback = pCallback;
7292 break;
7293
7294 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
7295 hhrtim->Capture2EventCallback = pCallback;
7296 break;
7297
7298 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
7299 hhrtim->DelayedProtectionCallback = pCallback;
7300 break;
7301
7302 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
7303 hhrtim->CounterResetCallback = pCallback;
7304 break;
7305
7306 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
7307 hhrtim->Output1SetCallback = pCallback;
7308 break;
7309
7310 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
7311 hhrtim->Output1ResetCallback = pCallback;
7312 break;
7313
7314 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
7315 hhrtim->Output2SetCallback = pCallback;
7316 break;
7317
7318 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
7319 hhrtim->Output2ResetCallback = pCallback;
7320 break;
7321
7322 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
7323 hhrtim->BurstDMATransferCallback = pCallback;
7324 break;
7325
7326 default :
7327
7328 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7329
7330
7331 status = HAL_ERROR;
7332 break;
7333 }
7334 }
7335 else
7336 {
7337
7338 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7339
7340
7341 status = HAL_ERROR;
7342 }
7343
7344
7345 __HAL_UNLOCK(hhrtim);
7346
7347 return status;
7348 }
7349
7350
7351
7352
7353
7354
7355
7356
7357
7358
7359
7360
7361
7362
7363
7364
7365
7366
7367
7368
7369
7370
7371
7372 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7373 HAL_HRTIM_CallbackIDTypeDef CallbackID)
7374 {
7375 HAL_StatusTypeDef status = HAL_OK;
7376
7377
7378 __HAL_LOCK(hhrtim);
7379
7380 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7381 {
7382 switch (CallbackID)
7383 {
7384 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
7385 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
7386 break;
7387
7388 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
7389 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
7390 break;
7391
7392 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
7393 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
7394 break;
7395
7396 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
7397 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
7398 break;
7399
7400 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
7401 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
7402 break;
7403
7404 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
7405 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
7406 break;
7407
7408 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
7409 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
7410 break;
7411
7412 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
7413 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
7414 break;
7415
7416 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
7417 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
7418 break;
7419
7420 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
7421 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
7422 break;
7423
7424 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
7425 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
7426 break;
7427
7428 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
7429 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
7430 break;
7431
7432 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
7433 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
7434 break;
7435
7436 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
7437 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
7438 break;
7439
7440 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
7441 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
7442 break;
7443
7444 default :
7445
7446 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7447
7448
7449 status = HAL_ERROR;
7450 break;
7451 }
7452 }
7453 else
7454 {
7455
7456 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7457
7458
7459 status = HAL_ERROR;
7460 }
7461
7462
7463 __HAL_UNLOCK(hhrtim);
7464
7465 return status;
7466 }
7467 #endif
7468
7469
7470
7471
7472
7473
7474
7475
7476
7477
7478
7479
7480
7481
7482
7483
7484
7485
7486 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
7487 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
7488 {
7489 uint32_t hrtim_mcr;
7490
7491
7492 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
7493
7494
7495 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
7496 hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
7497
7498
7499 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
7500 hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
7501
7502
7503 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
7504 hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
7505 hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
7506 }
7507
7508
7509
7510
7511
7512
7513
7514
7515 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
7516 uint32_t TimerIdx ,
7517 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
7518 {
7519 uint32_t hrtim_timcr;
7520
7521
7522 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
7523
7524
7525 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
7526 hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
7527
7528
7529 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
7530 hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
7531
7532
7533 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
7534 hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
7535 hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
7536 }
7537
7538
7539
7540
7541
7542
7543
7544 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
7545 const HRTIM_TimerCfgTypeDef * pTimerCfg)
7546 {
7547 uint32_t hrtim_mcr;
7548 uint32_t hrtim_bmcr;
7549
7550
7551 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
7552 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
7553
7554
7555 hrtim_mcr &= ~(HRTIM_MCR_HALF);
7556 hrtim_mcr |= pTimerCfg->HalfModeEnable;
7557
7558
7559 hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
7560 hrtim_mcr |= pTimerCfg->StartOnSync;
7561
7562
7563 hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
7564 hrtim_mcr |= pTimerCfg->ResetOnSync;
7565
7566
7567 hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
7568 hrtim_mcr |= pTimerCfg->DACSynchro;
7569
7570
7571 hrtim_mcr &= ~(HRTIM_MCR_PREEN);
7572 hrtim_mcr |= pTimerCfg->PreloadEnable;
7573
7574
7575 hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
7576 hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
7577
7578
7579 hrtim_mcr &= ~(HRTIM_MCR_MREPU);
7580 hrtim_mcr |= pTimerCfg->RepetitionUpdate;
7581
7582
7583 hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
7584 hrtim_bmcr |= pTimerCfg->BurstMode;
7585
7586
7587 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
7588 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
7589 }
7590
7591
7592
7593
7594
7595
7596
7597
7598 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
7599 uint32_t TimerIdx,
7600 const HRTIM_TimerCfgTypeDef * pTimerCfg)
7601 {
7602 uint32_t hrtim_timcr;
7603 uint32_t hrtim_timfltr;
7604 uint32_t hrtim_timoutr;
7605 uint32_t hrtim_timrstr;
7606 uint32_t hrtim_bmcr;
7607
7608
7609 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
7610
7611
7612 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
7613 hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
7614 hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
7615 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
7616
7617
7618 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
7619 hrtim_timcr |= pTimerCfg->HalfModeEnable;
7620
7621
7622 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
7623 hrtim_timcr |= pTimerCfg->StartOnSync;
7624
7625
7626 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
7627 hrtim_timcr |= pTimerCfg->ResetOnSync;
7628
7629
7630 hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
7631 hrtim_timcr |= pTimerCfg->DACSynchro;
7632
7633
7634 hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
7635 hrtim_timcr |= pTimerCfg->PreloadEnable;
7636
7637
7638 hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
7639 hrtim_timcr |= pTimerCfg->UpdateGating;
7640
7641
7642 hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
7643 if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
7644 {
7645 hrtim_timcr |= HRTIM_TIMCR_TREPU;
7646 }
7647
7648
7649 hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
7650 hrtim_timcr |= pTimerCfg->PushPull;
7651
7652
7653 hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
7654 hrtim_timcr |= pTimerCfg->ResetUpdate;
7655
7656
7657 hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
7658 hrtim_timcr |= pTimerCfg->UpdateTrigger;
7659
7660
7661 hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
7662 hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
7663
7664
7665 hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
7666 hrtim_timfltr |= pTimerCfg->FaultLock;
7667
7668
7669 if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
7670 {
7671
7672 hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
7673 hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
7674 }
7675
7676
7677
7678
7679
7680 if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
7681 && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
7682 || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
7683 {
7684 hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
7685 hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
7686 }
7687
7688
7689 hrtim_timrstr = pTimerCfg->ResetTrigger;
7690
7691
7692 switch (TimerIdx)
7693 {
7694 case HRTIM_TIMERINDEX_TIMER_A:
7695 {
7696 hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
7697 hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
7698 break;
7699 }
7700
7701 case HRTIM_TIMERINDEX_TIMER_B:
7702 {
7703 hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
7704 hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
7705 break;
7706 }
7707
7708 case HRTIM_TIMERINDEX_TIMER_C:
7709 {
7710 hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
7711 hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
7712 break;
7713 }
7714
7715 case HRTIM_TIMERINDEX_TIMER_D:
7716 {
7717 hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
7718 hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
7719 break;
7720 }
7721
7722 case HRTIM_TIMERINDEX_TIMER_E:
7723 {
7724 hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
7725 hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
7726 break;
7727 }
7728
7729 default:
7730 break;
7731 }
7732
7733
7734 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
7735 hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
7736 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
7737 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
7738 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
7739 }
7740
7741
7742
7743
7744
7745
7746
7747
7748
7749 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
7750 uint32_t TimerIdx,
7751 uint32_t CaptureUnit,
7752 uint32_t Event)
7753 {
7754 uint32_t CaptureTrigger = 0xFFFFFFFFU;
7755
7756 switch (Event)
7757 {
7758 case HRTIM_EVENT_1:
7759 {
7760 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
7761 break;
7762 }
7763
7764 case HRTIM_EVENT_2:
7765 {
7766 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
7767 break;
7768 }
7769
7770 case HRTIM_EVENT_3:
7771 {
7772 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
7773 break;
7774 }
7775
7776 case HRTIM_EVENT_4:
7777 {
7778 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
7779 break;
7780 }
7781
7782 case HRTIM_EVENT_5:
7783 {
7784 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
7785 break;
7786 }
7787
7788 case HRTIM_EVENT_6:
7789 {
7790 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
7791 break;
7792 }
7793
7794 case HRTIM_EVENT_7:
7795 {
7796 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
7797 break;
7798 }
7799
7800 case HRTIM_EVENT_8:
7801 {
7802 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
7803 break;
7804 }
7805
7806 case HRTIM_EVENT_9:
7807 {
7808 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
7809 break;
7810 }
7811
7812 case HRTIM_EVENT_10:
7813 {
7814 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
7815 break;
7816 }
7817
7818 default:
7819 break;
7820 }
7821
7822 switch (CaptureUnit)
7823 {
7824 case HRTIM_CAPTUREUNIT_1:
7825 {
7826 hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
7827 break;
7828 }
7829
7830 case HRTIM_CAPTUREUNIT_2:
7831 {
7832 hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
7833 break;
7834 }
7835
7836 default:
7837 break;
7838 }
7839 }
7840
7841
7842
7843
7844
7845
7846
7847
7848
7849 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
7850 uint32_t TimerIdx,
7851 uint32_t Output,
7852 const HRTIM_OutputCfgTypeDef * pOutputCfg)
7853 {
7854 uint32_t hrtim_outr;
7855 uint32_t hrtim_dtr;
7856
7857 uint32_t shift = 0U;
7858
7859 hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
7860 hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
7861
7862 switch (Output)
7863 {
7864 case HRTIM_OUTPUT_TA1:
7865 case HRTIM_OUTPUT_TB1:
7866 case HRTIM_OUTPUT_TC1:
7867 case HRTIM_OUTPUT_TD1:
7868 case HRTIM_OUTPUT_TE1:
7869 {
7870
7871 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
7872 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
7873 break;
7874 }
7875
7876 case HRTIM_OUTPUT_TA2:
7877 case HRTIM_OUTPUT_TB2:
7878 case HRTIM_OUTPUT_TC2:
7879 case HRTIM_OUTPUT_TD2:
7880 case HRTIM_OUTPUT_TE2:
7881 {
7882
7883 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
7884 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
7885 shift = 16U;
7886 break;
7887 }
7888
7889 default:
7890 break;
7891 }
7892
7893
7894 hrtim_outr &= ~((HRTIM_OUTR_POL1 |
7895 HRTIM_OUTR_IDLM1 |
7896 HRTIM_OUTR_IDLES1|
7897 HRTIM_OUTR_FAULT1|
7898 HRTIM_OUTR_CHP1 |
7899 HRTIM_OUTR_DIDL1) << shift);
7900
7901
7902 hrtim_outr |= (pOutputCfg->Polarity << shift);
7903
7904
7905 hrtim_outr |= (pOutputCfg->IdleMode << shift);
7906
7907
7908 hrtim_outr |= (pOutputCfg->IdleLevel << shift);
7909
7910
7911 hrtim_outr |= (pOutputCfg->FaultLevel << shift);
7912
7913
7914 hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
7915
7916
7917
7918
7919
7920
7921
7922 if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
7923 ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
7924 ((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET))
7925 {
7926 hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
7927 }
7928
7929
7930 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
7931 }
7932
7933
7934
7935
7936
7937
7938
7939
7940 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
7941 uint32_t Event,
7942 const HRTIM_EventCfgTypeDef *pEventCfg)
7943 {
7944 uint32_t hrtim_eecr1;
7945 uint32_t hrtim_eecr2;
7946 uint32_t hrtim_eecr3;
7947
7948
7949 hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
7950 hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
7951 hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
7952
7953 switch (Event)
7954 {
7955 case HRTIM_EVENT_NONE:
7956 {
7957
7958 hhrtim->Instance->sCommonRegs.EECR1 = 0U;
7959 hhrtim->Instance->sCommonRegs.EECR2 = 0U;
7960 hhrtim->Instance->sCommonRegs.EECR3 = 0U;
7961 break;
7962 }
7963
7964 case HRTIM_EVENT_1:
7965 {
7966 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
7967 hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC);
7968 hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
7969 hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS);
7970
7971 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7972
7973 hrtim_eecr1 |= (pEventCfg->FastMode & HRTIM_EECR1_EE1FAST);
7974 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7975 break;
7976 }
7977
7978 case HRTIM_EVENT_2:
7979 {
7980 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
7981 hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC);
7982 hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL);
7983 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS);
7984
7985 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7986
7987 hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST);
7988 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7989 break;
7990 }
7991
7992 case HRTIM_EVENT_3:
7993 {
7994 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
7995 hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC);
7996 hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL);
7997 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS);
7998
7999 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8000
8001 hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST);
8002 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8003 break;
8004 }
8005
8006 case HRTIM_EVENT_4:
8007 {
8008 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
8009 hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC);
8010 hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL);
8011 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS);
8012
8013 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8014
8015 hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST);
8016 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8017 break;
8018 }
8019
8020 case HRTIM_EVENT_5:
8021 {
8022 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
8023 hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC);
8024 hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL);
8025 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS);
8026
8027 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8028
8029 hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST);
8030 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8031 break;
8032 }
8033
8034 case HRTIM_EVENT_6:
8035 {
8036 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
8037 hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC);
8038 hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
8039 hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS);
8040 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
8041 hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F);
8042
8043 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8044 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8045 break;
8046 }
8047
8048 case HRTIM_EVENT_7:
8049 {
8050 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
8051 hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC);
8052 hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL);
8053 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS);
8054 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
8055 hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F);
8056
8057 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8058 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8059 break;
8060 }
8061
8062 case HRTIM_EVENT_8:
8063 {
8064 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
8065 hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC);
8066 hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL);
8067 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS);
8068 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
8069 hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F );
8070
8071 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8072 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8073 break;
8074 }
8075
8076 case HRTIM_EVENT_9:
8077 {
8078 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
8079 hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC);
8080 hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL);
8081 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS);
8082 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
8083 hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F);
8084
8085 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8086 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8087 break;
8088 }
8089
8090 case HRTIM_EVENT_10:
8091 {
8092 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
8093 hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC);
8094 hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL);
8095 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS);
8096 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
8097 hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F);
8098
8099 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8100 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8101 break;
8102 }
8103
8104 default:
8105 break;
8106 }
8107 }
8108
8109
8110
8111
8112
8113
8114
8115
8116 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
8117 uint32_t TimerIdx,
8118 uint32_t Event)
8119 {
8120 switch (Event)
8121 {
8122 case HRTIM_EVENT_1:
8123 {
8124 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
8125 break;
8126 }
8127
8128 case HRTIM_EVENT_2:
8129 {
8130 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
8131 break;
8132 }
8133
8134 case HRTIM_EVENT_3:
8135 {
8136 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
8137 break;
8138 }
8139
8140 case HRTIM_EVENT_4:
8141 {
8142 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
8143 break;
8144 }
8145
8146 case HRTIM_EVENT_5:
8147 {
8148 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
8149 break;
8150 }
8151
8152 case HRTIM_EVENT_6:
8153 {
8154 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
8155 break;
8156 }
8157
8158 case HRTIM_EVENT_7:
8159 {
8160 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
8161 break;
8162 }
8163
8164 case HRTIM_EVENT_8:
8165 {
8166 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
8167 break;
8168 }
8169
8170 case HRTIM_EVENT_9:
8171 {
8172 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
8173 break;
8174 }
8175
8176 case HRTIM_EVENT_10:
8177 {
8178 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
8179 break;
8180 }
8181
8182 default:
8183 break;
8184 }
8185 }
8186
8187
8188
8189
8190
8191
8192
8193
8194
8195
8196
8197
8198
8199
8200
8201
8202
8203
8204
8205
8206 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
8207 uint32_t TimerIdx,
8208 uint32_t OCChannel)
8209 {
8210 uint32_t hrtim_set;
8211 uint32_t hrtim_reset;
8212 uint32_t interrupt = 0U;
8213
8214 switch (OCChannel)
8215 {
8216 case HRTIM_OUTPUT_TA1:
8217 case HRTIM_OUTPUT_TB1:
8218 case HRTIM_OUTPUT_TC1:
8219 case HRTIM_OUTPUT_TD1:
8220 case HRTIM_OUTPUT_TE1:
8221 {
8222
8223 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
8224 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
8225
8226 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8227 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8228 {
8229
8230 interrupt = HRTIM_TIM_IT_CMP1;
8231 }
8232 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8233 (hrtim_reset == 0U))
8234 {
8235
8236 interrupt = HRTIM_TIM_IT_SET1;
8237 }
8238 else if ((hrtim_set == 0U) &&
8239 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8240 {
8241
8242 interrupt = HRTIM_TIM_IT_RST1;
8243 }
8244 else
8245 {
8246
8247 }
8248 break;
8249 }
8250
8251 case HRTIM_OUTPUT_TA2:
8252 case HRTIM_OUTPUT_TB2:
8253 case HRTIM_OUTPUT_TC2:
8254 case HRTIM_OUTPUT_TD2:
8255 case HRTIM_OUTPUT_TE2:
8256 {
8257
8258 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
8259 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
8260
8261 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8262 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8263 {
8264
8265 interrupt = HRTIM_TIM_IT_CMP2;
8266 }
8267 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8268 (hrtim_reset == 0U))
8269 {
8270
8271 interrupt = HRTIM_TIM_IT_SET2;
8272 }
8273 else if ((hrtim_set == 0U) &&
8274 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8275 {
8276
8277 interrupt = HRTIM_TIM_IT_RST2;
8278 }
8279 else
8280 {
8281
8282 }
8283 break;
8284 }
8285
8286 default:
8287 break;
8288 }
8289
8290 return interrupt;
8291 }
8292
8293
8294
8295
8296
8297
8298
8299
8300
8301
8302
8303
8304
8305
8306
8307
8308
8309
8310
8311
8312 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
8313 uint32_t TimerIdx,
8314 uint32_t OCChannel)
8315 {
8316 uint32_t hrtim_set;
8317 uint32_t hrtim_reset;
8318 uint32_t dma_request = 0U;
8319
8320 switch (OCChannel)
8321 {
8322 case HRTIM_OUTPUT_TA1:
8323 case HRTIM_OUTPUT_TB1:
8324 case HRTIM_OUTPUT_TC1:
8325 case HRTIM_OUTPUT_TD1:
8326 case HRTIM_OUTPUT_TE1:
8327 {
8328
8329 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
8330 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
8331
8332 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8333 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8334 {
8335
8336 dma_request = HRTIM_TIM_DMA_CMP1;
8337 }
8338 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8339 (hrtim_reset == 0U))
8340 {
8341
8342 dma_request = HRTIM_TIM_DMA_SET1;
8343 }
8344 else if ((hrtim_set == 0U) &&
8345 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8346 {
8347
8348 dma_request = HRTIM_TIM_DMA_RST1;
8349 }
8350 else
8351 {
8352
8353 }
8354 break;
8355 }
8356
8357 case HRTIM_OUTPUT_TA2:
8358 case HRTIM_OUTPUT_TB2:
8359 case HRTIM_OUTPUT_TC2:
8360 case HRTIM_OUTPUT_TD2:
8361 case HRTIM_OUTPUT_TE2:
8362 {
8363
8364 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
8365 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
8366
8367 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8368 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8369 {
8370
8371 dma_request = HRTIM_TIM_DMA_CMP2;
8372 }
8373 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8374 (hrtim_reset == 0U))
8375 {
8376
8377 dma_request = HRTIM_TIM_DMA_SET2;
8378 }
8379 else if ((hrtim_set == 0U) &&
8380 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8381 {
8382
8383 dma_request = HRTIM_TIM_DMA_RST2;
8384 }
8385 else
8386 {
8387
8388 }
8389 break;
8390 }
8391
8392 default:
8393 break;
8394 }
8395
8396 return dma_request;
8397 }
8398
8399 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,
8400 uint32_t TimerIdx)
8401 {
8402 DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
8403
8404 switch (TimerIdx)
8405 {
8406 case HRTIM_TIMERINDEX_MASTER:
8407 {
8408 hdma = hhrtim->hdmaMaster;
8409 break;
8410 }
8411
8412 case HRTIM_TIMERINDEX_TIMER_A:
8413 {
8414 hdma = hhrtim->hdmaTimerA;
8415 break;
8416 }
8417
8418 case HRTIM_TIMERINDEX_TIMER_B:
8419 {
8420 hdma = hhrtim->hdmaTimerB;
8421 break;
8422 }
8423
8424 case HRTIM_TIMERINDEX_TIMER_C:
8425 {
8426 hdma = hhrtim->hdmaTimerC;
8427 break;
8428 }
8429
8430 case HRTIM_TIMERINDEX_TIMER_D:
8431 {
8432 hdma = hhrtim->hdmaTimerD;
8433 break;
8434 }
8435
8436 case HRTIM_TIMERINDEX_TIMER_E:
8437 {
8438 hdma = hhrtim->hdmaTimerE;
8439 break;
8440 }
8441
8442 default:
8443 break;
8444 }
8445
8446 return hdma;
8447 }
8448
8449 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,
8450 const DMA_HandleTypeDef * hdma)
8451 {
8452 uint32_t timed_idx = 0xFFFFFFFFU;
8453
8454 if (hdma == hhrtim->hdmaMaster)
8455 {
8456 timed_idx = HRTIM_TIMERINDEX_MASTER;
8457 }
8458 else if (hdma == hhrtim->hdmaTimerA)
8459 {
8460 timed_idx = HRTIM_TIMERINDEX_TIMER_A;
8461 }
8462 else if (hdma == hhrtim->hdmaTimerB)
8463 {
8464 timed_idx = HRTIM_TIMERINDEX_TIMER_B;
8465 }
8466 else if (hdma == hhrtim->hdmaTimerC)
8467 {
8468 timed_idx = HRTIM_TIMERINDEX_TIMER_C;
8469 }
8470 else if (hdma == hhrtim->hdmaTimerD)
8471 {
8472 timed_idx = HRTIM_TIMERINDEX_TIMER_D;
8473 }
8474 else if (hdma == hhrtim->hdmaTimerE)
8475 {
8476 timed_idx = HRTIM_TIMERINDEX_TIMER_E;
8477 }
8478 else
8479 {
8480
8481 }
8482 return timed_idx;
8483 }
8484
8485
8486
8487
8488
8489
8490
8491
8492 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
8493 uint32_t TimerIdx)
8494 {
8495 switch (TimerIdx)
8496 {
8497 case HRTIM_TIMERINDEX_MASTER:
8498 {
8499 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
8500 break;
8501 }
8502
8503 case HRTIM_TIMERINDEX_TIMER_A:
8504 {
8505 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
8506 break;
8507 }
8508
8509 case HRTIM_TIMERINDEX_TIMER_B:
8510 {
8511 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
8512 break;
8513 }
8514
8515 case HRTIM_TIMERINDEX_TIMER_C:
8516 {
8517 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
8518 break;
8519 }
8520
8521 case HRTIM_TIMERINDEX_TIMER_D:
8522 {
8523 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
8524 break;
8525 }
8526
8527 case HRTIM_TIMERINDEX_TIMER_E:
8528 {
8529 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
8530 break;
8531 }
8532
8533 default:
8534 break;
8535 }
8536 }
8537
8538
8539
8540
8541
8542
8543
8544 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
8545 {
8546 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
8547 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
8548
8549
8550 if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET)
8551 {
8552 if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET)
8553 {
8554 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
8555
8556
8557 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8558 hhrtim->Fault1Callback(hhrtim);
8559 #else
8560 HAL_HRTIM_Fault1Callback(hhrtim);
8561 #endif
8562 }
8563 }
8564
8565
8566 if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET)
8567 {
8568 if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET)
8569 {
8570 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
8571
8572
8573 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8574 hhrtim->Fault2Callback(hhrtim);
8575 #else
8576 HAL_HRTIM_Fault2Callback(hhrtim);
8577 #endif
8578 }
8579 }
8580
8581
8582 if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET)
8583 {
8584 if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET)
8585 {
8586 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
8587
8588
8589 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8590 hhrtim->Fault3Callback(hhrtim);
8591 #else
8592 HAL_HRTIM_Fault3Callback(hhrtim);
8593 #endif
8594 }
8595 }
8596
8597
8598 if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET)
8599 {
8600 if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET)
8601 {
8602 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
8603
8604
8605 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8606 hhrtim->Fault4Callback(hhrtim);
8607 #else
8608 HAL_HRTIM_Fault4Callback(hhrtim);
8609 #endif
8610 }
8611 }
8612
8613
8614 if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET)
8615 {
8616 if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET)
8617 {
8618 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
8619
8620
8621 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8622 hhrtim->Fault5Callback(hhrtim);
8623 #else
8624 HAL_HRTIM_Fault5Callback(hhrtim);
8625 #endif
8626 }
8627 }
8628
8629
8630 if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
8631 {
8632 if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET)
8633 {
8634 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
8635
8636
8637 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8638 hhrtim->SystemFaultCallback(hhrtim);
8639 #else
8640 HAL_HRTIM_SystemFaultCallback(hhrtim);
8641 #endif
8642 }
8643 }
8644 }
8645
8646
8647
8648
8649
8650
8651 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
8652 {
8653 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
8654 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
8655 uint32_t misrflags = READ_REG(hhrtim->Instance->sMasterRegs.MISR);
8656 uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER);
8657
8658
8659 if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET)
8660 {
8661 if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET)
8662 {
8663 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
8664
8665
8666 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8667 hhrtim->BurstModePeriodCallback(hhrtim);
8668 #else
8669 HAL_HRTIM_BurstModePeriodCallback(hhrtim);
8670 #endif
8671 }
8672 }
8673
8674
8675 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
8676 {
8677 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET)
8678 {
8679 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
8680
8681
8682 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8683 hhrtim->Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8684 #else
8685 HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8686 #endif
8687 }
8688 }
8689
8690
8691 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
8692 {
8693 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET)
8694 {
8695 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
8696
8697
8698 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8699 hhrtim->Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8700 #else
8701 HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8702 #endif
8703 }
8704 }
8705
8706
8707 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
8708 {
8709 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET)
8710 {
8711 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
8712
8713
8714 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8715 hhrtim->Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8716 #else
8717 HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8718 #endif
8719 }
8720 }
8721
8722
8723 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
8724 {
8725 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET)
8726 {
8727 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
8728
8729
8730 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8731 hhrtim->Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8732 #else
8733 HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8734 #endif
8735 }
8736 }
8737
8738
8739 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
8740 {
8741 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET)
8742 {
8743 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
8744
8745
8746 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8747 hhrtim->RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8748 #else
8749 HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8750 #endif
8751 }
8752 }
8753
8754
8755 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
8756 {
8757 if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET)
8758 {
8759 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
8760
8761
8762 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8763 hhrtim->SynchronizationEventCallback(hhrtim);
8764 #else
8765 HAL_HRTIM_SynchronizationEventCallback(hhrtim);
8766 #endif
8767 }
8768 }
8769
8770
8771 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
8772 {
8773 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET)
8774 {
8775 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
8776
8777
8778 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8779 hhrtim->RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8780 #else
8781 HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8782 #endif
8783 }
8784 }
8785 }
8786
8787
8788
8789
8790
8791
8792
8793
8794
8795
8796
8797
8798
8799 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
8800 uint32_t TimerIdx)
8801 {
8802 uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR);
8803 uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER);
8804
8805
8806 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
8807 {
8808 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET)
8809 {
8810 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
8811
8812
8813 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8814 hhrtim->Compare1EventCallback(hhrtim, TimerIdx);
8815 #else
8816 HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
8817 #endif
8818 }
8819 }
8820
8821
8822 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
8823 {
8824 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET)
8825 {
8826 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
8827
8828
8829 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8830 hhrtim->Compare2EventCallback(hhrtim, TimerIdx);
8831 #else
8832 HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
8833 #endif
8834 }
8835 }
8836
8837
8838 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
8839 {
8840 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET)
8841 {
8842 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
8843
8844
8845 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8846 hhrtim->Compare3EventCallback(hhrtim, TimerIdx);
8847 #else
8848 HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
8849 #endif
8850 }
8851 }
8852
8853
8854 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
8855 {
8856 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET)
8857 {
8858 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
8859
8860
8861 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8862 hhrtim->Compare4EventCallback(hhrtim, TimerIdx);
8863 #else
8864 HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
8865 #endif
8866 }
8867 }
8868
8869
8870 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
8871 {
8872 if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET)
8873 {
8874 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
8875
8876
8877 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8878 hhrtim->RepetitionEventCallback(hhrtim, TimerIdx);
8879 #else
8880 HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
8881 #endif
8882 }
8883 }
8884
8885
8886 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
8887 {
8888 if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET)
8889 {
8890 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
8891
8892
8893 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8894 hhrtim->RegistersUpdateCallback(hhrtim, TimerIdx);
8895 #else
8896 HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
8897 #endif
8898 }
8899 }
8900
8901
8902 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
8903 {
8904 if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET)
8905 {
8906 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
8907
8908
8909 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8910 hhrtim->Capture1EventCallback(hhrtim, TimerIdx);
8911 #else
8912 HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
8913 #endif
8914 }
8915 }
8916
8917
8918 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
8919 {
8920 if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET)
8921 {
8922 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
8923
8924
8925 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8926 hhrtim->Capture2EventCallback(hhrtim, TimerIdx);
8927 #else
8928 HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
8929 #endif
8930 }
8931 }
8932
8933
8934 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
8935 {
8936 if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET)
8937 {
8938 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
8939
8940
8941 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8942 hhrtim->Output1SetCallback(hhrtim, TimerIdx);
8943 #else
8944 HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
8945 #endif
8946 }
8947 }
8948
8949
8950 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
8951 {
8952 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET)
8953 {
8954 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
8955
8956
8957 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8958 hhrtim->Output1ResetCallback(hhrtim, TimerIdx);
8959 #else
8960 HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
8961 #endif
8962 }
8963 }
8964
8965
8966 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
8967 {
8968 if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET)
8969 {
8970 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
8971
8972
8973 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8974 hhrtim->Output2SetCallback(hhrtim, TimerIdx);
8975 #else
8976 HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
8977 #endif
8978 }
8979 }
8980
8981
8982 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
8983 {
8984 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET)
8985 {
8986 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
8987
8988
8989 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8990 hhrtim->Output2ResetCallback(hhrtim, TimerIdx);
8991 #else
8992 HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
8993 #endif
8994 }
8995 }
8996
8997
8998 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
8999 {
9000 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET)
9001 {
9002 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
9003
9004
9005 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9006 hhrtim->CounterResetCallback(hhrtim, TimerIdx);
9007 #else
9008 HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
9009 #endif
9010 }
9011 }
9012
9013
9014 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
9015 {
9016 if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET)
9017 {
9018 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
9019
9020
9021 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9022 hhrtim->DelayedProtectionCallback(hhrtim, TimerIdx);
9023 #else
9024 HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
9025 #endif
9026 }
9027 }
9028 }
9029
9030
9031
9032
9033
9034
9035 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
9036 {
9037 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9038
9039 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET)
9040 {
9041 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9042 hrtim->Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9043 #else
9044 HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9045 #endif
9046 }
9047 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET)
9048 {
9049 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9050 hrtim->Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9051 #else
9052 HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9053 #endif
9054 }
9055 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET)
9056 {
9057 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9058 hrtim->Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9059 #else
9060 HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9061 #endif
9062 }
9063 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET)
9064 {
9065 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9066 hrtim->Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9067 #else
9068 HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9069 #endif
9070 }
9071 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET)
9072 {
9073 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9074 hrtim->SynchronizationEventCallback(hrtim);
9075 #else
9076 HAL_HRTIM_SynchronizationEventCallback(hrtim);
9077 #endif
9078 }
9079 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET)
9080 {
9081 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9082 hrtim->RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9083 #else
9084 HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9085 #endif
9086 }
9087 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET)
9088 {
9089 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9090 hrtim->RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9091 #else
9092 HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9093 #endif
9094 }
9095 else
9096 {
9097
9098 }
9099 }
9100
9101
9102
9103
9104
9105
9106 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
9107 {
9108 uint8_t timer_idx;
9109
9110 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9111
9112 timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma);
9113
9114 if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;}
9115
9116 if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET)
9117 {
9118 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9119 hrtim->Compare1EventCallback(hrtim, timer_idx);
9120 #else
9121 HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
9122 #endif
9123 }
9124 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != (uint32_t)RESET)
9125 {
9126 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9127 hrtim->Compare2EventCallback(hrtim, timer_idx);
9128 #else
9129 HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
9130 #endif
9131 }
9132 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != (uint32_t)RESET)
9133 {
9134 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9135 hrtim->Compare3EventCallback(hrtim, timer_idx);
9136 #else
9137 HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
9138 #endif
9139 }
9140 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != (uint32_t)RESET)
9141 {
9142 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9143 hrtim->Compare4EventCallback(hrtim, timer_idx);
9144 #else
9145 HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
9146 #endif
9147 }
9148 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != (uint32_t)RESET)
9149 {
9150 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9151 hrtim->RegistersUpdateCallback(hrtim, timer_idx);
9152 #else
9153 HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
9154 #endif
9155 }
9156 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != (uint32_t)RESET)
9157 {
9158 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9159 hrtim->Capture1EventCallback(hrtim, timer_idx);
9160 #else
9161 HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
9162 #endif
9163 }
9164 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != (uint32_t)RESET)
9165 {
9166 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9167 hrtim->Capture2EventCallback(hrtim, timer_idx);
9168 #else
9169 HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
9170 #endif
9171 }
9172 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != (uint32_t)RESET)
9173 {
9174 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9175 hrtim->Output1SetCallback(hrtim, timer_idx);
9176 #else
9177 HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
9178 #endif
9179 }
9180 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != (uint32_t)RESET)
9181 {
9182 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9183 hrtim->Output1ResetCallback(hrtim, timer_idx);
9184 #else
9185 HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
9186 #endif
9187 }
9188 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != (uint32_t)RESET)
9189 {
9190 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9191 hrtim->Output2SetCallback(hrtim, timer_idx);
9192 #else
9193 HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
9194 #endif
9195 }
9196 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != (uint32_t)RESET)
9197 {
9198 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9199 hrtim->Output2ResetCallback(hrtim, timer_idx);
9200 #else
9201 HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
9202 #endif
9203 }
9204 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != (uint32_t)RESET)
9205 {
9206 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9207 hrtim->CounterResetCallback(hrtim, timer_idx);
9208 #else
9209 HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
9210 #endif
9211 }
9212 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != (uint32_t)RESET)
9213 {
9214 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9215 hrtim->DelayedProtectionCallback(hrtim, timer_idx);
9216 #else
9217 HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
9218 #endif
9219 }
9220 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != (uint32_t)RESET)
9221 {
9222 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9223 hrtim->RepetitionEventCallback(hrtim, timer_idx);
9224 #else
9225 HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
9226 #endif
9227 }
9228 else
9229 {
9230
9231 }
9232 }
9233
9234
9235
9236
9237
9238
9239 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
9240 {
9241 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9242
9243 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9244 hrtim->ErrorCallback(hrtim);
9245 #else
9246 HAL_HRTIM_ErrorCallback(hrtim);
9247 #endif
9248 }
9249
9250
9251
9252
9253
9254
9255 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
9256 {
9257 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9258
9259 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9260 hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
9261 #else
9262 HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
9263 #endif
9264 }
9265
9266
9267
9268
9269
9270
9271
9272
9273
9274 #endif
9275
9276 #endif
9277
9278
9279
9280