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0138 #include "stm32h7xx_hal.h"
0139
0140
0141
0142
0143 #ifdef HAL_GFXMMU_MODULE_ENABLED
0144 #if defined(GFXMMU)
0145
0146
0147
0148
0149
0150
0151
0152
0153 #define GFXMMU_LUTXL_FVB_OFFSET 8U
0154 #define GFXMMU_LUTXL_LVB_OFFSET 16U
0155 #define GFXMMU_CR_ITS_MASK 0x1FU
0156
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0185
0186 HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu)
0187 {
0188 HAL_StatusTypeDef status = HAL_OK;
0189
0190
0191 if(hgfxmmu == NULL)
0192 {
0193 status = HAL_ERROR;
0194 }
0195 else
0196 {
0197
0198 assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
0199 assert_param(IS_GFXMMU_BLOCKS_PER_LINE(hgfxmmu->Init.BlocksPerLine));
0200 assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf0Address));
0201 assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf1Address));
0202 assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf2Address));
0203 assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf3Address));
0204 assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.CachePrefetch.Activation));
0205 assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.Interrupts.Activation));
0206
0207 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
0208
0209 hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
0210
0211
0212 if(hgfxmmu->MspInitCallback == NULL)
0213 {
0214 hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
0215 }
0216 hgfxmmu->MspInitCallback(hgfxmmu);
0217 #else
0218
0219 HAL_GFXMMU_MspInit(hgfxmmu);
0220 #endif
0221
0222
0223 hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE |
0224 GFXMMU_CR_AMEIE | GFXMMU_CR_192BM | GFXMMU_CR_CE | GFXMMU_CR_CL |
0225 GFXMMU_CR_CLB | GFXMMU_CR_FC | GFXMMU_CR_PD | GFXMMU_CR_OC |
0226 GFXMMU_CR_OB);
0227 hgfxmmu->Instance->CR |= (hgfxmmu->Init.BlocksPerLine);
0228 if(hgfxmmu->Init.CachePrefetch.Activation == ENABLE)
0229 {
0230 assert_param(IS_GFXMMU_CACHE_LOCK(hgfxmmu->Init.CachePrefetch.CacheLock));
0231 assert_param(IS_GFXMMU_PREFETCH(hgfxmmu->Init.CachePrefetch.Prefetch));
0232 assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(hgfxmmu->Init.CachePrefetch.OutterBufferability));
0233 assert_param(IS_GFXMMU_OUTTER_CACHABILITY(hgfxmmu->Init.CachePrefetch.OutterCachability));
0234 hgfxmmu->Instance->CR |= (GFXMMU_CR_CE |
0235 hgfxmmu->Init.CachePrefetch.CacheLock |
0236 hgfxmmu->Init.CachePrefetch.Prefetch |
0237 hgfxmmu->Init.CachePrefetch.OutterBufferability |
0238 hgfxmmu->Init.CachePrefetch.OutterCachability);
0239 if(hgfxmmu->Init.CachePrefetch.CacheLock == GFXMMU_CACHE_LOCK_ENABLE)
0240 {
0241 assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(hgfxmmu->Init.CachePrefetch.CacheLockBuffer));
0242 assert_param(IS_GFXMMU_CACHE_FORCE(hgfxmmu->Init.CachePrefetch.CacheForce));
0243 hgfxmmu->Instance->CR |= (hgfxmmu->Init.CachePrefetch.CacheLockBuffer |
0244 hgfxmmu->Init.CachePrefetch.CacheForce);
0245 }
0246 }
0247 if(hgfxmmu->Init.Interrupts.Activation == ENABLE)
0248 {
0249 assert_param(IS_GFXMMU_INTERRUPTS(hgfxmmu->Init.Interrupts.UsedInterrupts));
0250 hgfxmmu->Instance->CR |= hgfxmmu->Init.Interrupts.UsedInterrupts;
0251 }
0252
0253
0254 hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue;
0255
0256
0257 hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address;
0258 hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address;
0259 hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address;
0260 hgfxmmu->Instance->B3CR = hgfxmmu->Init.Buffers.Buf3Address;
0261
0262
0263 if(hgfxmmu->Init.CachePrefetch.Activation == ENABLE)
0264 {
0265 hgfxmmu->Instance->CCR |= GFXMMU_CACHE_FORCE_INVALIDATE;
0266 }
0267
0268
0269 hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
0270
0271
0272 hgfxmmu->State = HAL_GFXMMU_STATE_READY;
0273 }
0274
0275 return status;
0276 }
0277
0278
0279
0280
0281
0282
0283 HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu)
0284 {
0285 HAL_StatusTypeDef status = HAL_OK;
0286
0287
0288 if(hgfxmmu == NULL)
0289 {
0290 status = HAL_ERROR;
0291 }
0292 else
0293 {
0294
0295 assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
0296
0297
0298 hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE |
0299 GFXMMU_CR_AMEIE);
0300
0301
0302 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
0303 if(hgfxmmu->MspDeInitCallback == NULL)
0304 {
0305 hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
0306 }
0307 hgfxmmu->MspDeInitCallback(hgfxmmu);
0308 #else
0309 HAL_GFXMMU_MspDeInit(hgfxmmu);
0310 #endif
0311
0312
0313 hgfxmmu->State = HAL_GFXMMU_STATE_RESET;
0314 }
0315
0316 return status;
0317 }
0318
0319
0320
0321
0322
0323
0324 __weak void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu)
0325 {
0326
0327 UNUSED(hgfxmmu);
0328
0329
0330
0331
0332 }
0333
0334
0335
0336
0337
0338
0339 __weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu)
0340 {
0341
0342 UNUSED(hgfxmmu);
0343
0344
0345
0346
0347 }
0348
0349 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
0350
0351
0352
0353
0354
0355
0356
0357
0358
0359
0360
0361
0362 HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
0363 HAL_GFXMMU_CallbackIDTypeDef CallbackID,
0364 pGFXMMU_CallbackTypeDef pCallback)
0365 {
0366 HAL_StatusTypeDef status = HAL_OK;
0367
0368 if(pCallback == NULL)
0369 {
0370
0371 hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
0372
0373 status = HAL_ERROR;
0374 }
0375 else
0376 {
0377 if(HAL_GFXMMU_STATE_READY == hgfxmmu->State)
0378 {
0379 switch (CallbackID)
0380 {
0381 case HAL_GFXMMU_ERROR_CB_ID :
0382 hgfxmmu->ErrorCallback = pCallback;
0383 break;
0384 case HAL_GFXMMU_MSPINIT_CB_ID :
0385 hgfxmmu->MspInitCallback = pCallback;
0386 break;
0387 case HAL_GFXMMU_MSPDEINIT_CB_ID :
0388 hgfxmmu->MspDeInitCallback = pCallback;
0389 break;
0390 default :
0391
0392 hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
0393
0394 status = HAL_ERROR;
0395 break;
0396 }
0397 }
0398 else if(HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
0399 {
0400 switch (CallbackID)
0401 {
0402 case HAL_GFXMMU_MSPINIT_CB_ID :
0403 hgfxmmu->MspInitCallback = pCallback;
0404 break;
0405 case HAL_GFXMMU_MSPDEINIT_CB_ID :
0406 hgfxmmu->MspDeInitCallback = pCallback;
0407 break;
0408 default :
0409
0410 hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
0411
0412 status = HAL_ERROR;
0413 break;
0414 }
0415 }
0416 else
0417 {
0418
0419 hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
0420
0421 status = HAL_ERROR;
0422 }
0423 }
0424 return status;
0425 }
0426
0427
0428
0429
0430
0431
0432
0433
0434
0435
0436
0437
0438 HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
0439 HAL_GFXMMU_CallbackIDTypeDef CallbackID)
0440 {
0441 HAL_StatusTypeDef status = HAL_OK;
0442
0443 if(HAL_GFXMMU_STATE_READY == hgfxmmu->State)
0444 {
0445 switch (CallbackID)
0446 {
0447 case HAL_GFXMMU_ERROR_CB_ID :
0448 hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
0449 break;
0450 case HAL_GFXMMU_MSPINIT_CB_ID :
0451 hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
0452 break;
0453 case HAL_GFXMMU_MSPDEINIT_CB_ID :
0454 hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
0455 break;
0456 default :
0457
0458 hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
0459
0460 status = HAL_ERROR;
0461 break;
0462 }
0463 }
0464 else if(HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
0465 {
0466 switch (CallbackID)
0467 {
0468 case HAL_GFXMMU_MSPINIT_CB_ID :
0469 hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
0470 break;
0471 case HAL_GFXMMU_MSPDEINIT_CB_ID :
0472 hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
0473 break;
0474 default :
0475
0476 hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
0477
0478 status = HAL_ERROR;
0479 break;
0480 }
0481 }
0482 else
0483 {
0484
0485 hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
0486
0487 status = HAL_ERROR;
0488 }
0489 return status;
0490 }
0491 #endif
0492
0493
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0523
0524
0525 HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,
0526 uint32_t FirstLine,
0527 uint32_t LinesNumber,
0528 uint32_t Address)
0529 {
0530 HAL_StatusTypeDef status = HAL_OK;
0531
0532
0533 assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
0534 assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
0535 assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
0536
0537
0538 if((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
0539 {
0540 status = HAL_ERROR;
0541 }
0542 else
0543 {
0544 uint32_t current_address, current_line, lutxl_address, lutxh_address;
0545
0546
0547 current_address = Address;
0548 current_line = 0U;
0549 lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
0550 lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
0551
0552
0553 while(current_line < LinesNumber)
0554 {
0555 *((uint32_t *)lutxl_address) = *((uint32_t *)current_address);
0556 current_address += 4U;
0557 *((uint32_t *)lutxh_address) = *((uint32_t *)current_address);
0558 current_address += 4U;
0559 lutxl_address += 8U;
0560 lutxh_address += 8U;
0561 current_line++;
0562 }
0563 }
0564
0565 return status;
0566 }
0567
0568
0569
0570
0571
0572
0573
0574
0575
0576
0577 HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu,
0578 uint32_t FirstLine,
0579 uint32_t LinesNumber)
0580 {
0581 HAL_StatusTypeDef status = HAL_OK;
0582
0583
0584 assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
0585 assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
0586 assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
0587
0588
0589 if((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
0590 {
0591 status = HAL_ERROR;
0592 }
0593 else
0594 {
0595 uint32_t current_line, lutxl_address, lutxh_address;
0596
0597
0598 current_line = 0U;
0599 lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
0600 lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
0601
0602
0603 while(current_line < LinesNumber)
0604 {
0605 *((uint32_t *)lutxl_address) = 0U;
0606 *((uint32_t *)lutxh_address) = 0U;
0607 lutxl_address += 8U;
0608 lutxh_address += 8U;
0609 current_line++;
0610 }
0611 }
0612
0613 return status;
0614 }
0615
0616
0617
0618
0619
0620
0621
0622 HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine)
0623 {
0624 HAL_StatusTypeDef status = HAL_OK;
0625
0626
0627 assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
0628 assert_param(IS_GFXMMU_LUT_LINE(lutLine->LineNumber));
0629 assert_param(IS_GFXMMU_LUT_LINE_STATUS(lutLine->LineStatus));
0630 assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->FirstVisibleBlock));
0631 assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->LastVisibleBlock));
0632 assert_param(IS_GFXMMU_LUT_LINE_OFFSET(lutLine->LineOffset));
0633
0634
0635 if(hgfxmmu->State != HAL_GFXMMU_STATE_READY)
0636 {
0637 status = HAL_ERROR;
0638 }
0639 else
0640 {
0641 uint32_t lutxl_address, lutxh_address;
0642
0643
0644 lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * lutLine->LineNumber]);
0645 lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * lutLine->LineNumber) + 1U]);
0646
0647
0648 if(lutLine->LineStatus == GFXMMU_LUT_LINE_ENABLE)
0649 {
0650
0651 *((uint32_t *)lutxl_address) = (lutLine->LineStatus |
0652 (lutLine->FirstVisibleBlock << GFXMMU_LUTXL_FVB_OFFSET) |
0653 (lutLine->LastVisibleBlock << GFXMMU_LUTXL_LVB_OFFSET));
0654 *((uint32_t *)lutxh_address) = (uint32_t) lutLine->LineOffset;
0655 }
0656 else
0657 {
0658
0659 *((uint32_t *)lutxl_address) = 0U;
0660 *((uint32_t *)lutxh_address) = 0U;
0661 }
0662 }
0663
0664 return status;
0665 }
0666
0667
0668
0669
0670
0671
0672
0673
0674 HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam)
0675 {
0676 HAL_StatusTypeDef status = HAL_OK;
0677
0678
0679 assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
0680 assert_param(IS_GFXMMU_CACHE_FORCE_ACTION(ForceParam));
0681
0682
0683 if(((hgfxmmu->Instance->CR & GFXMMU_CR_CE) != GFXMMU_CR_CE) || (hgfxmmu->State != HAL_GFXMMU_STATE_READY))
0684 {
0685 status = HAL_ERROR;
0686 }
0687 else
0688 {
0689
0690 hgfxmmu->Instance->CCR |= ForceParam;
0691 }
0692
0693 return status;
0694 }
0695
0696
0697
0698
0699
0700
0701
0702 HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers)
0703 {
0704 HAL_StatusTypeDef status = HAL_OK;
0705
0706
0707 assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
0708 assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf0Address));
0709 assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf1Address));
0710 assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf2Address));
0711 assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf3Address));
0712
0713
0714 if(hgfxmmu->State != HAL_GFXMMU_STATE_READY)
0715 {
0716 status = HAL_ERROR;
0717 }
0718 else
0719 {
0720
0721 hgfxmmu->Instance->B0CR = Buffers->Buf0Address;
0722 hgfxmmu->Instance->B1CR = Buffers->Buf1Address;
0723 hgfxmmu->Instance->B2CR = Buffers->Buf2Address;
0724 hgfxmmu->Instance->B3CR = Buffers->Buf3Address;
0725 }
0726
0727 return status;
0728 }
0729
0730
0731
0732
0733
0734
0735
0736 HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu,
0737 GFXMMU_CachePrefetchTypeDef *CachePrefetch)
0738 {
0739 HAL_StatusTypeDef status = HAL_OK;
0740 assert_param(IS_FUNCTIONAL_STATE(CachePrefetch->Activation));
0741
0742
0743 assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
0744
0745
0746 if(hgfxmmu->State != HAL_GFXMMU_STATE_READY)
0747 {
0748 status = HAL_ERROR;
0749 }
0750 else
0751 {
0752
0753 hgfxmmu->Instance->CR &= ~(GFXMMU_CR_CE | GFXMMU_CR_CL | GFXMMU_CR_CLB | GFXMMU_CR_FC |
0754 GFXMMU_CR_PD | GFXMMU_CR_OC | GFXMMU_CR_OB);
0755 if(CachePrefetch->Activation == ENABLE)
0756 {
0757 assert_param(IS_GFXMMU_CACHE_LOCK(CachePrefetch->CacheLock));
0758 assert_param(IS_GFXMMU_PREFETCH(CachePrefetch->Prefetch));
0759 assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(CachePrefetch->OutterBufferability));
0760 assert_param(IS_GFXMMU_OUTTER_CACHABILITY(CachePrefetch->OutterCachability));
0761 hgfxmmu->Instance->CR |= (GFXMMU_CR_CE |
0762 CachePrefetch->CacheLock |
0763 CachePrefetch->Prefetch |
0764 CachePrefetch->OutterBufferability |
0765 CachePrefetch->OutterCachability);
0766 if(CachePrefetch->CacheLock == GFXMMU_CACHE_LOCK_ENABLE)
0767 {
0768 assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(CachePrefetch->CacheLockBuffer));
0769 assert_param(IS_GFXMMU_CACHE_FORCE(CachePrefetch->CacheForce));
0770 hgfxmmu->Instance->CR |= (CachePrefetch->CacheLockBuffer |
0771 CachePrefetch->CacheForce);
0772 }
0773 }
0774 }
0775
0776 return status;
0777 }
0778
0779
0780
0781
0782
0783
0784 void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu)
0785 {
0786 uint32_t flags, interrupts, error;
0787
0788
0789 flags = hgfxmmu->Instance->SR;
0790 interrupts = (hgfxmmu->Instance->CR & GFXMMU_CR_ITS_MASK);
0791 error = (flags & interrupts);
0792
0793 if(error != 0U)
0794 {
0795
0796 hgfxmmu->Instance->FCR = error;
0797
0798
0799 hgfxmmu->ErrorCode |= error;
0800
0801
0802 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
0803 hgfxmmu->ErrorCallback(hgfxmmu);
0804 #else
0805 HAL_GFXMMU_ErrorCallback(hgfxmmu);
0806 #endif
0807 }
0808 }
0809
0810
0811
0812
0813
0814
0815 __weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu)
0816 {
0817
0818 UNUSED(hgfxmmu);
0819
0820
0821
0822
0823 }
0824
0825
0826
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0828
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0835
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0839
0840
0841
0842
0843
0844
0845
0846
0847
0848
0849 HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu)
0850 {
0851
0852 return hgfxmmu->State;
0853 }
0854
0855
0856
0857
0858
0859
0860 uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu)
0861 {
0862 uint32_t error_code;
0863
0864
0865 __disable_irq();
0866
0867
0868 error_code = hgfxmmu->ErrorCode;
0869 hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
0870
0871
0872 __enable_irq();
0873
0874
0875 return error_code;
0876 }
0877
0878
0879
0880
0881
0882
0883
0884
0885
0886
0887
0888
0889
0890
0891
0892 #endif
0893 #endif
0894
0895
0896
0897