stm32h7/hal/stm32h7xx_hal_eth_ex.c

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_eth_ex.c
0004   * @author  MCD Application Team
0005   * @brief   ETH HAL Extended module driver.
0006   *
0007   ******************************************************************************
0008   * @attention
0009   *
0010   * Copyright (c) 2017 STMicroelectronics.
0011   * All rights reserved.
0012   *
0013   * This software is licensed under terms that can be found in the LICENSE file
0014   * in the root directory of this software component.
0015   * If no LICENSE file comes with this software, it is provided AS-IS.
0016   *
0017   ******************************************************************************
0018   */
0019
0020 /* Includes ------------------------------------------------------------------*/
0021 #include "stm32h7xx_hal.h"
0022
0023 /** @addtogroup STM32H7xx_HAL_Driver
0024   * @{
0025   */
0026
0027 #ifdef HAL_ETH_MODULE_ENABLED
0028
0029 #if defined(ETH)
0030
0031 /** @defgroup ETHEx ETHEx
0032   * @ingroup RTEMSBSPsARMSTM32H7
0033   * @brief ETH HAL Extended module driver
0034   * @{
0035   */
0036
0037 /* Private typedef -----------------------------------------------------------*/
0038 /* Private define ------------------------------------------------------------*/
0039 /** @defgroup ETHEx_Private_Constants ETHEx Private Constants
0040   * @ingroup RTEMSBSPsARMSTM32H7
0041   * @{
0042   */
0043 #define ETH_MACL4CR_MASK     (ETH_MACL3L4CR_L4PEN | ETH_MACL3L4CR_L4SPM | \
0044                               ETH_MACL3L4CR_L4SPIM | ETH_MACL3L4CR_L4DPM | \
0045                               ETH_MACL3L4CR_L4DPIM)
0046
0047 #define ETH_MACL3CR_MASK     (ETH_MACL3L4CR_L3PEN | ETH_MACL3L4CR_L3SAM | \
0048                               ETH_MACL3L4CR_L3SAIM | ETH_MACL3L4CR_L3DAM | \
0049                               ETH_MACL3L4CR_L3DAIM | ETH_MACL3L4CR_L3HSBM | \
0050                               ETH_MACL3L4CR_L3HDBM)
0051
0052 #define ETH_MACRXVLAN_MASK (ETH_MACVTR_EIVLRXS | ETH_MACVTR_EIVLS | \
0053                             ETH_MACVTR_ERIVLT | ETH_MACVTR_EDVLP | \
0054                             ETH_MACVTR_VTHM | ETH_MACVTR_EVLRXS | \
0055                             ETH_MACVTR_EVLS | ETH_MACVTR_DOVLTC | \
0056                             ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL | \
0057                             ETH_MACVTR_VTIM | ETH_MACVTR_ETV)
0058
0059 #define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
0060                             ETH_MACVIR_VLP | ETH_MACVIR_VLC)
0061
0062 #define ETH_MAC_L4_SRSP_MASK          0x0000FFFFU
0063 #define ETH_MAC_L4_DSTP_MASK          0xFFFF0000U
0064 /**
0065   * @}
0066   */
0067
0068 /* Private macros ------------------------------------------------------------*/
0069 /* Private function prototypes -----------------------------------------------*/
0070 /* Exported functions ---------------------------------------------------------*/
0071 /** @defgroup ETHEx_Exported_Functions ETH Extended Exported Functions
0072   * @ingroup RTEMSBSPsARMSTM32H7
0073   * @{
0074   */
0075
0076 /** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions
0077   * @ingroup RTEMSBSPsARMSTM32H7
0078   * @brief    Extended features functions
0079   *
0080 @verbatim
0081  ===============================================================================
0082                       ##### Extended features functions #####
0083  ===============================================================================
0084     [..] This section provides functions allowing to:
0085       (+) Configure ARP offload module
0086       (+) Configure L3 and L4 filters
0087       (+) Configure Extended VLAN features
0088       (+) Configure Energy Efficient Ethernet module
0089
0090 @endverbatim
0091   * @{
0092   */
0093
0094 /**
0095   * @brief  Enables ARP Offload.
0096   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0097   *         the configuration information for ETHERNET module
0098   * @retval None
0099   */
0100
0101 void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
0102 {
0103   SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
0104 }
0105
0106 /**
0107   * @brief  Disables ARP Offload.
0108   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0109   *         the configuration information for ETHERNET module
0110   * @retval None
0111   */
0112 void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth)
0113 {
0114   CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
0115 }
0116
0117 /**
0118   * @brief  Set the ARP Match IP address
0119   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0120   *         the configuration information for ETHERNET module
0121   * @param  IpAddress: IP Address to be matched for incoming ARP requests
0122   * @retval None
0123   */
0124 void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
0125 {
0126   WRITE_REG(heth->Instance->MACARPAR, IpAddress);
0127 }
0128
0129 /**
0130   * @brief  Configures the L4 Filter, this function allow to:
0131   *         set the layer 4 protocol to be matched (TCP or UDP)
0132   *         enable/disable L4 source/destination port perfect/inverse match.
0133   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0134   *         the configuration information for ETHERNET module
0135   * @param  Filter: L4 filter to configured, this parameter must be one of the following
0136   *           ETH_L4_FILTER_0
0137   *           ETH_L4_FILTER_1
0138   * @param  pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
0139   *         that contains L4 filter configuration.
0140   * @retval HAL status
0141   */
0142 HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
0143                                               const ETH_L4FilterConfigTypeDef *pL4FilterConfig)
0144 {
0145   if (pL4FilterConfig == NULL)
0146   {
0147     return HAL_ERROR;
0148   }
0149
0150   if (Filter == ETH_L4_FILTER_0)
0151   {
0152     /* Write configuration to MACL3L4C0R register */
0153     MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
0154                                                               pL4FilterConfig->SrcPortFilterMatch |
0155                                                               pL4FilterConfig->DestPortFilterMatch));
0156
0157     /* Write configuration to MACL4A0R register */
0158     WRITE_REG(heth->Instance->MACL4A0R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
0159
0160   }
0161   else /* Filter == ETH_L4_FILTER_1 */
0162   {
0163     /* Write configuration to MACL3L4C1R register */
0164     MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
0165                                                               pL4FilterConfig->SrcPortFilterMatch |
0166                                                               pL4FilterConfig->DestPortFilterMatch));
0167
0168     /* Write configuration to MACL4A1R register */
0169     WRITE_REG(heth->Instance->MACL4A1R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
0170   }
0171
0172   /* Enable L4 filter */
0173   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
0174
0175   return HAL_OK;
0176 }
0177
0178 /**
0179   * @brief  Configures the L4 Filter, this function allow to:
0180   *         set the layer 4 protocol to be matched (TCP or UDP)
0181   *         enable/disable L4 source/destination port perfect/inverse match.
0182   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0183   *         the configuration information for ETHERNET module
0184   * @param  Filter: L4 filter to configured, this parameter must be one of the following
0185   *           ETH_L4_FILTER_0
0186   *           ETH_L4_FILTER_1
0187   * @param  pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
0188   *         that contains L4 filter configuration.
0189   * @retval HAL status
0190   */
0191 HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
0192                                               ETH_L4FilterConfigTypeDef *pL4FilterConfig)
0193 {
0194   if (pL4FilterConfig == NULL)
0195   {
0196     return HAL_ERROR;
0197   }
0198
0199   if (Filter == ETH_L4_FILTER_0)
0200   {
0201     /* Get configuration from MACL3L4C0R register */
0202     pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C0R, ETH_MACL3L4CR_L4PEN);
0203     pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
0204                                                     (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
0205     pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
0206                                                    (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
0207
0208     /* Get configuration from MACL4A0R register */
0209     pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_DSTP_MASK) >> 16);
0210     pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_SRSP_MASK);
0211   }
0212   else /* Filter == ETH_L4_FILTER_1 */
0213   {
0214     /* Get configuration from MACL3L4C1R register */
0215     pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C1R, ETH_MACL3L4CR_L4PEN);
0216     pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
0217                                                     (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
0218     pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
0219                                                    (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
0220
0221     /* Get configuration from MACL4A1R register */
0222     pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_DSTP_MASK) >> 16);
0223     pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_SRSP_MASK);
0224   }
0225
0226   return HAL_OK;
0227 }
0228
0229 /**
0230   * @brief  Configures the L3 Filter, this function allow to:
0231   *         set the layer 3 protocol to be matched (IPv4 or IPv6)
0232   *         enable/disable L3 source/destination port perfect/inverse match.
0233   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0234   *         the configuration information for ETHERNET module
0235   * @param  Filter: L3 filter to configured, this parameter must be one of the following
0236   *           ETH_L3_FILTER_0
0237   *           ETH_L3_FILTER_1
0238   * @param  pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
0239   *         that contains L3 filter configuration.
0240   * @retval HAL status
0241   */
0242 HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
0243                                               const ETH_L3FilterConfigTypeDef *pL3FilterConfig)
0244 {
0245   if (pL3FilterConfig == NULL)
0246   {
0247     return HAL_ERROR;
0248   }
0249
0250   if (Filter == ETH_L3_FILTER_0)
0251   {
0252     /* Write configuration to MACL3L4C0R register */
0253     MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
0254                                                               pL3FilterConfig->SrcAddrFilterMatch |
0255                                                               pL3FilterConfig->DestAddrFilterMatch |
0256                                                               (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
0257                                                               (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
0258   }
0259   else  /* Filter == ETH_L3_FILTER_1 */
0260   {
0261     /* Write configuration to MACL3L4C1R register */
0262     MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
0263                                                               pL3FilterConfig->SrcAddrFilterMatch |
0264                                                               pL3FilterConfig->DestAddrFilterMatch |
0265                                                               (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
0266                                                               (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
0267   }
0268
0269   if (Filter == ETH_L3_FILTER_0)
0270   {
0271     /* Check if IPv6 protocol is selected */
0272     if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
0273     {
0274       /* Set the IPv6 address match */
0275       /* Set Bits[31:0] of 128-bit IP addr */
0276       WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip6Addr[0]);
0277       /* Set Bits[63:32] of 128-bit IP addr */
0278       WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip6Addr[1]);
0279       /* update Bits[95:64] of 128-bit IP addr */
0280       WRITE_REG(heth->Instance->MACL3A2R0R, pL3FilterConfig->Ip6Addr[2]);
0281       /* update Bits[127:96] of 128-bit IP addr */
0282       WRITE_REG(heth->Instance->MACL3A3R0R, pL3FilterConfig->Ip6Addr[3]);
0283     }
0284     else /* IPv4 protocol is selected */
0285     {
0286       /* Set the IPv4 source address match */
0287       WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip4SrcAddr);
0288       /* Set the IPv4 destination address match */
0289       WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip4DestAddr);
0290     }
0291   }
0292   else  /* Filter == ETH_L3_FILTER_1 */
0293   {
0294     /* Check if IPv6 protocol is selected */
0295     if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
0296     {
0297       /* Set the IPv6 address match */
0298       /* Set Bits[31:0] of 128-bit IP addr */
0299       WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip6Addr[0]);
0300       /* Set Bits[63:32] of 128-bit IP addr */
0301       WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[1]);
0302       /* update Bits[95:64] of 128-bit IP addr */
0303       WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[2]);
0304       /* update Bits[127:96] of 128-bit IP addr */
0305       WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[3]);
0306     }
0307     else /* IPv4 protocol is selected */
0308     {
0309       /* Set the IPv4 source address match */
0310       WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4SrcAddr);
0311       /* Set the IPv4 destination address match */
0312       WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4DestAddr);
0313
0314     }
0315   }
0316
0317   /* Enable L3 filter */
0318   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
0319
0320   return HAL_OK;
0321 }
0322
0323 /**
0324   * @brief  Configures the L3 Filter, this function allow to:
0325   *         set the layer 3 protocol to be matched (IPv4 or IPv6)
0326   *         enable/disable L3 source/destination port perfect/inverse match.
0327   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0328   *         the configuration information for ETHERNET module
0329   * @param  Filter: L3 filter to configured, this parameter must be one of the following
0330   *           ETH_L3_FILTER_0
0331   *           ETH_L3_FILTER_1
0332   * @param  pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
0333   *         that will contain the L3 filter configuration.
0334   * @retval HAL status
0335   */
0336 HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
0337                                               ETH_L3FilterConfigTypeDef *pL3FilterConfig)
0338 {
0339   if (pL3FilterConfig == NULL)
0340   {
0341     return HAL_ERROR;
0342   }
0343   pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
0344                                        ETH_MACL3L4CR_L3PEN);
0345   pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
0346                                                  (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
0347   pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
0348                                                   (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
0349   pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
0350                                                       ETH_MACL3L4CR_L3HSBM) >> 6);
0351   pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
0352                                                        ETH_MACL3L4CR_L3HDBM) >> 11);
0353
0354   if (Filter == ETH_L3_FILTER_0)
0355   {
0356     if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
0357     {
0358       WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R0R);
0359       WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R0R);
0360       WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R0R);
0361       WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R0R);
0362     }
0363     else
0364     {
0365       WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R0R);
0366       WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R0R);
0367     }
0368   }
0369   else /* ETH_L3_FILTER_1 */
0370   {
0371     if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
0372     {
0373       WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R1R);
0374       WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R1R);
0375       WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R1R);
0376       WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R1R);
0377     }
0378     else
0379     {
0380       WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R1R);
0381       WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R1R);
0382     }
0383   }
0384
0385   return HAL_OK;
0386 }
0387
0388 /**
0389   * @brief  Enables L3 and L4 filtering process.
0390   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0391   *         the configuration information for ETHERNET module
0392   * @retval None.
0393   */
0394 void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth)
0395 {
0396   /* Enable L3/L4 filter */
0397   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
0398 }
0399
0400 /**
0401   * @brief  Disables L3 and L4 filtering process.
0402   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0403   *         the configuration information for ETHERNET module
0404   * @retval None.
0405   */
0406 void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
0407 {
0408   /* Disable L3/L4 filter */
0409   CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
0410 }
0411
0412 /**
0413   * @brief  Get the VLAN Configuration for Receive Packets.
0414   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0415   *         the configuration information for ETHERNET module
0416   * @param  pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
0417   *         that will contain the VLAN filter configuration.
0418   * @retval HAL status
0419   */
0420 HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
0421 {
0422   if (pVlanConfig == NULL)
0423   {
0424     return HAL_ERROR;
0425   }
0426
0427   pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR,
0428                                                  ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
0429   pVlanConfig->StripInnerVLANTag  = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
0430   pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR,
0431                                          ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
0432   pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR,
0433                                                  ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
0434   pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR,
0435                                                   ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
0436   pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR,
0437                                             ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
0438   pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
0439   pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR,
0440                                         (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
0441   pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U)
0442                                      ? DISABLE : ENABLE;
0443
0444   return HAL_OK;
0445 }
0446
0447 /**
0448   * @brief  Set the VLAN Configuration for Receive Packets.
0449   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0450   *         the configuration information for ETHERNET module
0451   * @param  pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
0452   *         that contains VLAN filter configuration.
0453   * @retval HAL status
0454   */
0455 HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
0456 {
0457   if (pVlanConfig == NULL)
0458   {
0459     return HAL_ERROR;
0460   }
0461
0462   /* Write config to MACVTR */
0463   MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) |
0464                                                           pVlanConfig->StripInnerVLANTag |
0465                                                           ((uint32_t)pVlanConfig->InnerVLANTag << 27) |
0466                                                           ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
0467                                                           ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
0468                                                           ((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
0469                                                           pVlanConfig->StripVLANTag |
0470                                                           pVlanConfig->VLANTypeCheck |
0471                                                           ((uint32_t)pVlanConfig->VLANTagInverceMatch << 17)));
0472
0473   return HAL_OK;
0474 }
0475
0476 /**
0477   * @brief  Set the VLAN Hash Table
0478   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0479   *         the configuration information for ETHERNET module
0480   * @param  VLANHashTable: VLAN hash table 16 bit value
0481   * @retval None
0482   */
0483 void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
0484 {
0485   MODIFY_REG(heth->Instance->MACVHTR, ETH_MACVHTR_VLHT, VLANHashTable);
0486 }
0487
0488 /**
0489   * @brief  Get the VLAN Configuration for Transmit Packets.
0490   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0491   *         the configuration information for ETHERNET module
0492   * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
0493   *                 ETH_OUTER_TX_VLANTAG
0494   *                 ETH_INNER_TX_VLANTAG
0495   * @param  pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
0496   *         that will contain the Tx VLAN filter configuration.
0497   * @retval HAL Status.
0498   */
0499 HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
0500                                             ETH_TxVLANConfigTypeDef *pVlanConfig)
0501 {
0502   if (pVlanConfig == NULL)
0503   {
0504     return HAL_ERROR;
0505   }
0506
0507   if (VLANTag == ETH_INNER_TX_VLANTAG)
0508   {
0509     pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
0510     pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
0511     pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACIVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
0512   }
0513   else
0514   {
0515     pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
0516     pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
0517     pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
0518   }
0519
0520   return HAL_OK;;
0521 }
0522
0523 /**
0524   * @brief  Set the VLAN Configuration for Transmit Packets.
0525   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0526   *         the configuration information for ETHERNET module
0527   * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
0528   *                 ETH_OUTER_TX_VLANTAG
0529   *                 ETH_INNER_TX_VLANTAG
0530   * @param  pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
0531   *         that contains Tx VLAN filter configuration.
0532   * @retval HAL Status
0533   */
0534 HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
0535                                             const ETH_TxVLANConfigTypeDef *pVlanConfig)
0536 {
0537   if (VLANTag == ETH_INNER_TX_VLANTAG)
0538   {
0539     MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
0540                                                              ((uint32_t)pVlanConfig->SVLANType << 19) |
0541                                                              pVlanConfig->VLANTagControl));
0542     /* Enable Double VLAN processing */
0543     SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
0544   }
0545   else
0546   {
0547     MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
0548                                                             ((uint32_t)pVlanConfig->SVLANType << 19) |
0549                                                             pVlanConfig->VLANTagControl));
0550   }
0551
0552   return HAL_OK;
0553 }
0554
0555 /**
0556   * @brief  Set the VLAN Tag Identifier for Transmit Packets.
0557   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0558   *         the configuration information for ETHERNET module
0559   * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
0560   *                 ETH_OUTER_TX_VLANTAG
0561   *                 ETH_INNER_TX_VLANTAG
0562   * @param  VLANIdentifier: VLAN Identifier 16 bit value
0563   * @retval None
0564   */
0565 void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier)
0566 {
0567   if (VLANTag == ETH_INNER_TX_VLANTAG)
0568   {
0569     MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier);
0570   }
0571   else
0572   {
0573     MODIFY_REG(heth->Instance->MACVIR, ETH_MACVIR_VLT, VLANIdentifier);
0574   }
0575 }
0576
0577 /**
0578   * @brief  Enables the VLAN Tag Filtering process.
0579   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0580   *         the configuration information for ETHERNET module
0581   * @retval None.
0582   */
0583 void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth)
0584 {
0585   /* Enable VLAN processing */
0586   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
0587 }
0588
0589 /**
0590   * @brief  Disables the VLAN Tag Filtering process.
0591   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0592   *         the configuration information for ETHERNET module
0593   * @retval None.
0594   */
0595 void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth)
0596 {
0597   /* Disable VLAN processing */
0598   CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
0599 }
0600
0601 /**
0602   * @brief  Enters the Low Power Idle (LPI) mode
0603   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0604   *         the configuration information for ETHERNET module
0605   * @param  TxAutomate: Enable/Disable automate enter/exit LPI mode.
0606   * @param  TxClockStop: Enable/Disable Tx clock stop in LPI mode.
0607   * @retval None
0608   */
0609 void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
0610 {
0611   /* Enable LPI Interrupts */
0612   __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE);
0613
0614   /* Write to LPI Control register: Enter low power mode */
0615   MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE),
0616              (((uint32_t)TxAutomate << 19) |
0617               ((uint32_t)TxClockStop << 21) |
0618               ETH_MACLCSR_LPIEN));
0619 }
0620
0621 /**
0622   * @brief  Exits the Low Power Idle (LPI) mode.
0623   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0624   *         the configuration information for ETHERNET module
0625   * @retval None
0626   */
0627 void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
0628 {
0629   /* Clear the LPI Config and exit low power mode */
0630   CLEAR_BIT(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE));
0631
0632   /* Enable LPI Interrupts */
0633   __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
0634 }
0635
0636 /**
0637   * @brief  Returns the ETH MAC LPI event
0638   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0639   *         the configuration information for ETHERNET module
0640   * @retval ETH MAC WakeUp event
0641   */
0642 uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth)
0643 {
0644   return heth->MACLPIEvent;
0645 }
0646
0647 /**
0648   * @}
0649   */
0650
0651 /**
0652   * @}
0653   */
0654
0655 /**
0656   * @}
0657   */
0658
0659 #endif /* ETH */
0660
0661 #endif /* HAL_ETH_MODULE_ENABLED */
0662 /**
0663   * @}
0664   */