File indexing completed on 2025-05-11 08:23:07
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0044 #include "stm32h7xx_hal.h"
0045
0046
0047
0048
0049
0050 #ifdef HAL_DTS_MODULE_ENABLED
0051
0052 #if defined(DTS)
0053
0054
0055
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0057
0058
0059
0060
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0070 #define DTS_DELAY_STARTUP (1UL)
0071
0072
0073
0074
0075
0076
0077
0078 #define TS_TIMEOUT_MS (5UL)
0079
0080
0081
0082
0083 #define DTS_FACTORY_TEMPERATURE1 (30UL)
0084 #define DTS_FACTORY_TEMPERATURE2 (130UL)
0085
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0119
0120 HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts)
0121 {
0122
0123 if (hdts == NULL)
0124 {
0125 return HAL_ERROR;
0126 }
0127
0128
0129 assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
0130 assert_param(IS_DTS_QUICKMEAS(hdts->Init.QuickMeasure));
0131 assert_param(IS_DTS_REFCLK(hdts->Init.RefClock));
0132 assert_param(IS_DTS_TRIGGERINPUT(hdts->Init.TriggerInput));
0133 assert_param(IS_DTS_SAMPLINGTIME(hdts->Init.SamplingTime));
0134 assert_param(IS_DTS_THRESHOLD(hdts->Init.HighThreshold));
0135 assert_param(IS_DTS_THRESHOLD(hdts->Init.LowThreshold));
0136
0137 if (hdts->State == HAL_DTS_STATE_RESET)
0138 {
0139 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
0140
0141 hdts->EndCallback = HAL_DTS_EndCallback;
0142 hdts->LowCallback = HAL_DTS_LowCallback;
0143 hdts->HighCallback = HAL_DTS_HighCallback;
0144 hdts->AsyncEndCallback = HAL_DTS_AsyncEndCallback;
0145 hdts->AsyncLowCallback = HAL_DTS_AsyncLowCallback;
0146 hdts->AsyncHighCallback = HAL_DTS_AsyncHighCallback;
0147
0148 if (hdts->MspInitCallback == NULL)
0149 {
0150 hdts->MspInitCallback = HAL_DTS_MspInit;
0151 }
0152
0153
0154 hdts->MspInitCallback(hdts);
0155 #else
0156
0157 HAL_DTS_MspInit(hdts);
0158 #endif
0159 }
0160
0161
0162 hdts->State = HAL_DTS_STATE_BUSY;
0163
0164
0165 if (hdts->Instance->RAMPVALR == 0UL)
0166 {
0167 return HAL_ERROR;
0168 }
0169
0170
0171 if (hdts->Instance->T0VALR1 == 0UL)
0172 {
0173 return HAL_ERROR;
0174 }
0175
0176
0177 if (hdts->Init.QuickMeasure == DTS_QUICKMEAS_DISABLE)
0178 {
0179
0180 if (hdts->Init.RefClock == DTS_REFCLKSEL_PCLK)
0181 {
0182 assert_param(IS_DTS_DIVIDER_RATIO_NUMBER(hdts->Init.Divider));
0183 }
0184
0185 CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_Q_MEAS_OPT);
0186 }
0187 else
0188 {
0189
0190
0191 if (hdts->Init.RefClock != DTS_REFCLKSEL_LSE)
0192 {
0193 return HAL_ERROR;
0194 }
0195
0196
0197 SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_Q_MEAS_OPT);
0198 }
0199
0200
0201 if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE)
0202 {
0203 SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_REFCLK_SEL);
0204 }
0205 else
0206 {
0207 CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_REFCLK_SEL);
0208 }
0209
0210 MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_HSREF_CLK_DIV, (hdts->Init.Divider << DTS_CFGR1_HSREF_CLK_DIV_Pos));
0211 MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_TS1_SMP_TIME, hdts->Init.SamplingTime);
0212 MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_TS1_INTRIG_SEL, hdts->Init.TriggerInput);
0213 MODIFY_REG(hdts->Instance->ITR1, DTS_ITR1_TS1_HITTHD, (hdts->Init.HighThreshold << DTS_ITR1_TS1_HITTHD_Pos));
0214 MODIFY_REG(hdts->Instance->ITR1, DTS_ITR1_TS1_LITTHD, hdts->Init.LowThreshold);
0215
0216
0217 hdts->State = HAL_DTS_STATE_READY;
0218
0219 return HAL_OK;
0220 }
0221
0222
0223
0224
0225
0226
0227
0228
0229 HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts)
0230 {
0231
0232 if (hdts == NULL)
0233 {
0234 return HAL_ERROR;
0235 }
0236
0237
0238 assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
0239
0240
0241 CLEAR_REG(hdts->Instance->CFGR1);
0242
0243 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
0244 if (hdts->MspDeInitCallback == NULL)
0245 {
0246 hdts->MspDeInitCallback = HAL_DTS_MspDeInit;
0247 }
0248
0249
0250 hdts->MspDeInitCallback(hdts);
0251 #else
0252
0253 HAL_DTS_MspDeInit(hdts);
0254 #endif
0255
0256 hdts->State = HAL_DTS_STATE_RESET;
0257
0258 return HAL_OK;
0259 }
0260
0261
0262
0263
0264
0265
0266 __weak void HAL_DTS_MspInit(DTS_HandleTypeDef *hdts)
0267 {
0268
0269 UNUSED(hdts);
0270
0271
0272
0273
0274 }
0275
0276
0277
0278
0279
0280
0281 __weak void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts)
0282 {
0283
0284 UNUSED(hdts);
0285
0286
0287
0288
0289 }
0290
0291 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
0292
0293
0294
0295
0296
0297
0298
0299
0300
0301
0302
0303
0304
0305
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0307
0308 HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef *hdts,
0309 HAL_DTS_CallbackIDTypeDef CallbackID,
0310 pDTS_CallbackTypeDef pCallback)
0311 {
0312 HAL_StatusTypeDef status = HAL_OK;
0313
0314
0315 if (pCallback == NULL)
0316 {
0317
0318 status = HAL_ERROR;
0319 }
0320 else
0321 {
0322 if (hdts->State == HAL_DTS_STATE_READY)
0323 {
0324 switch (CallbackID)
0325 {
0326 case HAL_DTS_MEAS_COMPLETE_CB_ID :
0327 hdts->EndCallback = pCallback;
0328 break;
0329 case HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID :
0330 hdts->AsyncEndCallback = pCallback;
0331 break;
0332 case HAL_DTS_LOW_THRESHOLD_CB_ID :
0333 hdts->LowCallback = pCallback;
0334 break;
0335 case HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID :
0336 hdts->AsyncLowCallback = pCallback;
0337 break;
0338 case HAL_DTS_HIGH_THRESHOLD_CB_ID :
0339 hdts->HighCallback = pCallback;
0340 break;
0341 case HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID :
0342 hdts->AsyncHighCallback = pCallback;
0343 break;
0344 case HAL_DTS_MSPINIT_CB_ID :
0345 hdts->MspInitCallback = pCallback;
0346 break;
0347 case HAL_DTS_MSPDEINIT_CB_ID :
0348 hdts->MspDeInitCallback = pCallback;
0349 break;
0350 default :
0351
0352 status = HAL_ERROR;
0353 break;
0354 }
0355 }
0356 else if (hdts->State == HAL_DTS_STATE_RESET)
0357 {
0358 switch (CallbackID)
0359 {
0360 case HAL_DTS_MSPINIT_CB_ID :
0361 hdts->MspInitCallback = pCallback;
0362 break;
0363 case HAL_DTS_MSPDEINIT_CB_ID :
0364 hdts->MspDeInitCallback = pCallback;
0365 break;
0366 default :
0367
0368 status = HAL_ERROR;
0369 break;
0370 }
0371 }
0372 else
0373 {
0374
0375 status = HAL_ERROR;
0376 }
0377 }
0378
0379
0380 return status;
0381 }
0382
0383
0384
0385
0386
0387
0388
0389
0390
0391
0392
0393
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0397
0398
0399 HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef *hdts,
0400 HAL_DTS_CallbackIDTypeDef CallbackID)
0401 {
0402 HAL_StatusTypeDef status = HAL_OK;
0403
0404 if (hdts->State == HAL_DTS_STATE_READY)
0405 {
0406 switch (CallbackID)
0407 {
0408 case HAL_DTS_MEAS_COMPLETE_CB_ID :
0409 hdts->EndCallback = HAL_DTS_EndCallback;
0410 break;
0411 case HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID :
0412 hdts->AsyncEndCallback = HAL_DTS_AsyncEndCallback;
0413 break;
0414 case HAL_DTS_LOW_THRESHOLD_CB_ID :
0415 hdts->LowCallback = HAL_DTS_LowCallback;
0416 break;
0417 case HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID :
0418 hdts->AsyncLowCallback = HAL_DTS_AsyncLowCallback;
0419 break;
0420 case HAL_DTS_HIGH_THRESHOLD_CB_ID :
0421 hdts->HighCallback = HAL_DTS_HighCallback;
0422 break;
0423 case HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID :
0424 hdts->AsyncHighCallback = HAL_DTS_AsyncHighCallback;
0425 break;
0426 case HAL_DTS_MSPINIT_CB_ID :
0427 hdts->MspInitCallback = HAL_DTS_MspInit;
0428 break;
0429 case HAL_DTS_MSPDEINIT_CB_ID :
0430 hdts->MspDeInitCallback = HAL_DTS_MspDeInit;
0431 break;
0432 default :
0433
0434 status = HAL_ERROR;
0435 break;
0436 }
0437 }
0438 else if (hdts->State == HAL_DTS_STATE_RESET)
0439 {
0440 switch (CallbackID)
0441 {
0442 case HAL_DTS_MSPINIT_CB_ID :
0443 hdts->MspInitCallback = HAL_DTS_MspInit;
0444 break;
0445 case HAL_DTS_MSPDEINIT_CB_ID :
0446 hdts->MspDeInitCallback = HAL_DTS_MspDeInit;
0447 break;
0448 default :
0449
0450 status = HAL_ERROR;
0451 break;
0452 }
0453 }
0454 else
0455 {
0456
0457 status = HAL_ERROR;
0458 }
0459
0460
0461 return status;
0462 }
0463 #endif
0464
0465
0466
0467
0468
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0471
0472
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0490
0491
0492 HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts)
0493 {
0494 uint32_t Ref_Time;
0495
0496
0497 if (hdts == NULL)
0498 {
0499 return HAL_ERROR;
0500 }
0501
0502 if (hdts->State == HAL_DTS_STATE_READY)
0503 {
0504 hdts->State = HAL_DTS_STATE_BUSY;
0505
0506
0507 __HAL_DTS_ENABLE(hdts);
0508
0509
0510 Ref_Time = HAL_GetTick();
0511
0512
0513 while (__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_RDY) == RESET)
0514 {
0515 if ((HAL_GetTick() - Ref_Time) > DTS_DELAY_STARTUP)
0516 {
0517 return HAL_TIMEOUT;
0518 }
0519 }
0520
0521 if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
0522 {
0523
0524 SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
0525
0526
0527 HAL_Delay(TS_TIMEOUT_MS);
0528 }
0529
0530 hdts->State = HAL_DTS_STATE_READY;
0531 }
0532 else
0533 {
0534 return HAL_BUSY;
0535 }
0536
0537 return HAL_OK;
0538 }
0539
0540
0541
0542
0543
0544
0545 HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts)
0546 {
0547
0548 if (hdts == NULL)
0549 {
0550 return HAL_ERROR;
0551 }
0552
0553 if (hdts->State == HAL_DTS_STATE_READY)
0554 {
0555 hdts->State = HAL_DTS_STATE_BUSY;
0556
0557 if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
0558 {
0559 CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
0560 }
0561
0562
0563 __HAL_DTS_DISABLE(hdts);
0564
0565 hdts->State = HAL_DTS_STATE_READY;
0566 }
0567 else
0568 {
0569 return HAL_BUSY;
0570 }
0571
0572 return HAL_OK;
0573 }
0574
0575
0576
0577
0578
0579
0580 HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts)
0581 {
0582 uint32_t Ref_Time;
0583
0584
0585 if (hdts == NULL)
0586 {
0587 return HAL_ERROR;
0588 }
0589
0590 if (hdts->State == HAL_DTS_STATE_READY)
0591 {
0592 hdts->State = HAL_DTS_STATE_BUSY;
0593
0594
0595 if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE)
0596 {
0597 __HAL_DTS_ENABLE_IT(hdts, DTS_IT_TS1_AITE | DTS_IT_TS1_AITL | DTS_IT_TS1_AITH);
0598 }
0599 else
0600 {
0601
0602 __HAL_DTS_ENABLE_IT(hdts, DTS_IT_TS1_ITE | DTS_IT_TS1_ITL | DTS_IT_TS1_ITH);
0603 }
0604
0605
0606 __HAL_DTS_ENABLE(hdts);
0607
0608
0609 Ref_Time = HAL_GetTick();
0610
0611
0612 while (__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_RDY) == RESET)
0613 {
0614 if ((HAL_GetTick() - Ref_Time) > DTS_DELAY_STARTUP)
0615 {
0616 return HAL_TIMEOUT;
0617 }
0618 }
0619
0620 if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
0621 {
0622
0623 SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
0624
0625
0626 HAL_Delay(TS_TIMEOUT_MS);
0627 }
0628
0629 hdts->State = HAL_DTS_STATE_READY;
0630 }
0631 else
0632 {
0633 return HAL_BUSY;
0634 }
0635
0636 return HAL_OK;
0637 }
0638
0639
0640
0641
0642
0643
0644 HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts)
0645 {
0646
0647 if (hdts == NULL)
0648 {
0649 return HAL_ERROR;
0650 }
0651
0652 if (hdts->State == HAL_DTS_STATE_READY)
0653 {
0654 hdts->State = HAL_DTS_STATE_BUSY;
0655
0656
0657 if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE)
0658 {
0659 __HAL_DTS_DISABLE_IT(hdts, DTS_IT_TS1_AITE | DTS_IT_TS1_AITL | DTS_IT_TS1_AITH);
0660 }
0661 else
0662 {
0663
0664 __HAL_DTS_DISABLE_IT(hdts, DTS_IT_TS1_ITE | DTS_IT_TS1_ITL | DTS_IT_TS1_ITH);
0665 }
0666
0667 if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
0668 {
0669 CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
0670 }
0671
0672
0673 __HAL_DTS_DISABLE(hdts);
0674
0675 hdts->State = HAL_DTS_STATE_READY;
0676 }
0677 else
0678 {
0679 return HAL_BUSY;
0680 }
0681
0682 return HAL_OK;
0683 }
0684
0685
0686
0687
0688
0689
0690
0691
0692 HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Temperature)
0693 {
0694 uint32_t freq_meas;
0695 uint32_t samples;
0696 uint32_t t0_temp;
0697 uint32_t t0_freq;
0698 uint32_t ramp_coeff;
0699
0700 if (hdts->State == HAL_DTS_STATE_READY)
0701 {
0702 hdts->State = HAL_DTS_STATE_BUSY;
0703
0704
0705 samples = (hdts->Instance->DR & DTS_DR_TS1_MFREQ);
0706
0707 if ((hdts->Init.SamplingTime == 0UL) || (samples == 0UL))
0708 {
0709 hdts->State = HAL_DTS_STATE_READY;
0710 return HAL_ERROR;
0711 }
0712
0713 if ((hdts->Init.RefClock) == DTS_REFCLKSEL_LSE)
0714 {
0715 freq_meas = (LSE_VALUE * samples) / (hdts->Init.SamplingTime >> DTS_CFGR1_TS1_SMP_TIME_Pos);
0716 }
0717 else
0718 {
0719 freq_meas = (HAL_RCCEx_GetD3PCLK1Freq() * (hdts->Init.SamplingTime >> DTS_CFGR1_TS1_SMP_TIME_Pos)) / samples;
0720 }
0721
0722
0723 t0_temp = hdts->Instance->T0VALR1 >> DTS_T0VALR1_TS1_T0_Pos;
0724
0725 if (t0_temp == 0UL)
0726 {
0727 t0_temp = DTS_FACTORY_TEMPERATURE1;
0728 }
0729 else if (t0_temp == 1UL)
0730 {
0731 t0_temp = DTS_FACTORY_TEMPERATURE2;
0732 }
0733 else
0734 {
0735 hdts->State = HAL_DTS_STATE_READY;
0736 return HAL_ERROR;
0737 }
0738
0739 t0_freq = (hdts->Instance->T0VALR1 & DTS_T0VALR1_TS1_FMT0) * 100UL;
0740
0741 ramp_coeff = hdts->Instance->RAMPVALR & DTS_RAMPVALR_TS1_RAMP_COEFF;
0742
0743 if (ramp_coeff == 0UL)
0744 {
0745 hdts->State = HAL_DTS_STATE_READY;
0746 return HAL_ERROR;
0747 }
0748
0749
0750 *Temperature = (int32_t)t0_temp + (((int32_t)freq_meas - (int32_t)t0_freq) / (int32_t)ramp_coeff);
0751
0752 hdts->State = HAL_DTS_STATE_READY;
0753 }
0754 else
0755 {
0756 return HAL_BUSY;
0757 }
0758
0759 return HAL_OK;
0760 }
0761
0762
0763
0764
0765
0766
0767 void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts)
0768 {
0769
0770 if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITE)) != RESET)
0771 {
0772 __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITE);
0773
0774 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
0775 hdts->AsyncEndCallback(hdts);
0776 #else
0777 HAL_DTS_AsyncEndCallback(hdts);
0778 #endif
0779 }
0780
0781
0782 if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITL)) != RESET)
0783 {
0784 __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITL);
0785
0786 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
0787 hdts->AsyncLowCallback(hdts);
0788 #else
0789 HAL_DTS_AsyncLowCallback(hdts);
0790 #endif
0791 }
0792
0793
0794 if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITH)) != RESET)
0795 {
0796 __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITH);
0797
0798 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
0799 hdts->AsyncHighCallback(hdts);
0800 #else
0801 HAL_DTS_AsyncHighCallback(hdts);
0802 #endif
0803 }
0804
0805
0806 if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITE)) != RESET)
0807 {
0808 __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITE);
0809
0810 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
0811 hdts->EndCallback(hdts);
0812 #else
0813 HAL_DTS_EndCallback(hdts);
0814 #endif
0815 }
0816
0817
0818 if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITL)) != RESET)
0819 {
0820 __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITL);
0821
0822 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
0823 hdts->LowCallback(hdts);
0824 #else
0825 HAL_DTS_LowCallback(hdts);
0826 #endif
0827 }
0828
0829
0830 if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITH)) != RESET)
0831 {
0832 __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITH);
0833
0834 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
0835 hdts->HighCallback(hdts);
0836 #else
0837 HAL_DTS_HighCallback(hdts);
0838 #endif
0839 }
0840 }
0841
0842
0843
0844
0845
0846
0847 __weak void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts)
0848 {
0849
0850 UNUSED(hdts);
0851
0852
0853
0854
0855 }
0856
0857
0858
0859
0860
0861
0862 __weak void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts)
0863 {
0864
0865 UNUSED(hdts);
0866
0867
0868
0869
0870 }
0871
0872
0873
0874
0875
0876
0877 __weak void HAL_DTS_HighCallback(DTS_HandleTypeDef *hdts)
0878 {
0879
0880 UNUSED(hdts);
0881
0882
0883
0884
0885 }
0886
0887
0888
0889
0890
0891
0892 __weak void HAL_DTS_AsyncEndCallback(DTS_HandleTypeDef *hdts)
0893 {
0894
0895 UNUSED(hdts);
0896
0897
0898
0899
0900 }
0901
0902
0903
0904
0905
0906
0907 __weak void HAL_DTS_AsyncLowCallback(DTS_HandleTypeDef *hdts)
0908 {
0909
0910 UNUSED(hdts);
0911
0912
0913
0914
0915 }
0916
0917
0918
0919
0920
0921
0922 __weak void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts)
0923 {
0924
0925 UNUSED(hdts);
0926
0927
0928
0929
0930 }
0931
0932
0933
0934
0935
0936
0937
0938
0939
0940
0941
0942
0943
0944
0945
0946
0947
0948
0949
0950
0951
0952
0953
0954
0955
0956 HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts)
0957 {
0958
0959 if (hdts == NULL)
0960 {
0961 return HAL_DTS_STATE_RESET;
0962 }
0963
0964
0965 return hdts->State;
0966 }
0967
0968
0969
0970
0971
0972
0973
0974
0975
0976
0977
0978
0979 #endif
0980
0981 #endif
0982
0983
0984
0985
0986