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0268 #include "stm32h7xx_hal.h"
0269
0270
0271
0272
0273 #ifdef HAL_DFSDM_MODULE_ENABLED
0274
0275
0276
0277
0278
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0280
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0286
0287 #define DFSDM_FLTCR1_MSB_RCH_OFFSET 8
0288 #define DFSDM_MSB_MASK 0xFFFF0000U
0289 #define DFSDM_LSB_MASK 0x0000FFFFU
0290 #define DFSDM_CKAB_TIMEOUT 5000U
0291 #define DFSDM1_CHANNEL_NUMBER 8U
0292 #if defined(DFSDM2_Channel0)
0293 #define DFSDM2_CHANNEL_NUMBER 2U
0294 #endif
0295
0296
0297
0298
0299
0300
0301
0302
0303
0304
0305 static __IO uint32_t v_dfsdm1ChannelCounter = 0;
0306 static DFSDM_Channel_HandleTypeDef *a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};
0307 #if defined(DFSDM2_Channel0)
0308 static __IO uint32_t v_dfsdm2ChannelCounter = 0;
0309 static DFSDM_Channel_HandleTypeDef *a_dfsdm2ChannelHandle[DFSDM2_CHANNEL_NUMBER] = {NULL};
0310 #endif
0311
0312
0313
0314
0315
0316
0317
0318
0319
0320 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
0321 static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance);
0322 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
0323 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
0324 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
0325 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
0326 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
0327 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
0328 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
0329 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
0330 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma);
0331
0332
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0360
0361
0362 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
0363 {
0364 __IO uint32_t *channelCounterPtr;
0365 DFSDM_Channel_HandleTypeDef **channelHandleTable;
0366 DFSDM_Channel_TypeDef *channel0Instance;
0367
0368
0369 if(hdfsdm_channel == NULL)
0370 {
0371 return HAL_ERROR;
0372 }
0373
0374
0375 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
0376 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));
0377 assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));
0378 assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));
0379 assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));
0380 assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));
0381 assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));
0382 assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));
0383 assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
0384 assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
0385 assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
0386
0387 #if defined(DFSDM2_Channel0)
0388 if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
0389 {
0390 channelCounterPtr = &v_dfsdm1ChannelCounter;
0391 channelHandleTable = a_dfsdm1ChannelHandle;
0392 channel0Instance = DFSDM1_Channel0;
0393 }
0394 else
0395 {
0396 channelCounterPtr = &v_dfsdm2ChannelCounter;
0397 channelHandleTable = a_dfsdm2ChannelHandle;
0398 channel0Instance = DFSDM2_Channel0;
0399 }
0400 #else
0401 channelCounterPtr = &v_dfsdm1ChannelCounter;
0402 channelHandleTable = a_dfsdm1ChannelHandle;
0403 channel0Instance = DFSDM1_Channel0;
0404 #endif
0405
0406
0407 if (channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
0408 {
0409 return HAL_ERROR;
0410 }
0411
0412 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
0413
0414 hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
0415 hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
0416
0417
0418 if(hdfsdm_channel->MspInitCallback == NULL)
0419 {
0420 hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
0421 }
0422 hdfsdm_channel->MspInitCallback(hdfsdm_channel);
0423 #else
0424
0425 HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
0426 #endif
0427
0428
0429 (*channelCounterPtr)++;
0430
0431
0432 if(*channelCounterPtr == 1U)
0433 {
0434 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
0435
0436 channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
0437 channel0Instance->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
0438
0439
0440 channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
0441 if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
0442 {
0443 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
0444
0445 channel0Instance->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
0446 DFSDM_CHCFGR1_CKOUTDIV_Pos);
0447 }
0448
0449
0450 channel0Instance->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
0451 }
0452
0453
0454 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
0455 DFSDM_CHCFGR1_CHINSEL);
0456 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
0457 hdfsdm_channel->Init.Input.DataPacking |
0458 hdfsdm_channel->Init.Input.Pins);
0459
0460
0461 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
0462 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
0463 hdfsdm_channel->Init.SerialInterface.SpiClock);
0464
0465
0466 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
0467 hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
0468 ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
0469
0470
0471 hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
0472 hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
0473 (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
0474
0475
0476 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
0477
0478
0479 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
0480
0481
0482 channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
0483
0484 return HAL_OK;
0485 }
0486
0487
0488
0489
0490
0491
0492 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
0493 {
0494 __IO uint32_t *channelCounterPtr;
0495 DFSDM_Channel_HandleTypeDef **channelHandleTable;
0496 DFSDM_Channel_TypeDef *channel0Instance;
0497
0498
0499 if(hdfsdm_channel == NULL)
0500 {
0501 return HAL_ERROR;
0502 }
0503
0504
0505 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
0506
0507 #if defined(DFSDM2_Channel0)
0508 if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
0509 {
0510 channelCounterPtr = &v_dfsdm1ChannelCounter;
0511 channelHandleTable = a_dfsdm1ChannelHandle;
0512 channel0Instance = DFSDM1_Channel0;
0513 }
0514 else
0515 {
0516 channelCounterPtr = &v_dfsdm2ChannelCounter;
0517 channelHandleTable = a_dfsdm2ChannelHandle;
0518 channel0Instance = DFSDM2_Channel0;
0519 }
0520 #else
0521 channelCounterPtr = &v_dfsdm1ChannelCounter;
0522 channelHandleTable = a_dfsdm1ChannelHandle;
0523 channel0Instance = DFSDM1_Channel0;
0524 #endif
0525
0526
0527 if (channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
0528 {
0529 return HAL_ERROR;
0530 }
0531
0532
0533 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
0534
0535
0536 (*channelCounterPtr)--;
0537
0538
0539 if (*channelCounterPtr == 0U)
0540 {
0541 channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
0542 }
0543
0544
0545 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
0546 if(hdfsdm_channel->MspDeInitCallback == NULL)
0547 {
0548 hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
0549 }
0550 hdfsdm_channel->MspDeInitCallback(hdfsdm_channel);
0551 #else
0552 HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
0553 #endif
0554
0555
0556 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
0557
0558
0559 channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;
0560
0561 return HAL_OK;
0562 }
0563
0564
0565
0566
0567
0568
0569 __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
0570 {
0571
0572 UNUSED(hdfsdm_channel);
0573
0574
0575
0576
0577 }
0578
0579
0580
0581
0582
0583
0584 __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
0585 {
0586
0587 UNUSED(hdfsdm_channel);
0588
0589
0590
0591
0592 }
0593
0594 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
0595
0596
0597
0598
0599
0600
0601
0602
0603
0604
0605
0606
0607
0608 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
0609 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
0610 pDFSDM_Channel_CallbackTypeDef pCallback)
0611 {
0612 HAL_StatusTypeDef status = HAL_OK;
0613
0614 if(pCallback == NULL)
0615 {
0616
0617 status = HAL_ERROR;
0618 }
0619 else
0620 {
0621 if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)
0622 {
0623 switch (CallbackID)
0624 {
0625 case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
0626 hdfsdm_channel->CkabCallback = pCallback;
0627 break;
0628 case HAL_DFSDM_CHANNEL_SCD_CB_ID :
0629 hdfsdm_channel->ScdCallback = pCallback;
0630 break;
0631 case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
0632 hdfsdm_channel->MspInitCallback = pCallback;
0633 break;
0634 case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
0635 hdfsdm_channel->MspDeInitCallback = pCallback;
0636 break;
0637 default :
0638
0639 status = HAL_ERROR;
0640 break;
0641 }
0642 }
0643 else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)
0644 {
0645 switch (CallbackID)
0646 {
0647 case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
0648 hdfsdm_channel->MspInitCallback = pCallback;
0649 break;
0650 case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
0651 hdfsdm_channel->MspDeInitCallback = pCallback;
0652 break;
0653 default :
0654
0655 status = HAL_ERROR;
0656 break;
0657 }
0658 }
0659 else
0660 {
0661
0662 status = HAL_ERROR;
0663 }
0664 }
0665 return status;
0666 }
0667
0668
0669
0670
0671
0672
0673
0674
0675
0676
0677
0678
0679
0680 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
0681 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID)
0682 {
0683 HAL_StatusTypeDef status = HAL_OK;
0684
0685 if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)
0686 {
0687 switch (CallbackID)
0688 {
0689 case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
0690 hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
0691 break;
0692 case HAL_DFSDM_CHANNEL_SCD_CB_ID :
0693 hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
0694 break;
0695 case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
0696 hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
0697 break;
0698 case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
0699 hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
0700 break;
0701 default :
0702
0703 status = HAL_ERROR;
0704 break;
0705 }
0706 }
0707 else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)
0708 {
0709 switch (CallbackID)
0710 {
0711 case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
0712 hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
0713 break;
0714 case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
0715 hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
0716 break;
0717 default :
0718
0719 status = HAL_ERROR;
0720 break;
0721 }
0722 }
0723 else
0724 {
0725
0726 status = HAL_ERROR;
0727 }
0728 return status;
0729 }
0730 #endif
0731
0732
0733
0734
0735
0736
0737
0738
0739
0740
0741
0742
0743
0744
0745
0746
0747
0748
0749
0750
0751
0752
0753
0754
0755
0756
0757
0758
0759
0760
0761
0762 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
0763 {
0764 HAL_StatusTypeDef status = HAL_OK;
0765 uint32_t channel;
0766 uint32_t tickstart;
0767 DFSDM_Filter_TypeDef *filter0Instance;
0768
0769
0770 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
0771
0772 #if defined(DFSDM2_Channel0)
0773 if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
0774 {
0775 filter0Instance = DFSDM1_Filter0;
0776 }
0777 else
0778 {
0779 filter0Instance = DFSDM2_Filter0;
0780 }
0781 #else
0782 filter0Instance = DFSDM1_Filter0;
0783 #endif
0784
0785
0786 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
0787 {
0788
0789 status = HAL_ERROR;
0790 }
0791 else
0792 {
0793
0794 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
0795
0796
0797 tickstart = HAL_GetTick();
0798
0799
0800 while ((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
0801 {
0802 filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
0803
0804
0805 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
0806 {
0807
0808 status = HAL_TIMEOUT;
0809 break;
0810 }
0811 }
0812
0813 if(status == HAL_OK)
0814 {
0815
0816 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
0817 }
0818 }
0819
0820 return status;
0821 }
0822
0823
0824
0825
0826
0827
0828
0829 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
0830 uint32_t Timeout)
0831 {
0832 uint32_t tickstart;
0833 uint32_t channel;
0834 DFSDM_Filter_TypeDef *filter0Instance;
0835
0836
0837 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
0838
0839 #if defined(DFSDM2_Channel0)
0840 if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
0841 {
0842 filter0Instance = DFSDM1_Filter0;
0843 }
0844 else
0845 {
0846 filter0Instance = DFSDM2_Filter0;
0847 }
0848 #else
0849 filter0Instance = DFSDM1_Filter0;
0850 #endif
0851
0852
0853 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
0854 {
0855
0856 return HAL_ERROR;
0857 }
0858 else
0859 {
0860
0861 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
0862
0863
0864 tickstart = HAL_GetTick();
0865
0866
0867 while ((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)
0868 {
0869
0870 if(Timeout != HAL_MAX_DELAY)
0871 {
0872 if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
0873 {
0874
0875 return HAL_TIMEOUT;
0876 }
0877 }
0878 }
0879
0880
0881 filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
0882
0883
0884 return HAL_OK;
0885 }
0886 }
0887
0888
0889
0890
0891
0892
0893 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
0894 {
0895 HAL_StatusTypeDef status = HAL_OK;
0896 uint32_t channel;
0897 DFSDM_Filter_TypeDef *filter0Instance;
0898
0899
0900 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
0901
0902 #if defined(DFSDM2_Channel0)
0903 if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
0904 {
0905 filter0Instance = DFSDM1_Filter0;
0906 }
0907 else
0908 {
0909 filter0Instance = DFSDM2_Filter0;
0910 }
0911 #else
0912 filter0Instance = DFSDM1_Filter0;
0913 #endif
0914
0915
0916 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
0917 {
0918
0919 status = HAL_ERROR;
0920 }
0921 else
0922 {
0923
0924 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
0925
0926
0927 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
0928 filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
0929 }
0930
0931 return status;
0932 }
0933
0934
0935
0936
0937
0938
0939
0940
0941
0942
0943 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
0944 {
0945 HAL_StatusTypeDef status = HAL_OK;
0946 uint32_t channel;
0947 uint32_t tickstart;
0948 DFSDM_Filter_TypeDef *filter0Instance;
0949
0950
0951 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
0952
0953 #if defined(DFSDM2_Channel0)
0954 if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
0955 {
0956 filter0Instance = DFSDM1_Filter0;
0957 }
0958 else
0959 {
0960 filter0Instance = DFSDM2_Filter0;
0961 }
0962 #else
0963 filter0Instance = DFSDM1_Filter0;
0964 #endif
0965
0966
0967 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
0968 {
0969
0970 status = HAL_ERROR;
0971 }
0972 else
0973 {
0974
0975 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
0976
0977
0978 tickstart = HAL_GetTick();
0979
0980
0981 while ((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
0982 {
0983 filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
0984
0985
0986 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
0987 {
0988
0989 status = HAL_TIMEOUT;
0990 break;
0991 }
0992 }
0993
0994 if(status == HAL_OK)
0995 {
0996
0997 filter0Instance->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
0998
0999
1000 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
1001 }
1002 }
1003
1004 return status;
1005 }
1006
1007
1008
1009
1010
1011
1012 __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1013 {
1014
1015 UNUSED(hdfsdm_channel);
1016
1017
1018
1019
1020 }
1021
1022
1023
1024
1025
1026
1027
1028 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1029 {
1030 HAL_StatusTypeDef status = HAL_OK;
1031 uint32_t channel;
1032 DFSDM_Filter_TypeDef *filter0Instance;
1033
1034
1035 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1036
1037 #if defined(DFSDM2_Channel0)
1038 if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1039 {
1040 filter0Instance = DFSDM1_Filter0;
1041 }
1042 else
1043 {
1044 filter0Instance = DFSDM2_Filter0;
1045 }
1046 #else
1047 filter0Instance = DFSDM1_Filter0;
1048 #endif
1049
1050
1051 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1052 {
1053
1054 status = HAL_ERROR;
1055 }
1056 else
1057 {
1058
1059 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
1060
1061
1062 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1063 filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
1064
1065
1066 filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
1067 }
1068
1069 return status;
1070 }
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
1083 uint32_t Threshold,
1084 uint32_t BreakSignal)
1085 {
1086 HAL_StatusTypeDef status = HAL_OK;
1087
1088
1089 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1090 assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
1091 assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
1092
1093
1094 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1095 {
1096
1097 status = HAL_ERROR;
1098 }
1099 else
1100 {
1101
1102 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
1103 hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
1104 Threshold);
1105
1106
1107 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
1108 }
1109
1110 return status;
1111 }
1112
1113
1114
1115
1116
1117
1118
1119 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
1120 uint32_t Timeout)
1121 {
1122 uint32_t tickstart;
1123 uint32_t channel;
1124 DFSDM_Filter_TypeDef *filter0Instance;
1125
1126
1127 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1128
1129 #if defined(DFSDM2_Channel0)
1130 if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1131 {
1132 filter0Instance = DFSDM1_Filter0;
1133 }
1134 else
1135 {
1136 filter0Instance = DFSDM2_Filter0;
1137 }
1138 #else
1139 filter0Instance = DFSDM1_Filter0;
1140 #endif
1141
1142
1143 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1144 {
1145
1146 return HAL_ERROR;
1147 }
1148 else
1149 {
1150
1151 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1152
1153
1154 tickstart = HAL_GetTick();
1155
1156
1157 while (((filter0Instance->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)
1158 {
1159
1160 if(Timeout != HAL_MAX_DELAY)
1161 {
1162 if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
1163 {
1164
1165 return HAL_TIMEOUT;
1166 }
1167 }
1168 }
1169
1170
1171 filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
1172
1173
1174 return HAL_OK;
1175 }
1176 }
1177
1178
1179
1180
1181
1182
1183 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1184 {
1185 HAL_StatusTypeDef status = HAL_OK;
1186 uint32_t channel;
1187 DFSDM_Filter_TypeDef *filter0Instance;
1188
1189
1190 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1191
1192 #if defined(DFSDM2_Channel0)
1193 if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1194 {
1195 filter0Instance = DFSDM1_Filter0;
1196 }
1197 else
1198 {
1199 filter0Instance = DFSDM2_Filter0;
1200 }
1201 #else
1202 filter0Instance = DFSDM1_Filter0;
1203 #endif
1204
1205
1206 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1207 {
1208
1209 status = HAL_ERROR;
1210 }
1211 else
1212 {
1213
1214 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
1215
1216
1217 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1218 filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
1219 }
1220
1221 return status;
1222 }
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
1235 uint32_t Threshold,
1236 uint32_t BreakSignal)
1237 {
1238 HAL_StatusTypeDef status = HAL_OK;
1239 DFSDM_Filter_TypeDef *filter0Instance;
1240
1241
1242 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1243 assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
1244 assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
1245
1246 #if defined(DFSDM2_Channel0)
1247 if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1248 {
1249 filter0Instance = DFSDM1_Filter0;
1250 }
1251 else
1252 {
1253 filter0Instance = DFSDM2_Filter0;
1254 }
1255 #else
1256 filter0Instance = DFSDM1_Filter0;
1257 #endif
1258
1259
1260 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1261 {
1262
1263 status = HAL_ERROR;
1264 }
1265 else
1266 {
1267
1268 filter0Instance->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
1269
1270
1271 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
1272 hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
1273 Threshold);
1274
1275
1276 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
1277 }
1278
1279 return status;
1280 }
1281
1282
1283
1284
1285
1286
1287 __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1288 {
1289
1290 UNUSED(hdfsdm_channel);
1291
1292
1293
1294
1295 }
1296
1297
1298
1299
1300
1301
1302
1303 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1304 {
1305 HAL_StatusTypeDef status = HAL_OK;
1306 uint32_t channel;
1307 DFSDM_Filter_TypeDef *filter0Instance;
1308
1309
1310 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1311
1312 #if defined(DFSDM2_Channel0)
1313 if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1314 {
1315 filter0Instance = DFSDM1_Filter0;
1316 }
1317 else
1318 {
1319 filter0Instance = DFSDM2_Filter0;
1320 }
1321 #else
1322 filter0Instance = DFSDM1_Filter0;
1323 #endif
1324
1325
1326 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1327 {
1328
1329 status = HAL_ERROR;
1330 }
1331 else
1332 {
1333
1334 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
1335
1336
1337 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1338 filter0Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
1339
1340
1341 filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
1342 }
1343
1344 return status;
1345 }
1346
1347
1348
1349
1350
1351
1352 int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1353 {
1354 return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
1355 }
1356
1357
1358
1359
1360
1361
1362
1363
1364 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
1365 int32_t Offset)
1366 {
1367 HAL_StatusTypeDef status = HAL_OK;
1368
1369
1370 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1371 assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
1372
1373
1374 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1375 {
1376
1377 status = HAL_ERROR;
1378 }
1379 else
1380 {
1381
1382 hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
1383 hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos);
1384 }
1385
1386 return status;
1387 }
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1413 {
1414
1415 return hdfsdm_channel->State;
1416 }
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1444 {
1445 const DFSDM_Filter_TypeDef *filter0Instance;
1446
1447
1448 if(hdfsdm_filter == NULL)
1449 {
1450 return HAL_ERROR;
1451 }
1452
1453
1454 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1455 assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));
1456 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));
1457 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));
1458 assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));
1459 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));
1460 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));
1461 assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));
1462 assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));
1463 assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
1464
1465 #if defined(DFSDM2_Channel0)
1466 if (IS_DFSDM1_FILTER_INSTANCE(hdfsdm_filter->Instance))
1467 {
1468 filter0Instance = DFSDM1_Filter0;
1469 }
1470 else
1471 {
1472 filter0Instance = DFSDM2_Filter0;
1473 }
1474 #else
1475 filter0Instance = DFSDM1_Filter0;
1476 #endif
1477
1478
1479 if ((hdfsdm_filter->Instance == filter0Instance) &&
1480 ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
1481 (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
1482 {
1483 return HAL_ERROR;
1484 }
1485
1486
1487 hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF;
1488 hdfsdm_filter->InjectedChannelsNbr = 1;
1489 hdfsdm_filter->InjConvRemaining = 1;
1490 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE;
1491
1492 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
1493
1494 hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;
1495 hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;
1496 hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;
1497 hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback;
1498 hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;
1499 hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback;
1500
1501
1502 if(hdfsdm_filter->MspInitCallback == NULL)
1503 {
1504 hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
1505 }
1506 hdfsdm_filter->MspInitCallback(hdfsdm_filter);
1507 #else
1508
1509 HAL_DFSDM_FilterMspInit(hdfsdm_filter);
1510 #endif
1511
1512
1513 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
1514 if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)
1515 {
1516 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;
1517 }
1518 else
1519 {
1520 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
1521 }
1522
1523 if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)
1524 {
1525 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;
1526 }
1527 else
1528 {
1529 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);
1530 }
1531
1532
1533 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);
1534 if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)
1535 {
1536 assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));
1537 assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));
1538 hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);
1539 }
1540
1541 if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)
1542 {
1543 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;
1544 }
1545 else
1546 {
1547 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
1548 }
1549
1550 if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)
1551 {
1552 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;
1553 }
1554 else
1555 {
1556 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
1557 }
1558
1559
1560 hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
1561 hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
1562 ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_Pos) |
1563 (hdfsdm_filter->Init.FilterParam.IntOversampling - 1U));
1564
1565
1566 hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger;
1567 hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger;
1568 hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
1569 hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
1570
1571
1572 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
1573
1574
1575 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
1576
1577 return HAL_OK;
1578 }
1579
1580
1581
1582
1583
1584
1585 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1586 {
1587
1588 if(hdfsdm_filter == NULL)
1589 {
1590 return HAL_ERROR;
1591 }
1592
1593
1594 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1595
1596
1597 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
1598
1599
1600 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
1601 if(hdfsdm_filter->MspDeInitCallback == NULL)
1602 {
1603 hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
1604 }
1605 hdfsdm_filter->MspDeInitCallback(hdfsdm_filter);
1606 #else
1607 HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
1608 #endif
1609
1610
1611 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
1612
1613 return HAL_OK;
1614 }
1615
1616
1617
1618
1619
1620
1621 __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1622 {
1623
1624 UNUSED(hdfsdm_filter);
1625
1626
1627
1628
1629 }
1630
1631
1632
1633
1634
1635
1636 __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1637 {
1638
1639 UNUSED(hdfsdm_filter);
1640
1641
1642
1643
1644 }
1645
1646 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
1664 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
1665 pDFSDM_Filter_CallbackTypeDef pCallback)
1666 {
1667 HAL_StatusTypeDef status = HAL_OK;
1668
1669 if(pCallback == NULL)
1670 {
1671
1672 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1673
1674 status = HAL_ERROR;
1675 }
1676 else
1677 {
1678 if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
1679 {
1680 switch (CallbackID)
1681 {
1682 case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
1683 hdfsdm_filter->RegConvCpltCallback = pCallback;
1684 break;
1685 case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
1686 hdfsdm_filter->RegConvHalfCpltCallback = pCallback;
1687 break;
1688 case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
1689 hdfsdm_filter->InjConvCpltCallback = pCallback;
1690 break;
1691 case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
1692 hdfsdm_filter->InjConvHalfCpltCallback = pCallback;
1693 break;
1694 case HAL_DFSDM_FILTER_ERROR_CB_ID :
1695 hdfsdm_filter->ErrorCallback = pCallback;
1696 break;
1697 case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
1698 hdfsdm_filter->MspInitCallback = pCallback;
1699 break;
1700 case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
1701 hdfsdm_filter->MspDeInitCallback = pCallback;
1702 break;
1703 default :
1704
1705 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1706
1707 status = HAL_ERROR;
1708 break;
1709 }
1710 }
1711 else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)
1712 {
1713 switch (CallbackID)
1714 {
1715 case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
1716 hdfsdm_filter->MspInitCallback = pCallback;
1717 break;
1718 case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
1719 hdfsdm_filter->MspDeInitCallback = pCallback;
1720 break;
1721 default :
1722
1723 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1724
1725 status = HAL_ERROR;
1726 break;
1727 }
1728 }
1729 else
1730 {
1731
1732 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1733
1734 status = HAL_ERROR;
1735 }
1736 }
1737 return status;
1738 }
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
1756 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID)
1757 {
1758 HAL_StatusTypeDef status = HAL_OK;
1759
1760 if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
1761 {
1762 switch (CallbackID)
1763 {
1764 case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
1765 hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;
1766 break;
1767 case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
1768 hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;
1769 break;
1770 case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
1771 hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback;
1772 break;
1773 case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
1774 hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;
1775 break;
1776 case HAL_DFSDM_FILTER_ERROR_CB_ID :
1777 hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback;
1778 break;
1779 case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
1780 hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
1781 break;
1782 case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
1783 hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
1784 break;
1785 default :
1786
1787 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1788
1789 status = HAL_ERROR;
1790 break;
1791 }
1792 }
1793 else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)
1794 {
1795 switch (CallbackID)
1796 {
1797 case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
1798 hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
1799 break;
1800 case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
1801 hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
1802 break;
1803 default :
1804
1805 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1806
1807 status = HAL_ERROR;
1808 break;
1809 }
1810 }
1811 else
1812 {
1813
1814 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1815
1816 status = HAL_ERROR;
1817 }
1818 return status;
1819 }
1820
1821
1822
1823
1824
1825
1826
1827
1828 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
1829 pDFSDM_Filter_AwdCallbackTypeDef pCallback)
1830 {
1831 HAL_StatusTypeDef status = HAL_OK;
1832
1833 if(pCallback == NULL)
1834 {
1835
1836 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1837
1838 status = HAL_ERROR;
1839 }
1840 else
1841 {
1842 if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
1843 {
1844 hdfsdm_filter->AwdCallback = pCallback;
1845 }
1846 else
1847 {
1848
1849 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1850
1851 status = HAL_ERROR;
1852 }
1853 }
1854 return status;
1855 }
1856
1857
1858
1859
1860
1861
1862
1863 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1864 {
1865 HAL_StatusTypeDef status = HAL_OK;
1866
1867 if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
1868 {
1869 hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;
1870 }
1871 else
1872 {
1873
1874 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1875
1876 status = HAL_ERROR;
1877 }
1878 return status;
1879 }
1880 #endif
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
1912 uint32_t Channel,
1913 uint32_t ContinuousMode)
1914 {
1915 HAL_StatusTypeDef status = HAL_OK;
1916
1917
1918 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1919 assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
1920 assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
1921
1922
1923 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
1924 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
1925 {
1926
1927 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
1928 if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
1929 {
1930 hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
1931 DFSDM_FLTCR1_RCONT);
1932 }
1933 else
1934 {
1935 hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);
1936 }
1937
1938 hdfsdm_filter->RegularContMode = ContinuousMode;
1939 }
1940 else
1941 {
1942 status = HAL_ERROR;
1943 }
1944
1945
1946 return status;
1947 }
1948
1949
1950
1951
1952
1953
1954
1955
1956 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
1957 uint32_t Channel)
1958 {
1959 HAL_StatusTypeDef status = HAL_OK;
1960
1961
1962 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1963 assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
1964
1965
1966 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
1967 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
1968 {
1969
1970 hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
1971
1972 hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
1973
1974 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
1975 hdfsdm_filter->InjectedChannelsNbr : 1U;
1976 }
1977 else
1978 {
1979 status = HAL_ERROR;
1980 }
1981
1982 return status;
1983 }
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2028 {
2029 HAL_StatusTypeDef status = HAL_OK;
2030
2031
2032 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2033
2034
2035 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2036 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
2037 {
2038
2039 DFSDM_RegConvStart(hdfsdm_filter);
2040 }
2041 else
2042 {
2043 status = HAL_ERROR;
2044 }
2045
2046 return status;
2047 }
2048
2049
2050
2051
2052
2053
2054
2055
2056 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2057 uint32_t Timeout)
2058 {
2059 uint32_t tickstart;
2060
2061
2062 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2063
2064
2065 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
2066 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2067 {
2068
2069 return HAL_ERROR;
2070 }
2071 else
2072 {
2073
2074 tickstart = HAL_GetTick();
2075
2076
2077 while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
2078 {
2079
2080 if(Timeout != HAL_MAX_DELAY)
2081 {
2082 if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
2083 {
2084
2085 return HAL_TIMEOUT;
2086 }
2087 }
2088 }
2089
2090 if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)
2091 {
2092
2093 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
2094 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
2095 hdfsdm_filter->ErrorCallback(hdfsdm_filter);
2096 #else
2097 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
2098 #endif
2099
2100
2101 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
2102 }
2103
2104 if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
2105 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
2106 {
2107 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
2108 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
2109 }
2110
2111 return HAL_OK;
2112 }
2113 }
2114
2115
2116
2117
2118
2119
2120
2121 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2122 {
2123 HAL_StatusTypeDef status = HAL_OK;
2124
2125
2126 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2127
2128
2129 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
2130 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2131 {
2132
2133 status = HAL_ERROR;
2134 }
2135 else
2136 {
2137
2138 DFSDM_RegConvStop(hdfsdm_filter);
2139 }
2140
2141 return status;
2142 }
2143
2144
2145
2146
2147
2148
2149
2150
2151 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2152 {
2153 HAL_StatusTypeDef status = HAL_OK;
2154
2155
2156 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2157
2158
2159 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2160 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
2161 {
2162
2163 hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
2164
2165
2166 DFSDM_RegConvStart(hdfsdm_filter);
2167 }
2168 else
2169 {
2170 status = HAL_ERROR;
2171 }
2172
2173 return status;
2174 }
2175
2176
2177
2178
2179
2180
2181
2182 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2183 {
2184 HAL_StatusTypeDef status = HAL_OK;
2185
2186
2187 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2188
2189
2190 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
2191 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2192 {
2193
2194 status = HAL_ERROR;
2195 }
2196 else
2197 {
2198
2199 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
2200
2201
2202 DFSDM_RegConvStop(hdfsdm_filter);
2203 }
2204
2205 return status;
2206 }
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2221 int32_t *pData,
2222 uint32_t Length)
2223 {
2224 HAL_StatusTypeDef status = HAL_OK;
2225
2226
2227 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2228
2229
2230 if((pData == NULL) || (Length == 0U))
2231 {
2232 status = HAL_ERROR;
2233 }
2234
2235 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
2236 {
2237 status = HAL_ERROR;
2238 }
2239
2240 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2241 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
2242 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
2243 (Length != 1U))
2244 {
2245 status = HAL_ERROR;
2246 }
2247 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2248 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
2249 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
2250 {
2251 status = HAL_ERROR;
2252 }
2253
2254 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2255 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
2256 {
2257
2258 hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
2259 hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
2260 hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
2261 DFSDM_DMARegularHalfConvCplt : NULL;
2262
2263
2264 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
2265 (uint32_t) pData, Length) != HAL_OK)
2266 {
2267
2268 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2269 status = HAL_ERROR;
2270 }
2271 else
2272 {
2273
2274 DFSDM_RegConvStart(hdfsdm_filter);
2275 }
2276 }
2277 else
2278 {
2279 status = HAL_ERROR;
2280 }
2281
2282 return status;
2283 }
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2298 int16_t *pData,
2299 uint32_t Length)
2300 {
2301 HAL_StatusTypeDef status = HAL_OK;
2302
2303
2304 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2305
2306
2307 if((pData == NULL) || (Length == 0U))
2308 {
2309 status = HAL_ERROR;
2310 }
2311
2312 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
2313 {
2314 status = HAL_ERROR;
2315 }
2316
2317 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2318 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
2319 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
2320 (Length != 1U))
2321 {
2322 status = HAL_ERROR;
2323 }
2324 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2325 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
2326 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
2327 {
2328 status = HAL_ERROR;
2329 }
2330
2331 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2332 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
2333 {
2334
2335 hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
2336 hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
2337 hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
2338 DFSDM_DMARegularHalfConvCplt : NULL;
2339
2340
2341 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \
2342 (uint32_t) pData, Length) != HAL_OK)
2343 {
2344
2345 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2346 status = HAL_ERROR;
2347 }
2348 else
2349 {
2350
2351 DFSDM_RegConvStart(hdfsdm_filter);
2352 }
2353 }
2354 else
2355 {
2356 status = HAL_ERROR;
2357 }
2358
2359 return status;
2360 }
2361
2362
2363
2364
2365
2366
2367
2368 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2369 {
2370 HAL_StatusTypeDef status = HAL_OK;
2371
2372
2373 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2374
2375
2376 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
2377 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2378 {
2379
2380 status = HAL_ERROR;
2381 }
2382 else
2383 {
2384
2385 if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)
2386 {
2387
2388 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2389 status = HAL_ERROR;
2390 }
2391 else
2392 {
2393
2394 DFSDM_RegConvStop(hdfsdm_filter);
2395 }
2396 }
2397
2398 return status;
2399 }
2400
2401
2402
2403
2404
2405
2406
2407 int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2408 uint32_t *Channel)
2409 {
2410 uint32_t reg;
2411 int32_t value;
2412
2413
2414 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2415 assert_param(Channel != (void *)0);
2416
2417
2418 reg = hdfsdm_filter->Instance->FLTRDATAR;
2419
2420
2421 *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
2422
2423
2424 reg &= DFSDM_FLTRDATAR_RDATA;
2425 value = ((int32_t)reg) / 256;
2426
2427
2428 return value;
2429 }
2430
2431
2432
2433
2434
2435
2436
2437
2438 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2439 {
2440 HAL_StatusTypeDef status = HAL_OK;
2441
2442
2443 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2444
2445
2446 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2447 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
2448 {
2449
2450 DFSDM_InjConvStart(hdfsdm_filter);
2451 }
2452 else
2453 {
2454 status = HAL_ERROR;
2455 }
2456
2457 return status;
2458 }
2459
2460
2461
2462
2463
2464
2465
2466
2467 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2468 uint32_t Timeout)
2469 {
2470 uint32_t tickstart;
2471
2472
2473 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2474
2475
2476 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
2477 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2478 {
2479
2480 return HAL_ERROR;
2481 }
2482 else
2483 {
2484
2485 tickstart = HAL_GetTick();
2486
2487
2488 while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
2489 {
2490
2491 if(Timeout != HAL_MAX_DELAY)
2492 {
2493 if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
2494 {
2495
2496 return HAL_TIMEOUT;
2497 }
2498 }
2499 }
2500
2501 if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)
2502 {
2503
2504 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
2505 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
2506 hdfsdm_filter->ErrorCallback(hdfsdm_filter);
2507 #else
2508 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
2509 #endif
2510
2511
2512 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
2513 }
2514
2515
2516 hdfsdm_filter->InjConvRemaining--;
2517 if(hdfsdm_filter->InjConvRemaining == 0U)
2518 {
2519
2520 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
2521 {
2522 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
2523 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
2524 }
2525
2526
2527 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
2528 hdfsdm_filter->InjectedChannelsNbr : 1U;
2529 }
2530
2531
2532 return HAL_OK;
2533 }
2534 }
2535
2536
2537
2538
2539
2540
2541
2542 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2543 {
2544 HAL_StatusTypeDef status = HAL_OK;
2545
2546
2547 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2548
2549
2550 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
2551 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2552 {
2553
2554 status = HAL_ERROR;
2555 }
2556 else
2557 {
2558
2559 DFSDM_InjConvStop(hdfsdm_filter);
2560 }
2561
2562 return status;
2563 }
2564
2565
2566
2567
2568
2569
2570
2571
2572 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2573 {
2574 HAL_StatusTypeDef status = HAL_OK;
2575
2576
2577 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2578
2579
2580 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2581 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
2582 {
2583
2584 hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
2585
2586
2587 DFSDM_InjConvStart(hdfsdm_filter);
2588 }
2589 else
2590 {
2591 status = HAL_ERROR;
2592 }
2593
2594 return status;
2595 }
2596
2597
2598
2599
2600
2601
2602
2603 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2604 {
2605 HAL_StatusTypeDef status = HAL_OK;
2606
2607
2608 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2609
2610
2611 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
2612 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2613 {
2614
2615 status = HAL_ERROR;
2616 }
2617 else
2618 {
2619
2620 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
2621
2622
2623 DFSDM_InjConvStop(hdfsdm_filter);
2624 }
2625
2626 return status;
2627 }
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2642 int32_t *pData,
2643 uint32_t Length)
2644 {
2645 HAL_StatusTypeDef status = HAL_OK;
2646
2647
2648 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2649
2650
2651 if((pData == NULL) || (Length == 0U))
2652 {
2653 status = HAL_ERROR;
2654 }
2655
2656 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
2657 {
2658 status = HAL_ERROR;
2659 }
2660
2661 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2662 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
2663 (Length > hdfsdm_filter->InjConvRemaining))
2664 {
2665 status = HAL_ERROR;
2666 }
2667 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2668 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
2669 {
2670 status = HAL_ERROR;
2671 }
2672
2673 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2674 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
2675 {
2676
2677 hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
2678 hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
2679 hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
2680 DFSDM_DMAInjectedHalfConvCplt : NULL;
2681
2682
2683 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
2684 (uint32_t) pData, Length) != HAL_OK)
2685 {
2686
2687 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2688 status = HAL_ERROR;
2689 }
2690 else
2691 {
2692
2693 DFSDM_InjConvStart(hdfsdm_filter);
2694 }
2695 }
2696 else
2697 {
2698 status = HAL_ERROR;
2699 }
2700
2701 return status;
2702 }
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2717 int16_t *pData,
2718 uint32_t Length)
2719 {
2720 HAL_StatusTypeDef status = HAL_OK;
2721
2722
2723 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2724
2725
2726 if((pData == NULL) || (Length == 0U))
2727 {
2728 status = HAL_ERROR;
2729 }
2730
2731 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
2732 {
2733 status = HAL_ERROR;
2734 }
2735
2736 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2737 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
2738 (Length > hdfsdm_filter->InjConvRemaining))
2739 {
2740 status = HAL_ERROR;
2741 }
2742 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2743 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
2744 {
2745 status = HAL_ERROR;
2746 }
2747
2748 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2749 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
2750 {
2751
2752 hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
2753 hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
2754 hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
2755 DFSDM_DMAInjectedHalfConvCplt : NULL;
2756
2757
2758 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \
2759 (uint32_t) pData, Length) != HAL_OK)
2760 {
2761
2762 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2763 status = HAL_ERROR;
2764 }
2765 else
2766 {
2767
2768 DFSDM_InjConvStart(hdfsdm_filter);
2769 }
2770 }
2771 else
2772 {
2773 status = HAL_ERROR;
2774 }
2775
2776 return status;
2777 }
2778
2779
2780
2781
2782
2783
2784
2785 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2786 {
2787 HAL_StatusTypeDef status = HAL_OK;
2788
2789
2790 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2791
2792
2793 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
2794 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2795 {
2796
2797 status = HAL_ERROR;
2798 }
2799 else
2800 {
2801
2802 if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)
2803 {
2804
2805 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2806 status = HAL_ERROR;
2807 }
2808 else
2809 {
2810
2811 DFSDM_InjConvStop(hdfsdm_filter);
2812 }
2813 }
2814
2815 return status;
2816 }
2817
2818
2819
2820
2821
2822
2823
2824 int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2825 uint32_t *Channel)
2826 {
2827 uint32_t reg;
2828 int32_t value;
2829
2830
2831 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2832 assert_param(Channel != (void *)0);
2833
2834
2835 reg = hdfsdm_filter->Instance->FLTJDATAR;
2836
2837
2838 *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
2839
2840
2841 reg &= DFSDM_FLTJDATAR_JDATA;
2842 value = ((int32_t)reg) / 256;
2843
2844
2845 return value;
2846 }
2847
2848
2849
2850
2851
2852
2853
2854 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2855 const DFSDM_Filter_AwdParamTypeDef *awdParam)
2856 {
2857 HAL_StatusTypeDef status = HAL_OK;
2858
2859
2860 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2861 assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));
2862 assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));
2863 assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));
2864 assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
2865 assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
2866 assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
2867
2868
2869 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
2870 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
2871 {
2872
2873 status = HAL_ERROR;
2874 }
2875 else
2876 {
2877
2878 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
2879 hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;
2880
2881
2882 hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
2883 hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \
2884 awdParam->HighBreakSignal);
2885 hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
2886 hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \
2887 awdParam->LowBreakSignal);
2888
2889
2890 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
2891 hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \
2892 DFSDM_FLTCR2_AWDIE);
2893 }
2894
2895 return status;
2896 }
2897
2898
2899
2900
2901
2902
2903 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2904 {
2905 HAL_StatusTypeDef status = HAL_OK;
2906
2907
2908 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2909
2910
2911 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
2912 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
2913 {
2914
2915 status = HAL_ERROR;
2916 }
2917 else
2918 {
2919
2920 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);
2921
2922
2923 hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
2924
2925
2926 hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
2927 hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
2928
2929
2930 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
2931 }
2932
2933 return status;
2934 }
2935
2936
2937
2938
2939
2940
2941
2942
2943 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2944 uint32_t Channel)
2945 {
2946 HAL_StatusTypeDef status = HAL_OK;
2947
2948
2949 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2950 assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
2951
2952
2953 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
2954 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
2955 {
2956
2957 status = HAL_ERROR;
2958 }
2959 else
2960 {
2961
2962 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
2963 hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);
2964 }
2965
2966 return status;
2967 }
2968
2969
2970
2971
2972
2973
2974 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2975 {
2976 HAL_StatusTypeDef status = HAL_OK;
2977 __IO uint32_t reg1;
2978 __IO uint32_t reg2;
2979
2980
2981 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2982
2983
2984 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
2985 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
2986 {
2987
2988 status = HAL_ERROR;
2989 }
2990 else
2991 {
2992
2993 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
2994
2995
2996 reg1 = hdfsdm_filter->Instance->FLTEXMAX;
2997 reg2 = hdfsdm_filter->Instance->FLTEXMIN;
2998 UNUSED(reg1);
2999 UNUSED(reg2);
3000 }
3001
3002 return status;
3003 }
3004
3005
3006
3007
3008
3009
3010
3011
3012 int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
3013 uint32_t *Channel)
3014 {
3015 uint32_t reg;
3016 int32_t value;
3017
3018
3019 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
3020 assert_param(Channel != (void *)0);
3021
3022
3023 reg = hdfsdm_filter->Instance->FLTEXMAX;
3024
3025
3026 *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
3027
3028
3029 reg &= DFSDM_FLTEXMAX_EXMAX;
3030 value = ((int32_t)reg) / 256;
3031
3032
3033 return value;
3034 }
3035
3036
3037
3038
3039
3040
3041
3042
3043 int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
3044 uint32_t *Channel)
3045 {
3046 uint32_t reg;
3047 int32_t value;
3048
3049
3050 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
3051 assert_param(Channel != (void *)0);
3052
3053
3054 reg = hdfsdm_filter->Instance->FLTEXMIN;
3055
3056
3057 *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
3058
3059
3060 reg &= DFSDM_FLTEXMIN_EXMIN;
3061 value = ((int32_t)reg) / 256;
3062
3063
3064 return value;
3065 }
3066
3067
3068
3069
3070
3071
3072
3073 uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3074 {
3075 uint32_t reg;
3076 uint32_t value;
3077
3078
3079 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
3080
3081
3082 reg = hdfsdm_filter->Instance->FLTCNVTIMR;
3083
3084
3085 value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos);
3086
3087
3088 return value;
3089 }
3090
3091
3092
3093
3094
3095
3096 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3097 {
3098 DFSDM_Channel_HandleTypeDef **channelHandleTable;
3099 const DFSDM_Filter_TypeDef *filter0Instance;
3100 uint32_t channelNumber;
3101
3102
3103 const uint32_t temp_fltisr = hdfsdm_filter->Instance->FLTISR;
3104 const uint32_t temp_fltcr2 = hdfsdm_filter->Instance->FLTCR2;
3105
3106 #if defined(DFSDM2_Channel0)
3107 if (IS_DFSDM1_FILTER_INSTANCE(hdfsdm_filter->Instance))
3108 {
3109 channelHandleTable = a_dfsdm1ChannelHandle;
3110 filter0Instance = DFSDM1_Filter0;
3111 channelNumber = DFSDM1_CHANNEL_NUMBER;
3112 }
3113 else
3114 {
3115 channelHandleTable = a_dfsdm2ChannelHandle;
3116 filter0Instance = DFSDM2_Filter0;
3117 channelNumber = DFSDM2_CHANNEL_NUMBER;
3118 }
3119 #else
3120 channelHandleTable = a_dfsdm1ChannelHandle;
3121 filter0Instance = DFSDM1_Filter0;
3122 channelNumber = DFSDM1_CHANNEL_NUMBER;
3123 #endif
3124
3125
3126 if(((temp_fltisr & DFSDM_FLTISR_ROVRF) != 0U) && \
3127 ((temp_fltcr2 & DFSDM_FLTCR2_ROVRIE) != 0U))
3128 {
3129
3130 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
3131
3132
3133 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
3134
3135
3136 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3137 hdfsdm_filter->ErrorCallback(hdfsdm_filter);
3138 #else
3139 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
3140 #endif
3141 }
3142
3143 else if(((temp_fltisr & DFSDM_FLTISR_JOVRF) != 0U) && \
3144 ((temp_fltcr2 & DFSDM_FLTCR2_JOVRIE) != 0U))
3145 {
3146
3147 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
3148
3149
3150 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
3151
3152
3153 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3154 hdfsdm_filter->ErrorCallback(hdfsdm_filter);
3155 #else
3156 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
3157 #endif
3158 }
3159
3160 else if(((temp_fltisr & DFSDM_FLTISR_REOCF) != 0U) && \
3161 ((temp_fltcr2 & DFSDM_FLTCR2_REOCIE) != 0U))
3162 {
3163
3164 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3165 hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
3166 #else
3167 HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
3168 #endif
3169
3170
3171 if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
3172 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
3173 {
3174
3175 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
3176
3177
3178 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
3179 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
3180 }
3181 }
3182
3183 else if(((temp_fltisr & DFSDM_FLTISR_JEOCF) != 0U) && \
3184 ((temp_fltcr2 & DFSDM_FLTCR2_JEOCIE) != 0U))
3185 {
3186
3187 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3188 hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
3189 #else
3190 HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
3191 #endif
3192
3193
3194 hdfsdm_filter->InjConvRemaining--;
3195 if(hdfsdm_filter->InjConvRemaining == 0U)
3196 {
3197
3198 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
3199 {
3200
3201 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);
3202
3203
3204 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
3205 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
3206 }
3207
3208 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
3209 hdfsdm_filter->InjectedChannelsNbr : 1U;
3210 }
3211 }
3212
3213 else if(((temp_fltisr & DFSDM_FLTISR_AWDF) != 0U) && \
3214 ((temp_fltcr2 & DFSDM_FLTCR2_AWDIE) != 0U))
3215 {
3216 uint32_t reg;
3217 uint32_t threshold;
3218 uint32_t channel = 0;
3219
3220
3221 reg = hdfsdm_filter->Instance->FLTAWSR;
3222 threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
3223 if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
3224 {
3225 reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos;
3226 }
3227 while (((reg & 1U) == 0U) && (channel < (channelNumber - 1U)))
3228 {
3229 channel++;
3230 reg = reg >> 1;
3231 }
3232
3233 hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
3234 (1UL << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \
3235 (1UL << channel);
3236
3237
3238 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3239 hdfsdm_filter->AwdCallback(hdfsdm_filter, channel, threshold);
3240 #else
3241 HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
3242 #endif
3243 }
3244
3245 else if((hdfsdm_filter->Instance == filter0Instance) && \
3246 ((temp_fltisr & DFSDM_FLTISR_CKABF) != 0U) && \
3247 ((temp_fltcr2 & DFSDM_FLTCR2_CKABIE) != 0U))
3248 {
3249 uint32_t reg;
3250 uint32_t channel = 0;
3251
3252 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
3253
3254 while (channel < channelNumber)
3255 {
3256
3257 if (((reg & 1U) != 0U) && (channelHandleTable[channel] != NULL))
3258 {
3259
3260 if ((channelHandleTable[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)
3261 {
3262
3263 hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
3264
3265
3266 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3267 channelHandleTable[channel]->CkabCallback(channelHandleTable[channel]);
3268 #else
3269 HAL_DFSDM_ChannelCkabCallback(channelHandleTable[channel]);
3270 #endif
3271 }
3272 }
3273 channel++;
3274 reg = reg >> 1;
3275 }
3276 }
3277
3278 else if((hdfsdm_filter->Instance == filter0Instance) && \
3279 ((temp_fltisr & DFSDM_FLTISR_SCDF) != 0U) && \
3280 ((temp_fltcr2 & DFSDM_FLTCR2_SCDIE) != 0U))
3281 {
3282 uint32_t reg;
3283 uint32_t channel = 0;
3284
3285
3286 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
3287 while (((reg & 1U) == 0U) && (channel < (channelNumber - 1U)))
3288 {
3289 channel++;
3290 reg = reg >> 1;
3291 }
3292
3293
3294 hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
3295
3296
3297 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3298 channelHandleTable[channel]->ScdCallback(channelHandleTable[channel]);
3299 #else
3300 HAL_DFSDM_ChannelScdCallback(channelHandleTable[channel]);
3301 #endif
3302 }
3303 }
3304
3305
3306
3307
3308
3309
3310
3311
3312 __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3313 {
3314
3315 UNUSED(hdfsdm_filter);
3316
3317
3318
3319
3320 }
3321
3322
3323
3324
3325
3326
3327 __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3328 {
3329
3330 UNUSED(hdfsdm_filter);
3331
3332
3333
3334
3335 }
3336
3337
3338
3339
3340
3341
3342
3343
3344 __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3345 {
3346
3347 UNUSED(hdfsdm_filter);
3348
3349
3350
3351
3352 }
3353
3354
3355
3356
3357
3358
3359 __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3360 {
3361
3362 UNUSED(hdfsdm_filter);
3363
3364
3365
3366
3367 }
3368
3369
3370
3371
3372
3373
3374
3375
3376 __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
3377 uint32_t Channel, uint32_t Threshold)
3378 {
3379
3380 UNUSED(hdfsdm_filter);
3381 UNUSED(Channel);
3382 UNUSED(Threshold);
3383
3384
3385
3386
3387 }
3388
3389
3390
3391
3392
3393
3394 __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3395 {
3396
3397 UNUSED(hdfsdm_filter);
3398
3399
3400
3401
3402 }
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3429 {
3430
3431 return hdfsdm_filter->State;
3432 }
3433
3434
3435
3436
3437
3438
3439 uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3440 {
3441 return hdfsdm_filter->ErrorCode;
3442 }
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
3464 {
3465
3466 DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
3467
3468
3469 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3470 hdfsdm_filter->RegConvHalfCpltCallback(hdfsdm_filter);
3471 #else
3472 HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
3473 #endif
3474 }
3475
3476
3477
3478
3479
3480
3481 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
3482 {
3483
3484 DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
3485
3486
3487 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3488 hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
3489 #else
3490 HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
3491 #endif
3492 }
3493
3494
3495
3496
3497
3498
3499 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
3500 {
3501
3502 DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
3503
3504
3505 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3506 hdfsdm_filter->InjConvHalfCpltCallback(hdfsdm_filter);
3507 #else
3508 HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
3509 #endif
3510 }
3511
3512
3513
3514
3515
3516
3517 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
3518 {
3519
3520 DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
3521
3522
3523 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3524 hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
3525 #else
3526 HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
3527 #endif
3528 }
3529
3530
3531
3532
3533
3534
3535 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
3536 {
3537
3538 DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
3539
3540
3541 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
3542
3543
3544 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3545 hdfsdm_filter->ErrorCallback(hdfsdm_filter);
3546 #else
3547 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
3548 #endif
3549 }
3550
3551
3552
3553
3554
3555
3556 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
3557 {
3558 uint32_t nbChannels = 0;
3559 uint32_t tmp;
3560
3561
3562 tmp = (uint32_t)(Channels & DFSDM_LSB_MASK);
3563 while(tmp != 0U)
3564 {
3565 if((tmp & 1U) != 0U)
3566 {
3567 nbChannels++;
3568 }
3569 tmp = (uint32_t)(tmp >> 1);
3570 }
3571 return nbChannels;
3572 }
3573
3574
3575
3576
3577
3578
3579 static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef* Instance)
3580 {
3581 uint32_t channel;
3582
3583
3584 if(Instance == DFSDM1_Channel0)
3585 {
3586 channel = 0;
3587 }
3588 #if defined(DFSDM2_Channel0)
3589 else if (Instance == DFSDM2_Channel0)
3590 {
3591 channel = 0;
3592 }
3593 else if (Instance == DFSDM2_Channel1)
3594 {
3595 channel = 1;
3596 }
3597 #endif
3598 else if(Instance == DFSDM1_Channel1)
3599 {
3600 channel = 1;
3601 }
3602 else if(Instance == DFSDM1_Channel2)
3603 {
3604 channel = 2;
3605 }
3606 else if(Instance == DFSDM1_Channel3)
3607 {
3608 channel = 3;
3609 }
3610 else if(Instance == DFSDM1_Channel4)
3611 {
3612 channel = 4;
3613 }
3614 else if(Instance == DFSDM1_Channel5)
3615 {
3616 channel = 5;
3617 }
3618 else if(Instance == DFSDM1_Channel6)
3619 {
3620 channel = 6;
3621 }
3622 else
3623 {
3624 channel = 7;
3625 }
3626
3627 return channel;
3628 }
3629
3630
3631
3632
3633
3634
3635 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3636 {
3637
3638 if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)
3639 {
3640
3641 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
3642 }
3643 else
3644 {
3645
3646 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
3647
3648
3649 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
3650
3651
3652 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
3653
3654
3655 if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
3656 {
3657 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
3658 {
3659 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
3660 }
3661
3662 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
3663 hdfsdm_filter->InjectedChannelsNbr : 1U;
3664 }
3665 }
3666
3667 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
3668 HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
3669 }
3670
3671
3672
3673
3674
3675
3676 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3677 {
3678
3679 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
3680
3681
3682 if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)
3683 {
3684 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
3685 }
3686
3687
3688 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
3689
3690
3691 if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
3692 {
3693 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
3694 {
3695 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
3696 }
3697
3698 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
3699 hdfsdm_filter->InjectedChannelsNbr : 1U;
3700 }
3701
3702
3703 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
3704 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
3705 }
3706
3707
3708
3709
3710
3711
3712 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3713 {
3714
3715 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
3716 {
3717
3718 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
3719 }
3720 else
3721 {
3722
3723 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
3724
3725 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
3726 {
3727
3728 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;
3729 }
3730 else
3731 {
3732
3733 hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
3734 }
3735
3736
3737 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
3738
3739
3740 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
3741 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
3742 {
3743 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
3744 }
3745 }
3746
3747 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
3748 HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;
3749 }
3750
3751
3752
3753
3754
3755
3756 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3757 {
3758
3759 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
3760
3761
3762 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
3763 {
3764 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);
3765 }
3766 else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)
3767 {
3768
3769 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
3770 }
3771 else
3772 {
3773
3774 }
3775
3776
3777 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
3778
3779
3780 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
3781 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
3782 {
3783 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
3784 }
3785
3786
3787 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
3788 hdfsdm_filter->InjectedChannelsNbr : 1U;
3789
3790
3791 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
3792 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
3793 }
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804 #endif
3805
3806
3807
3808
3809