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File indexing completed on 2025-05-11 08:23:06 

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_eth_ex.c
0004   * @author  MCD Application Team
0005   * @brief   ETH HAL Extended module driver.
0006   *
0007   ******************************************************************************
0008   * @attention
0009   *
0010   * Copyright (c) 2017 STMicroelectronics.
0011   * All rights reserved.
0012   *
0013   * This software is licensed under terms that can be found in the LICENSE file
0014   * in the root directory of this software component.
0015   * If no LICENSE file comes with this software, it is provided AS-IS.
0016   *
0017   ******************************************************************************
0018   */
0019 
0020 /* Includes ------------------------------------------------------------------*/
0021 #include "stm32h7xx_hal.h"
0022 
0023 /** @addtogroup STM32H7xx_HAL_Driver
0024   * @{
0025   */
0026 
0027 #ifdef HAL_ETH_LEGACY_MODULE_ENABLED
0028 
0029 #if defined(ETH)
0030 
0031 /** @defgroup ETHEx ETHEx
0032   * @ingroup RTEMSBSPsARMSTM32H7
0033   * @brief ETH HAL Extended module driver
0034   * @{
0035   */
0036 
0037 
0038 /* Private typedef -----------------------------------------------------------*/
0039 /* Private define ------------------------------------------------------------*/
0040 /** @defgroup ETHEx_Private_Constants ETHEx Private Constants
0041   * @ingroup RTEMSBSPsARMSTM32H7
0042   * @{
0043   */
0044 #define ETH_MACL4CR_MASK     (ETH_MACL3L4CR_L4PEN | ETH_MACL3L4CR_L4SPM | \
0045                               ETH_MACL3L4CR_L4SPIM | ETH_MACL3L4CR_L4DPM | \
0046                               ETH_MACL3L4CR_L4DPIM)
0047 
0048 #define ETH_MACL3CR_MASK     (ETH_MACL3L4CR_L3PEN | ETH_MACL3L4CR_L3SAM | \
0049                               ETH_MACL3L4CR_L3SAIM | ETH_MACL3L4CR_L3DAM | \
0050                               ETH_MACL3L4CR_L3DAIM | ETH_MACL3L4CR_L3HSBM | \
0051                               ETH_MACL3L4CR_L3HDBM)
0052 
0053 #define ETH_MACRXVLAN_MASK (ETH_MACVTR_EIVLRXS | ETH_MACVTR_EIVLS | \
0054                             ETH_MACVTR_ERIVLT | ETH_MACVTR_EDVLP | \
0055                             ETH_MACVTR_VTHM | ETH_MACVTR_EVLRXS | \
0056                             ETH_MACVTR_EVLS | ETH_MACVTR_DOVLTC | \
0057                             ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL | \
0058                             ETH_MACVTR_VTIM | ETH_MACVTR_ETV)
0059 
0060 #define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
0061                             ETH_MACVIR_VLP | ETH_MACVIR_VLC)
0062 /**
0063   * @}
0064   */
0065 
0066 /* Private macros ------------------------------------------------------------*/
0067 /* Private function prototypes -----------------------------------------------*/
0068 /* Exported functions ---------------------------------------------------------*/
0069 /** @defgroup ETHEx_Exported_Functions ETH Extended Exported Functions
0070   * @ingroup RTEMSBSPsARMSTM32H7
0071   * @{
0072   */
0073 
0074 /** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions
0075   * @ingroup RTEMSBSPsARMSTM32H7
0076   * @brief    Extended features functions
0077  *
0078 @verbatim
0079  ===============================================================================
0080                       ##### Extended features functions #####
0081  ===============================================================================
0082     [..] This section provides functions allowing to:
0083       (+) Configure ARP offload module
0084       (+) Configure L3 and L4 filters
0085       (+) Configure Extended VLAN features
0086       (+) Configure Energy Efficient Ethernet module
0087 
0088 @endverbatim
0089   * @{
0090   */
0091 
0092 /**
0093   * @brief  Enables ARP Offload.
0094   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0095   *         the configuration information for ETHERNET module
0096   * @retval None
0097   */
0098 void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
0099 {
0100   SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
0101 }
0102 
0103 /**
0104   * @brief  Disables ARP Offload.
0105   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0106   *         the configuration information for ETHERNET module
0107   * @retval None
0108   */
0109 void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth)
0110 {
0111   CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
0112 }
0113 
0114 /**
0115   * @brief  Set the ARP Match IP address
0116   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0117   *         the configuration information for ETHERNET module
0118   * @param  IpAddress: IP Address to be matched for incoming ARP requests
0119   * @retval None
0120   */
0121 void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
0122 {
0123   WRITE_REG(heth->Instance->MACARPAR, IpAddress);
0124 }
0125 
0126 /**
0127   * @brief  Configures the L4 Filter, this function allow to:
0128   *         set the layer 4 protocol to be matched (TCP or UDP)
0129   *         enable/disable L4 source/destination port perfect/inverse match.
0130   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0131   *         the configuration information for ETHERNET module
0132   * @param  Filter: L4 filter to configured, this parameter must be one of the following
0133   *           ETH_L4_FILTER_0
0134   *           ETH_L4_FILTER_1
0135   * @param  pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
0136   *         that contains L4 filter configuration.
0137   * @retval HAL status
0138   */
0139 HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter , ETH_L4FilterConfigTypeDef *pL4FilterConfig)
0140 {
0141   __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
0142 
0143   if(pL4FilterConfig == NULL)
0144   {
0145     return HAL_ERROR;
0146   }
0147 
0148   /* Write configuration to (MACL3L4C0R + filter )register */
0149   MODIFY_REG(*configreg, ETH_MACL4CR_MASK ,(pL4FilterConfig->Protocol |
0150                                             pL4FilterConfig->SrcPortFilterMatch |
0151                                               pL4FilterConfig->DestPortFilterMatch));
0152 
0153   configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
0154 
0155   /* Write configuration to (MACL4A0R + filter )register */
0156   MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP) , (pL4FilterConfig->SourcePort |
0157                                                                                                                   (pL4FilterConfig->DestinationPort << 16)));
0158 
0159   /* Enable L4 filter */
0160   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
0161 
0162   return HAL_OK;
0163 }
0164 
0165 /**
0166   * @brief  Configures the L4 Filter, this function allow to:
0167   *         set the layer 4 protocol to be matched (TCP or UDP)
0168   *         enable/disable L4 source/destination port perfect/inverse match.
0169   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0170   *         the configuration information for ETHERNET module
0171   * @param  Filter: L4 filter to configured, this parameter must be one of the following
0172   *           ETH_L4_FILTER_0
0173   *           ETH_L4_FILTER_1
0174   * @param  pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
0175   *         that contains L4 filter configuration.
0176   * @retval HAL status
0177   */
0178 HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
0179 {
0180   if(pL4FilterConfig == NULL)
0181   {
0182     return HAL_ERROR;
0183   }
0184 
0185   /* Get configuration to (MACL3L4C0R + filter )register */
0186   pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L4PEN);
0187   pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
0188   pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
0189 
0190   /* Get configuration to (MACL3L4C0R + filter )register */
0191   pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4DP) >> 16);
0192   pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP);
0193 
0194   return HAL_OK;
0195 }
0196 
0197 /**
0198   * @brief  Configures the L3 Filter, this function allow to:
0199   *         set the layer 3 protocol to be matched (IPv4 or IPv6)
0200   *         enable/disable L3 source/destination port perfect/inverse match.
0201   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0202   *         the configuration information for ETHERNET module
0203   * @param  Filter: L3 filter to configured, this parameter must be one of the following
0204   *           ETH_L3_FILTER_0
0205   *           ETH_L3_FILTER_1
0206   * @param  pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
0207   *         that contains L3 filter configuration.
0208   * @retval HAL status
0209   */
0210 HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
0211 {
0212   __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
0213 
0214   if(pL3FilterConfig == NULL)
0215   {
0216     return HAL_ERROR;
0217   }
0218 
0219   /* Write configuration to (MACL3L4C0R + filter )register */
0220   MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
0221                                             pL3FilterConfig->SrcAddrFilterMatch |
0222                                               pL3FilterConfig->DestAddrFilterMatch |
0223                                                 (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
0224                                                   (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
0225 
0226   /* Check if IPv6 protocol is selected */
0227   if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
0228   {
0229     /* Set the IPv6 address match */
0230     /* Set Bits[31:0] of 128-bit IP addr */
0231     *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0];
0232     /* Set Bits[63:32] of 128-bit IP addr */
0233     *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1];
0234     /* update Bits[95:64] of 128-bit IP addr */
0235     *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2];
0236     /* update Bits[127:96] of 128-bit IP addr */
0237     *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3];
0238   }
0239   else /* IPv4 protocol is selected */
0240   {
0241     /* Set the IPv4 source address match */
0242     *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr;
0243     /* Set the IPv4 destination address match */
0244     *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr;
0245   }
0246 
0247   return HAL_OK;
0248 }
0249 
0250 /**
0251   * @brief  Configures the L3 Filter, this function allow to:
0252   *         set the layer 3 protocol to be matched (IPv4 or IPv6)
0253   *         enable/disable L3 source/destination port perfect/inverse match.
0254   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0255   *         the configuration information for ETHERNET module
0256   * @param  Filter: L3 filter to configured, this parameter must be one of the following
0257   *           ETH_L3_FILTER_0
0258   *           ETH_L3_FILTER_1
0259   * @param  pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
0260   *         that will contain the L3 filter configuration.
0261   * @retval HAL status
0262   */
0263 HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
0264 {
0265   if(pL3FilterConfig == NULL)
0266   {
0267     return HAL_ERROR;
0268   }
0269 
0270   pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3PEN);
0271   pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
0272   pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
0273   pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HSBM) >> 6);
0274   pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HDBM) >> 11);
0275 
0276   if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
0277   {
0278     pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
0279     pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
0280     pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter));
0281     pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter));
0282   }
0283   else
0284   {
0285     pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
0286     pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
0287   }
0288 
0289   return HAL_OK;
0290 }
0291 
0292 /**
0293   * @brief  Enables L3 and L4 filtering process.
0294   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0295   *         the configuration information for ETHERNET module
0296   * @retval None.
0297   */
0298 void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth)
0299 {
0300   /* Enable L3/L4 filter */
0301   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
0302 }
0303 
0304 /**
0305   * @brief  Disables L3 and L4 filtering process.
0306   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0307   *         the configuration information for ETHERNET module
0308   * @retval None.
0309   */
0310 void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
0311 {
0312   /* Disable L3/L4 filter */
0313   CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
0314 }
0315 
0316 /**
0317   * @brief  Get the VLAN Configuration for Receive Packets.
0318   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0319   *         the configuration information for ETHERNET module
0320   * @param  pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
0321   *         that will contain the VLAN filter configuration.
0322   * @retval HAL status
0323   */
0324 HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
0325 {
0326   if(pVlanConfig == NULL)
0327   {
0328     return HAL_ERROR;
0329   }
0330 
0331   pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
0332   pVlanConfig->StripInnerVLANTag  = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
0333   pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
0334   pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
0335   pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
0336   pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
0337   pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
0338   pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
0339   pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U) ? DISABLE : ENABLE;
0340 
0341   return HAL_OK;
0342 }
0343 
0344 /**
0345   * @brief  Set the VLAN Configuration for Receive Packets.
0346   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0347   *         the configuration information for ETHERNET module
0348   * @param  pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
0349   *         that contains VLAN filter configuration.
0350   * @retval HAL status
0351   */
0352 HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
0353 {
0354   if(pVlanConfig == NULL)
0355   {
0356     return HAL_ERROR;
0357   }
0358 
0359   /* Write config to MACVTR */
0360   MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) |
0361                                                           pVlanConfig->StripInnerVLANTag |
0362                                                             ((uint32_t)pVlanConfig->InnerVLANTag << 27) |
0363                                                               ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
0364                                                                 ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
0365                                                                   ((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
0366                                                                     pVlanConfig->StripVLANTag |
0367                                                                       pVlanConfig->VLANTypeCheck |
0368                                                                         ((uint32_t)pVlanConfig->VLANTagInverceMatch << 17)));
0369 
0370   return HAL_OK;
0371 }
0372 
0373 /**
0374   * @brief  Set the VLAN Hash Table
0375   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0376   *         the configuration information for ETHERNET module
0377   * @param  VLANHashTable: VLAN hash table 16 bit value
0378   * @retval None
0379   */
0380 void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
0381 {
0382   MODIFY_REG(heth->Instance->MACVHTR, ETH_MACVHTR_VLHT, VLANHashTable);
0383 }
0384 
0385 /**
0386   * @brief  Get the VLAN Configuration for Transmit Packets.
0387   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0388   *         the configuration information for ETHERNET module
0389   * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
0390   *                 ETH_OUTER_TX_VLANTAG
0391   *                 ETH_INNER_TX_VLANTAG
0392   * @param  pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
0393   *         that will contain the Tx VLAN filter configuration.
0394   * @retval HAL Status.
0395   */
0396 HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
0397 {
0398   if (pVlanConfig == NULL)
0399   {
0400     return HAL_ERROR;
0401   }
0402 
0403   if(VLANTag == ETH_INNER_TX_VLANTAG)
0404   {
0405     pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
0406     pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
0407     pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACIVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
0408   }
0409   else
0410   {
0411     pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
0412     pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
0413     pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
0414   }
0415 
0416   return HAL_OK;;
0417 }
0418 
0419 /**
0420   * @brief  Set the VLAN Configuration for Transmit Packets.
0421   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0422   *         the configuration information for ETHERNET module
0423   * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
0424   *                 ETH_OUTER_TX_VLANTAG
0425   *                 ETH_INNER_TX_VLANTAG
0426   * @param  pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
0427   *         that contains Tx VLAN filter configuration.
0428   * @retval HAL Status
0429   */
0430 HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
0431 {
0432   if(VLANTag == ETH_INNER_TX_VLANTAG)
0433   {
0434     MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
0435                                                             ((uint32_t)pVlanConfig->SVLANType << 19) |
0436                                                               pVlanConfig->VLANTagControl));
0437     /* Enable Double VLAN processing */
0438     SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
0439   }
0440   else
0441   {
0442     MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
0443                                                             ((uint32_t)pVlanConfig->SVLANType << 19) |
0444                                                               pVlanConfig->VLANTagControl));
0445   }
0446 
0447   return HAL_OK;
0448 }
0449 
0450 /**
0451   * @brief  Set the VLAN Tag Identifier for Transmit Packets.
0452   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0453   *         the configuration information for ETHERNET module
0454   * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
0455   *                 ETH_OUTER_TX_VLANTAG
0456   *                 ETH_INNER_TX_VLANTAG
0457   * @param  VLANIdentifier: VLAN Identifier 16 bit value
0458   * @retval None
0459   */
0460 void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier)
0461 {
0462   if(VLANTag == ETH_INNER_TX_VLANTAG)
0463   {
0464     MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier);
0465   }
0466   else
0467   {
0468     MODIFY_REG(heth->Instance->MACVIR, ETH_MACVIR_VLT, VLANIdentifier);
0469   }
0470 }
0471 
0472 /**
0473   * @brief  Enables the VLAN Tag Filtering process.
0474   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0475   *         the configuration information for ETHERNET module
0476   * @retval None.
0477   */
0478 void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth)
0479 {
0480   /* Enable VLAN processing */
0481   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
0482 }
0483 
0484 /**
0485   * @brief  Disables the VLAN Tag Filtering process.
0486   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0487   *         the configuration information for ETHERNET module
0488   * @retval None.
0489   */
0490 void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth)
0491 {
0492   /* Disable VLAN processing */
0493   CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
0494 }
0495 
0496 /**
0497   * @brief  Enters the Low Power Idle (LPI) mode
0498   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0499   *         the configuration information for ETHERNET module
0500   * @param  TxAutomate: Enable/Disable automate enter/exit LPI mode.
0501   * @param  TxClockStop: Enable/Disable Tx clock stop in LPI mode.
0502   * @retval None
0503   */
0504 void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
0505 {
0506   /* Enable LPI Interrupts */
0507   __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE);
0508 
0509   /* Write to LPI Control register: Enter low power mode */
0510   MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), (((uint32_t)TxAutomate << 19) |
0511                                                                                                        ((uint32_t)TxClockStop << 21) |
0512                                                                                                          ETH_MACLCSR_LPIEN));
0513 }
0514 
0515 /**
0516   * @brief  Exits the Low Power Idle (LPI) mode.
0517   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0518   *         the configuration information for ETHERNET module
0519   * @retval None
0520   */
0521 void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
0522 {
0523   /* Clear the LPI Config and exit low power mode */
0524   CLEAR_BIT(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE));
0525 
0526   /* Enable LPI Interrupts */
0527   __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
0528 }
0529 
0530 
0531 /**
0532   * @brief  Returns the ETH MAC LPI event
0533   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
0534   *         the configuration information for ETHERNET module
0535   * @retval ETH MAC WakeUp event
0536   */
0537 uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
0538 {
0539   return heth->MACLPIEvent;
0540 }
0541 
0542 /**
0543   * @}
0544   */
0545 
0546 /**
0547   * @}
0548   */
0549 
0550 /**
0551   * @}
0552   */
0553 
0554 #endif /* ETH */
0555 
0556 #endif /* HAL_ETH_LEGACY_MODULE_ENABLED*/
0557 
0558 /**
0559   * @}
0560   */
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