stm/stm32h7b3i-dk/system_stm32h7xx.c

0001 /**
0002   ******************************************************************************
0003   * @file    system_stm32h7xx.c
0004   * @author  MCD Application Team
0005   * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
0006   *
0007   *   This file provides two functions and one global variable to be called from
0008   *   user application:
0009   *      - SystemInit(): This function is called at startup just after reset and
0010   *                      before branch to main program. This call is made inside
0011   *                      the "startup_stm32h7xx.s" file.
0012   *
0013   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
0014   *                                  by the user application to setup the SysTick
0015   *                                  timer or configure other parameters.
0016   *
0017   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
0018   *                                 be called whenever the core clock is changed
0019   *                                 during program execution.
0020   *
0021   *
0022   ******************************************************************************
0023   * @attention
0024   *
0025   * Copyright (c) 2018 STMicroelectronics.
0026   * All rights reserved.
0027   *
0028   * This software is licensed under terms that can be found in the LICENSE file
0029   * in the root directory of this software component.
0030   * If no LICENSE file comes with this software, it is provided AS-IS.
0031   *
0032   ******************************************************************************
0033   */
0034
0035 /** @addtogroup CMSIS
0036   * @{
0037   */
0038
0039 /** @addtogroup stm32h7xx_system
0040   * @{
0041   */
0042
0043 /** @addtogroup STM32H7xx_System_Private_Includes
0044   * @{
0045   */
0046
0047 #include "stm32h7xx.h"
0048 #include <math.h>
0049 #ifdef __rtems__
0050 #include <bsp/linker-symbols.h>
0051 #include <bspopts.h>
0052
0053 #define HSE_VALUE STM32H7_HSE_FREQUENCY
0054
0055 #endif /* __rtems__ */
0056 #if !defined  (HSE_VALUE)
0057 #define HSE_VALUE    ((uint32_t)24000000) /*!< Value of the External oscillator in Hz */
0058 #endif /* HSE_VALUE */
0059
0060 #if !defined  (CSI_VALUE)
0061   #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
0062 #endif /* CSI_VALUE */
0063
0064 #if !defined  (HSI_VALUE)
0065   #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
0066 #endif /* HSI_VALUE */
0067
0068
0069 /**
0070   * @}
0071   */
0072
0073 /** @addtogroup STM32H7xx_System_Private_TypesDefinitions
0074   * @{
0075   */
0076
0077 /**
0078   * @}
0079   */
0080
0081 /** @addtogroup STM32H7xx_System_Private_Defines
0082   * @{
0083   */
0084
0085 /************************* Miscellaneous Configuration ************************/
0086 /*!< Uncomment the following line if you need to use initialized data in CD domain AHB SRAM */
0087 /* #define DATA_IN_CD_AHB_SRAM */
0088
0089 /*!< Uncomment the following line if you need to relocate your vector Table in
0090      Internal SRAM. */
0091 /* #define VECT_TAB_SRAM */
0092 #define VECT_TAB_OFFSET  0x00000000UL /*!< Vector Table base offset field.
0093                                       This value must be a multiple of 0x200. */
0094 /******************************************************************************/
0095
0096 /**
0097   * @}
0098   */
0099
0100 /** @addtogroup STM32H7xx_System_Private_Macros
0101   * @{
0102   */
0103
0104 /**
0105   * @}
0106   */
0107
0108 /** @addtogroup STM32H7xx_System_Private_Variables
0109   * @{
0110   */
0111   /* This variable is updated in three ways:
0112       1) by calling CMSIS function SystemCoreClockUpdate()
0113       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
0114       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
0115          Note: If you use this function to configure the system clock; then there
0116                is no need to call the 2 first functions listed above, since SystemCoreClock
0117                variable is updated automatically.
0118   */
0119 #ifndef __rtems__
0120   uint32_t SystemCoreClock = 64000000;
0121   uint32_t SystemD2Clock = 64000000;  /* AXI and AHBs Clock frequency */
0122 #else /* __rtems__ */
0123   RTEMS_SECTION(".rtemsstack") uint32_t SystemCoreClock;
0124   RTEMS_SECTION(".rtemsstack") uint32_t SystemD2Clock;
0125 #endif /* __rtems__ */
0126   const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /* CPU Domain Core Prescaler Table */
0127
0128 /**
0129   * @}
0130   */
0131
0132 /** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
0133   * @{
0134   */
0135
0136 /**
0137   * @}
0138   */
0139
0140 /** @addtogroup STM32H7xx_System_Private_Functions
0141   * @{
0142   */
0143
0144 /**
0145   * @brief  Setup the microcontroller system
0146   *         Initialize the FPU setting and  vector table location
0147   *         configuration.
0148   * @param  None
0149   * @retval None
0150   */
0151 void SystemInit (void)
0152 {
0153 #ifdef DATA_IN_CD_AHB_SRAM
0154  __IO uint32_t tmpreg;
0155 #endif /* DATA_IN_CD_AHB_SRAM */
0156
0157   /* FPU settings ------------------------------------------------------------*/
0158   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
0159     SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
0160   #endif
0161   /* Reset the RCC clock configuration to the default reset state ------------*/
0162   /* Set HSION bit */
0163   RCC->CR |= RCC_CR_HSION;
0164
0165   /* Reset CFGR register */
0166   RCC->CFGR = 0x00000000;
0167
0168   /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
0169   RCC->CR &= 0xEAF6ED7FU;
0170
0171   /* Reset CDCFGR1 register */
0172   RCC->CDCFGR1 = 0x00000000;
0173
0174   /* Reset CDCFGR2 register */
0175   RCC->CDCFGR2 = 0x00000000;
0176
0177   /* Reset SRDCFGR register */
0178   RCC->SRDCFGR = 0x00000000;
0179
0180   /* Reset PLLCKSELR register */
0181   RCC->PLLCKSELR = 0x02020200;
0182
0183   /* Reset PLLCFGR register */
0184   RCC->PLLCFGR = 0x01FF0000;
0185   /* Reset PLL1DIVR register */
0186   RCC->PLL1DIVR = 0x01010280;
0187   /* Reset PLL1FRACR register */
0188   RCC->PLL1FRACR = 0x00000000;
0189
0190   /* Reset PLL2DIVR register */
0191   RCC->PLL2DIVR = 0x01010280;
0192
0193   /* Reset PLL2FRACR register */
0194
0195   RCC->PLL2FRACR = 0x00000000;
0196   /* Reset PLL3DIVR register */
0197   RCC->PLL3DIVR = 0x01010280;
0198
0199   /* Reset PLL3FRACR register */
0200   RCC->PLL3FRACR = 0x00000000;
0201
0202   /* Reset HSEBYP bit */
0203   RCC->CR &= 0xFFFBFFFFU;
0204
0205   /* Disable all interrupts */
0206   RCC->CIER = 0x00000000;
0207
0208 #ifdef DATA_IN_CD_AHB_SRAM
0209   /* in case of initialized data in CD AHB SRAM, enable the CD AHB SRAM clock */
0210   RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
0211 #ifndef __rtems__
0212   tmpreg = RCC->AHB2ENR;
0213   (void) tmpreg;
0214 #else /* __rtems__ */
0215   RCC->AHB2ENR;
0216 #endif /* __rtems__ */
0217 #endif /* DATA_IN_CD_AHB_SRAM */
0218
0219 /*
0220    * Disable the FMC bank1 (enabled after reset).
0221    * This, prevents CPU speculation access on this bank which blocks the use of FMC during
0222    * 24us. During this time the others FMC master (such as LTDC) cannot use it!
0223    */
0224   FMC_Bank1_R->BTCR[0] = 0x000030D2;
0225
0226 #ifndef __rtems__
0227   /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
0228 #ifdef VECT_TAB_SRAM
0229   SCB->VTOR = CD_AXISRAM1_BASE  | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal CD AXI-RAM */
0230 #else
0231   SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
0232 #endif
0233 #else /* __rtems__ */
0234   SCB->VTOR = (uint32_t) bsp_start_vector_table_begin;
0235 #endif /* __rtems__ */
0236
0237 }
0238
0239 /**
0240    * @brief  Update SystemCoreClock variable according to Clock Register Values.
0241   *         The SystemCoreClock variable contains the core clock , it can
0242   *         be used by the user application to setup the SysTick timer or configure
0243   *         other parameters.
0244   *
0245   * @note   Each time the core clock changes, this function must be called
0246   *         to update SystemCoreClock variable value. Otherwise, any configuration
0247   *         based on this variable will be incorrect.
0248   *
0249   * @note   - The system frequency computed by this function is not the real
0250   *           frequency in the chip. It is calculated based on the predefined
0251   *           constant and the selected clock source:
0252   *
0253   *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
0254   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
0255   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
0256   *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
0257   *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
0258   *
0259   *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
0260   *             4 MHz) but the real value may vary depending on the variations
0261   *             in voltage and temperature.
0262   *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
0263   *             64 MHz) but the real value may vary depending on the variations
0264   *             in voltage and temperature.
0265   *
0266   *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
0267   *              25 MHz), user has to ensure that HSE_VALUE is same as the real
0268   *              frequency of the crystal used. Otherwise, this function may
0269   *              have wrong result.
0270   *
0271   *         - The result of this function could be not correct when using fractional
0272   *           value for HSE crystal.
0273   * @param  None
0274   * @retval None
0275   */
0276 void SystemCoreClockUpdate (void)
0277 {
0278   uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
0279   float_t fracn1, pllvco;
0280
0281   /* Get SYSCLK source -------------------------------------------------------*/
0282
0283   switch (RCC->CFGR & RCC_CFGR_SWS)
0284   {
0285   case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
0286     SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
0287     break;
0288
0289   case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
0290     SystemCoreClock = CSI_VALUE;
0291     break;
0292
0293   case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
0294     SystemCoreClock = HSE_VALUE;
0295     break;
0296
0297   case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
0298
0299     /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
0300     SYSCLK = PLL_VCO / PLLR
0301     */
0302     pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
0303     pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
0304     pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
0305     fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
0306
0307     if (pllm != 0U)
0308     {
0309       switch (pllsource)
0310       {
0311         case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
0312
0313         hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
0314         pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
0315
0316         break;
0317
0318         case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
0319           pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
0320         break;
0321
0322         case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
0323           pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
0324         break;
0325
0326       default:
0327           pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
0328         break;
0329       }
0330       pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
0331       SystemCoreClock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
0332     }
0333     else
0334     {
0335       SystemCoreClock = 0U;
0336     }
0337     break;
0338
0339   default:
0340     SystemCoreClock = CSI_VALUE;
0341     break;
0342   }
0343
0344   /* Compute SystemClock frequency --------------------------------------------------*/
0345
0346   tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
0347
0348   /* SystemCoreClock frequency : CM7 CPU frequency  */
0349   SystemCoreClock >>= tmp;
0350
0351   /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
0352   SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
0353
0354 }
0355
0356
0357 /**
0358   * @}
0359   */
0360
0361 /**
0362   * @}
0363   */
0364
0365 /**
0366   * @}
0367   */