stm/stm32h757i-eval/system_stm32h7xx.c

0001 /* SPDX-License-Identifier: BSD-3-Clause */
0002 /**
0003   ******************************************************************************
0004   * @file    system_stm32h7xx.c
0005   * @author  MCD Application Team
0006   * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
0007   *
0008   *   This file provides two functions and one global variable to be called from
0009   *   user application:
0010   *      - SystemInit(): This function is called at startup just after reset and
0011   *                      before branch to main program. This call is made inside
0012   *                      the "startup_stm32h7xx.s" file.
0013   *
0014   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
0015   *                                  by the user application to setup the SysTick
0016   *                                  timer or configure other parameters.
0017   *
0018   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
0019   *                                 be called whenever the core clock is changed
0020   *                                 during program execution.
0021   *
0022   *
0023   ******************************************************************************
0024   * @attention
0025   *
0026   * Copyright (c) 2019 STMicroelectronics.
0027   * All rights reserved.
0028   *
0029   * This software is licensed under terms that can be found in the LICENSE file
0030   * in the root directory of this software component.
0031   * If no LICENSE file comes with this software, it is provided AS-IS.
0032   *
0033   ******************************************************************************
0034   */
0035 /*
0036  * RTEMS committer clarification comment on license above:
0037  *
0038  * This file comes from STM32CubeH7 project from its Projects
0039  * subdirectory. There is Templates subdirectory per every supported
0040  * BSP there. The Templates contains the file. In our case the file is
0041  * here:
0042  * https://github.com/STMicroelectronics/STM32CubeH7/blob/master/Projects/STM32H747I-EVAL/Templates/BootCM4_CM7/Common/Src/system_stm32h7xx.c
0043  *
0044  * When we go up in the directory tree starting from the file, we find
0045  * out that the "root directory" in the sense of license claim above is Templates
0046  * directory here:
0047  * https://github.com/STMicroelectronics/STM32CubeH7/tree/master/Projects/STM32H747I-EVAL/Templates
0048  *
0049  * This directory contains LICENSE.md file with a following license text:
0050  *
0051  * Copyright 2019 STMicroelectronics.
0052  * All rights reserved.
0053  *
0054  * Redistribution and use in source and binary forms, with or without modification,
0055  * are permitted provided that the following conditions are met:
0056  *
0057  * 1. Redistributions of source code must retain the above copyright notice, this
0058  * list of conditions and the following disclaimer.
0059  *
0060  * 2. Redistributions in binary form must reproduce the above copyright notice,
0061  * this list of conditions and the following disclaimer in the documentation and/or
0062  * other materials provided with the distribution.
0063  *
0064  * 3. Neither the name of the copyright holder nor the names of its contributors
0065  * may be used to endorse or promote products derived from this software without
0066  * specific prior written permission.
0067  *
0068  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0069  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0070  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0071  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
0072  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0073  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0074  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0075  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0076  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0077  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0078  */
0079
0080 /** @addtogroup CMSIS
0081   * @{
0082   */
0083
0084 /** @addtogroup stm32h7xx_system
0085   * @{
0086   */
0087
0088 /** @addtogroup STM32H7xx_System_Private_Includes
0089   * @{
0090   */
0091
0092 #include "stm32h7xx.h"
0093 #include <math.h>
0094 #ifdef __rtems__
0095 #include <bsp/linker-symbols.h>
0096 #include <bspopts.h>
0097
0098 #define HSE_VALUE STM32H7_HSE_FREQUENCY
0099
0100 #endif /* __rtems__ */
0101 #if !defined  (HSE_VALUE)
0102 #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
0103 #endif /* HSE_VALUE */
0104
0105 #if !defined  (CSI_VALUE)
0106   #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
0107 #endif /* CSI_VALUE */
0108
0109 #if !defined  (HSI_VALUE)
0110   #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
0111 #endif /* HSI_VALUE */
0112
0113 /**
0114   * @}
0115   */
0116
0117 /** @addtogroup STM32H7xx_System_Private_TypesDefinitions
0118   * @{
0119   */
0120
0121 /**
0122   * @}
0123   */
0124
0125 /** @addtogroup STM32H7xx_System_Private_Defines
0126   * @{
0127   */
0128
0129 /************************* Miscellaneous Configuration ************************/
0130 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
0131      on EVAL board as data memory  */
0132 #define DATA_IN_ExtSRAM
0133 #define DATA_IN_ExtSDRAM
0134
0135 /*!< Uncomment the following line if you need to relocate your vector Table in
0136      Internal SRAM. */
0137 /* #define VECT_TAB_SRAM */
0138 #define VECT_TAB_OFFSET  0x00000000UL       /*!< Vector Table base offset field.
0139                                       This value must be a multiple of 0x200. */
0140 /******************************************************************************/
0141
0142 /**
0143   * @}
0144   */
0145
0146 /** @addtogroup STM32H7xx_System_Private_Macros
0147   * @{
0148   */
0149
0150 /**
0151   * @}
0152   */
0153
0154 /** @addtogroup STM32H7xx_System_Private_Variables
0155   * @{
0156   */
0157   /* This variable is updated in three ways:
0158       1) by calling CMSIS function SystemCoreClockUpdate()
0159       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
0160       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
0161          Note: If you use this function to configure the system clock; then there
0162                is no need to call the 2 first functions listed above, since SystemCoreClock
0163                variable is updated automatically.
0164   */
0165 #ifndef __rtems__
0166   uint32_t SystemCoreClock = 64000000;
0167   uint32_t SystemD2Clock = 64000000;
0168 #else /* __rtems__ */
0169   RTEMS_SECTION(".rtemsstack") uint32_t SystemCoreClock;
0170   RTEMS_SECTION(".rtemsstack") uint32_t SystemD2Clock;
0171 #endif /* __rtems__ */
0172   const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
0173
0174 /**
0175   * @}
0176   */
0177
0178 /** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
0179   * @{
0180   */
0181 #ifndef __rtems__
0182 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
0183   static void SystemInit_ExtMemCtl(void);
0184 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
0185 #endif /* __rtems__ */
0186
0187 /**
0188   * @}
0189   */
0190
0191 /** @addtogroup STM32H7xx_System_Private_Functions
0192   * @{
0193   */
0194
0195 /**
0196   * @brief  Setup the microcontroller system
0197   *         Initialize the FPU setting, vector table location and External memory
0198   *         configuration.
0199   * @param  None
0200   * @retval None
0201   */
0202 void SystemInit (void)
0203 {
0204   /* FPU settings ------------------------------------------------------------*/
0205   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
0206     SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
0207   #endif
0208
0209     /*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is
0210      detectable by the CPU after a WFI/WFE instruction.*/
0211  SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
0212
0213 #ifdef CORE_CM7
0214   /* Reset the RCC clock configuration to the default reset state ------------*/
0215   /* Set HSION bit */
0216   RCC->CR |= RCC_CR_HSION;
0217
0218   /* Reset CFGR register */
0219   RCC->CFGR = 0x00000000;
0220
0221   /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
0222   RCC->CR &= 0xEAF6ED7FU;
0223
0224   /* Reset D1CFGR register */
0225   RCC->D1CFGR = 0x00000000;
0226
0227   /* Reset D2CFGR register */
0228   RCC->D2CFGR = 0x00000000;
0229
0230   /* Reset D3CFGR register */
0231   RCC->D3CFGR = 0x00000000;
0232
0233   /* Reset PLLCKSELR register */
0234   RCC->PLLCKSELR = 0x00000000;
0235
0236   /* Reset PLLCFGR register */
0237   RCC->PLLCFGR = 0x00000000;
0238   /* Reset PLL1DIVR register */
0239   RCC->PLL1DIVR = 0x00000000;
0240   /* Reset PLL1FRACR register */
0241   RCC->PLL1FRACR = 0x00000000;
0242
0243   /* Reset PLL2DIVR register */
0244   RCC->PLL2DIVR = 0x00000000;
0245
0246   /* Reset PLL2FRACR register */
0247
0248   RCC->PLL2FRACR = 0x00000000;
0249   /* Reset PLL3DIVR register */
0250   RCC->PLL3DIVR = 0x00000000;
0251
0252   /* Reset PLL3FRACR register */
0253   RCC->PLL3FRACR = 0x00000000;
0254
0255   /* Reset HSEBYP bit */
0256   RCC->CR &= 0xFFFBFFFFU;
0257
0258   /* Disable all interrupts */
0259   RCC->CIER = 0x00000000;
0260
0261   /* Enable CortexM7 HSEM EXTI line (line 78)*/
0262   EXTI_D2->EMR3 |= 0x4000UL;
0263
0264   /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
0265   if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
0266   {
0267     /* if stm32h7 revY*/
0268     /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
0269     *((__IO uint32_t*)0x51008108) = 0x00000001U;
0270   }
0271
0272
0273 /*
0274    * Disable the FMC bank1 (enabled after reset).
0275    * This, prevents CPU speculation access on this bank which blocks the use of FMC during
0276    * 24us. During this time the others FMC master (such as LTDC) cannot use it!
0277    */
0278   FMC_Bank1_R->BTCR[0] = 0x000030D2;
0279
0280 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
0281   SystemInit_ExtMemCtl();
0282 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
0283
0284 #endif /* CORE_CM7*/
0285
0286 #ifndef __rtems__
0287 #ifdef CORE_CM4
0288
0289   /* Configure the Vector Table location add offset address ------------------*/
0290 #ifdef VECT_TAB_SRAM
0291   SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
0292 #else
0293   SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
0294 #endif
0295
0296 #else
0297 #ifdef CORE_CM7
0298
0299   /* Configure the Vector Table location add offset address ------------------*/
0300 #ifdef VECT_TAB_SRAM
0301   SCB->VTOR = D1_AXISRAM_BASE  | VECT_TAB_OFFSET;       /* Vector Table Relocation in Internal SRAM */
0302 #else
0303   SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET;       /* Vector Table Relocation in Internal FLASH */
0304 #endif
0305
0306 #else
0307 #error Please #define CORE_CM4 or CORE_CM7
0308 #endif
0309 #endif
0310
0311 #else /* __rtems__ */
0312   SCB->VTOR = (uint32_t) bsp_start_vector_table_begin;
0313 #endif /* __rtems__ */
0314
0315 }
0316
0317 /**
0318    * @brief  Update SystemCoreClock variable according to Clock Register Values.
0319   *         The SystemCoreClock variable contains the core clock , it can
0320   *         be used by the user application to setup the SysTick timer or configure
0321   *         other parameters.
0322   *
0323   * @note   Each time the core clock changes, this function must be called
0324   *         to update SystemCoreClock variable value. Otherwise, any configuration
0325   *         based on this variable will be incorrect.
0326   *
0327   * @note   - The system frequency computed by this function is not the real
0328   *           frequency in the chip. It is calculated based on the predefined
0329   *           constant and the selected clock source:
0330   *
0331   *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
0332   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
0333   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
0334   *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
0335   *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
0336   *
0337   *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
0338   *             4 MHz) but the real value may vary depending on the variations
0339   *             in voltage and temperature.
0340   *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
0341   *             64 MHz) but the real value may vary depending on the variations
0342   *             in voltage and temperature.
0343   *
0344   *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
0345   *              25 MHz), user has to ensure that HSE_VALUE is same as the real
0346   *              frequency of the crystal used. Otherwise, this function may
0347   *              have wrong result.
0348   *
0349   *         - The result of this function could be not correct when using fractional
0350   *           value for HSE crystal.
0351   * @param  None
0352   * @retval None
0353   */
0354 void SystemCoreClockUpdate (void)
0355 {
0356   uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
0357   uint32_t common_system_clock;
0358   float_t fracn1, pllvco;
0359
0360   /* Get SYSCLK source -------------------------------------------------------*/
0361
0362   switch (RCC->CFGR & RCC_CFGR_SWS)
0363   {
0364   case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
0365     common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
0366     break;
0367
0368   case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
0369     common_system_clock = CSI_VALUE;
0370     break;
0371
0372   case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
0373     common_system_clock = HSE_VALUE;
0374     break;
0375
0376   case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
0377
0378     /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
0379     SYSCLK = PLL_VCO / PLLR
0380     */
0381     pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
0382     pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
0383     pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
0384     fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
0385
0386     if (pllm != 0U)
0387     {
0388       switch (pllsource)
0389       {
0390         case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
0391
0392         hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
0393         pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
0394
0395         break;
0396
0397         case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
0398           pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
0399         break;
0400
0401         case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
0402           pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
0403         break;
0404
0405       default:
0406           pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
0407         break;
0408       }
0409       pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
0410       common_system_clock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
0411     }
0412     else
0413     {
0414       common_system_clock = 0U;
0415     }
0416     break;
0417
0418   default:
0419     common_system_clock = CSI_VALUE;
0420     break;
0421   }
0422
0423   /* Compute SystemClock frequency --------------------------------------------------*/
0424   tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
0425
0426   /* common_system_clock frequency : CM7 CPU frequency  */
0427   common_system_clock >>= tmp;
0428
0429   /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
0430   SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
0431
0432 #if defined(DUAL_CORE) && defined(CORE_CM4)
0433   SystemCoreClock = SystemD2Clock;
0434 #else
0435   SystemCoreClock = common_system_clock;
0436 #endif /* DUAL_CORE && CORE_CM4 */
0437 }
0438 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
0439 /**
0440   * @brief  Setup the external memory controller.
0441   *         Called in startup_stm32h7xx.s before jump to main.
0442   *         This function configures the external memories (SRAM/SDRAM)
0443   *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
0444   * @param  None
0445   * @retval None
0446   */
0447 void SystemInit_ExtMemCtl(void)
0448 {
0449   __IO uint32_t tmp = 0;
0450
0451 #if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
0452   register uint32_t tmpreg = 0, timeout = 0xFFFF;
0453   register __IO uint32_t index;
0454
0455   /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
0456       clock */
0457   RCC->AHB4ENR |= 0x000001F8;
0458
0459   /* Delay after an RCC peripheral clock enabling */
0460   tmp = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);
0461
0462   /* Connect PDx pins to FMC Alternate function */
0463   GPIOD->AFR[0]  = 0x00CC00CC;
0464   GPIOD->AFR[1]  = 0xCCCCCCCC;
0465   /* Configure PDx pins in Alternate function mode */
0466   GPIOD->MODER   = 0xAAAAFAFA;
0467   /* Configure PDx pins speed to 100 MHz */
0468   GPIOD->OSPEEDR = 0xFFFF0F0F;
0469   /* Configure PDx pins Output type to push-pull */
0470   GPIOD->OTYPER  = 0x00000000;
0471   /* Configure PDx pins in Pull-up */
0472   GPIOD->PUPDR   = 0x55550505;
0473
0474   /* Connect PEx pins to FMC Alternate function */
0475   GPIOE->AFR[0]  = 0xC00CC0CC;
0476   GPIOE->AFR[1]  = 0xCCCCCCCC;
0477   /* Configure PEx pins in Alternate function mode */
0478   GPIOE->MODER   = 0xAAAABEBA;
0479   /* Configure PEx pins speed to 100 MHz */
0480   GPIOE->OSPEEDR = 0xFFFFC3CF;
0481   /* Configure PEx pins Output type to push-pull */
0482   GPIOE->OTYPER  = 0x00000000;
0483   /* Configure PEx pins in Pull-up */
0484   GPIOE->PUPDR   = 0x55554145;
0485
0486   /* Connect PFx pins to FMC Alternate function */
0487   GPIOF->AFR[0]  = 0x00CCCCCC;
0488   GPIOF->AFR[1]  = 0xCCCCC000;
0489   /* Configure PFx pins in Alternate function mode */
0490   GPIOF->MODER   = 0xAABFFAAA;
0491   /* Configure PFx pins speed to 100 MHz */
0492   GPIOF->OSPEEDR = 0xFFC00FFF;
0493   /* Configure PFx pins Output type to push-pull */
0494   GPIOF->OTYPER  = 0x00000000;
0495   /* Configure PFx pins in Pull-up */
0496   GPIOF->PUPDR   = 0x55400555;
0497
0498   /* Connect PGx pins to FMC Alternate function */
0499   GPIOG->AFR[0]  = 0x00CCCCCC;
0500   GPIOG->AFR[1]  = 0xC0000C0C;
0501   /* Configure PGx pins in Alternate function mode */
0502   GPIOG->MODER   = 0xBFEEFAAA;
0503   /* Configure PGx pins speed to 100 MHz */
0504   GPIOG->OSPEEDR = 0xC0330FFF;
0505   /* Configure PGx pins Output type to push-pull */
0506   GPIOG->OTYPER  = 0x00000000;
0507   /* Configure PGx pins in Pull-up */
0508   GPIOG->PUPDR   = 0x40110555;
0509
0510   /* Connect PHx pins to FMC Alternate function */
0511   GPIOH->AFR[0]  = 0xCCC00000;
0512   GPIOH->AFR[1]  = 0xCCCCCCCC;
0513   /* Configure PHx pins in Alternate function mode */
0514   GPIOH->MODER   = 0xAAAAABFF;
0515   /* Configure PHx pins speed to 100 MHz */
0516   GPIOH->OSPEEDR = 0xFFFFFC00;
0517   /* Configure PHx pins Output type to push-pull */
0518   GPIOH->OTYPER  = 0x00000000;
0519   /* Configure PHx pins in Pull-up */
0520   GPIOH->PUPDR   = 0x55555400;
0521
0522   /* Connect PIx pins to FMC Alternate function */
0523   GPIOI->AFR[0]  = 0xCCCCCCCC;
0524   GPIOI->AFR[1]  = 0x00000CC0;
0525   /* Configure PIx pins in Alternate function mode */
0526   GPIOI->MODER   = 0xFFEBAAAA;
0527   /* Configure PIx pins speed to 100 MHz */
0528   GPIOI->OSPEEDR = 0x003CFFFF;
0529   /* Configure PIx pins Output type to push-pull */
0530   GPIOI->OTYPER  = 0x00000000;
0531   /* Configure PIx pins in Pull-up */
0532   GPIOI->PUPDR   = 0x00145555;
0533
0534   /* Enable the FMC/FSMC interface clock */
0535   (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
0536
0537   /* Configure and enable Bank1_SRAM2 */
0538   FMC_Bank1_R->BTCR[4]  = 0x00001091;
0539   FMC_Bank1_R->BTCR[5]  = 0x00110212;
0540   FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
0541
0542   /*SDRAM Timing and access interface configuration*/
0543   /*LoadToActiveDelay  = 2
0544     ExitSelfRefreshDelay = 6
0545     SelfRefreshTime      = 4
0546     RowCycleDelay        = 6
0547     WriteRecoveryTime    = 2
0548     RPDelay              = 2
0549     RCDDelay             = 2
0550     SDBank             = FMC_SDRAM_BANK2
0551     ColumnBitsNumber   = FMC_SDRAM_COLUMN_BITS_NUM_9
0552     RowBitsNumber      = FMC_SDRAM_ROW_BITS_NUM_12
0553     MemoryDataWidth    = FMC_SDRAM_MEM_BUS_WIDTH_32
0554     InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4
0555     CASLatency         = FMC_SDRAM_CAS_LATENCY_2
0556     WriteProtection    = FMC_SDRAM_WRITE_PROTECTION_DISABLE
0557     SDClockPeriod      = FMC_SDRAM_CLOCK_PERIOD_2
0558     ReadBurst          = FMC_SDRAM_RBURST_ENABLE
0559     ReadPipeDelay      = FMC_SDRAM_RPIPE_DELAY_0*/
0560
0561   FMC_Bank5_6_R->SDCR[0] = 0x00001800;
0562   FMC_Bank5_6_R->SDCR[1] = 0x00000165;
0563   FMC_Bank5_6_R->SDTR[0] = 0x00105000;
0564   FMC_Bank5_6_R->SDTR[1] = 0x01010351;
0565
0566   /* SDRAM initialization sequence */
0567   /* Clock enable command */
0568   FMC_Bank5_6_R->SDCMR = 0x00000009;
0569   tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
0570   while((tmpreg != 0) && (timeout-- > 0))
0571   {
0572     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
0573   }
0574
0575   /* Delay */
0576   for (index = 0; index<1000; index++);
0577
0578   /* PALL command */
0579     FMC_Bank5_6_R->SDCMR = 0x0000000A;
0580   timeout = 0xFFFF;
0581   while((tmpreg != 0) && (timeout-- > 0))
0582   {
0583     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
0584   }
0585
0586   FMC_Bank5_6_R->SDCMR = 0x000000EB;
0587   timeout = 0xFFFF;
0588   while((tmpreg != 0) && (timeout-- > 0))
0589   {
0590     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
0591   }
0592
0593   FMC_Bank5_6_R->SDCMR = 0x0004400C;
0594   timeout = 0xFFFF;
0595   while((tmpreg != 0) && (timeout-- > 0))
0596   {
0597     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
0598   }
0599   /* Set refresh count */
0600   tmpreg = FMC_Bank5_6_R->SDRTR;
0601   FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603<<1));
0602
0603   /* Disable write protection */
0604   tmpreg = FMC_Bank5_6_R->SDCR[1];
0605   FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
0606
0607    /*FMC controller Enable*/
0608   FMC_Bank1_R->BTCR[0]  |= 0x80000000;
0609
0610 #elif defined (DATA_IN_ExtSDRAM)
0611   register uint32_t tmpreg = 0, timeout = 0xFFFF;
0612   register __IO uint32_t index;
0613
0614   /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
0615       clock */
0616   RCC->AHB4ENR |= 0x000001F8;
0617
0618   /* Connect PDx pins to FMC Alternate function */
0619   GPIOD->AFR[0]  = 0x000000CC;
0620   GPIOD->AFR[1]  = 0xCC000CCC;
0621   /* Configure PDx pins in Alternate function mode */
0622   GPIOD->MODER   = 0xAFEAFFFA;
0623   /* Configure PDx pins speed to 100 MHz */
0624   GPIOD->OSPEEDR = 0xF03F000F;
0625   /* Configure PDx pins Output type to push-pull */
0626   GPIOD->OTYPER  = 0x00000000;
0627   /* Configure PDx pins in Pull-up */
0628   GPIOD->PUPDR   = 0x50150005;
0629
0630   /* Connect PEx pins to FMC Alternate function */
0631   GPIOE->AFR[0]  = 0xC00000CC;
0632   GPIOE->AFR[1]  = 0xCCCCCCCC;
0633   /* Configure PEx pins in Alternate function mode */
0634   GPIOE->MODER   = 0xAAAABFFA;
0635   /* Configure PEx pins speed to 100 MHz */
0636   GPIOE->OSPEEDR = 0xFFFFC00F;
0637   /* Configure PEx pins Output type to push-pull */
0638   GPIOE->OTYPER  = 0x00000000;
0639   /* Configure PEx pins in Pull-up */
0640   GPIOE->PUPDR   = 0x55554005;
0641
0642   /* Connect PFx pins to FMC Alternate function */
0643   GPIOF->AFR[0]  = 0x00CCCCCC;
0644   GPIOF->AFR[1]  = 0xCCCCC000;
0645   /* Configure PFx pins in Alternate function mode */
0646   GPIOF->MODER   = 0xAABFFAAA;
0647   /* Configure PFx pins speed to 100 MHz */
0648   GPIOF->OSPEEDR = 0xFFC00FFF;
0649   /* Configure PFx pins Output type to push-pull */
0650   GPIOF->OTYPER  = 0x00000000;
0651   /* Configure PFx pins in Pull-up */
0652   GPIOF->PUPDR   = 0x55400555;
0653
0654   /* Connect PGx pins to FMC Alternate function */
0655   GPIOG->AFR[0]  = 0x00CCCCCC;
0656   GPIOG->AFR[1]  = 0xC000000C;
0657   /* Configure PGx pins in Alternate function mode */
0658   GPIOG->MODER   = 0xBFFEFAAA;
0659  /* Configure PGx pins speed to 100 MHz */
0660   GPIOG->OSPEEDR = 0xC0030FFF;
0661   /* Configure PGx pins Output type to push-pull */
0662   GPIOG->OTYPER  = 0x00000000;
0663   /* Configure PGx pins in Pull-up */
0664   GPIOG->PUPDR   = 0x40010555;
0665
0666   /* Connect PHx pins to FMC Alternate function */
0667   GPIOH->AFR[0]  = 0xCCC00000;
0668   GPIOH->AFR[1]  = 0xCCCCCCCC;
0669   /* Configure PHx pins in Alternate function mode */
0670   GPIOH->MODER   = 0xAAAAABFF;
0671   /* Configure PHx pins speed to 100 MHz */
0672   GPIOH->OSPEEDR = 0xFFFFFC00;
0673   /* Configure PHx pins Output type to push-pull */
0674   GPIOH->OTYPER  = 0x00000000;
0675   /* Configure PHx pins in Pull-up */
0676   GPIOH->PUPDR   = 0x55555400;
0677
0678   /* Connect PIx pins to FMC Alternate function */
0679   GPIOI->AFR[0]  = 0xCCCCCCCC;
0680   GPIOI->AFR[1]  = 0x00000CC0;
0681   /* Configure PIx pins in Alternate function mode */
0682   GPIOI->MODER   = 0xFFEBAAAA;
0683   /* Configure PIx pins speed to 100 MHz */
0684   GPIOI->OSPEEDR = 0x003CFFFF;
0685   /* Configure PIx pins Output type to push-pull */
0686   GPIOI->OTYPER  = 0x00000000;
0687   /* Configure PIx pins in Pull-up */
0688   GPIOI->PUPDR   = 0x00145555;
0689
0690 /*-- FMC Configuration ------------------------------------------------------*/
0691   /* Enable the FMC interface clock */
0692   (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
0693   /*SDRAM Timing and access interface configuration*/
0694   /*LoadToActiveDelay  = 2
0695     ExitSelfRefreshDelay = 6
0696     SelfRefreshTime      = 4
0697     RowCycleDelay        = 6
0698     WriteRecoveryTime    = 2
0699     RPDelay              = 2
0700     RCDDelay             = 2
0701     SDBank             = FMC_SDRAM_BANK2
0702     ColumnBitsNumber   = FMC_SDRAM_COLUMN_BITS_NUM_9
0703     RowBitsNumber      = FMC_SDRAM_ROW_BITS_NUM_12
0704     MemoryDataWidth    = FMC_SDRAM_MEM_BUS_WIDTH_32
0705     InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4
0706     CASLatency         = FMC_SDRAM_CAS_LATENCY_2
0707     WriteProtection    = FMC_SDRAM_WRITE_PROTECTION_DISABLE
0708     SDClockPeriod      = FMC_SDRAM_CLOCK_PERIOD_2
0709     ReadBurst          = FMC_SDRAM_RBURST_ENABLE
0710     ReadPipeDelay      = FMC_SDRAM_RPIPE_DELAY_0*/
0711
0712   FMC_Bank5_6_R->SDCR[0] = 0x00001800;
0713   FMC_Bank5_6_R->SDCR[1] = 0x00000165;
0714   FMC_Bank5_6_R->SDTR[0] = 0x00105000;
0715   FMC_Bank5_6_R->SDTR[1] = 0x01010351;
0716
0717   /* SDRAM initialization sequence */
0718   /* Clock enable command */
0719   FMC_Bank5_6_R->SDCMR = 0x00000009;
0720   tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
0721   while((tmpreg != 0) && (timeout-- > 0))
0722   {
0723     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
0724   }
0725
0726   /* Delay */
0727   for (index = 0; index<1000; index++);
0728
0729   /* PALL command */
0730     FMC_Bank5_6_R->SDCMR = 0x0000000A;
0731   timeout = 0xFFFF;
0732   while((tmpreg != 0) && (timeout-- > 0))
0733   {
0734     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
0735   }
0736
0737   FMC_Bank5_6_R->SDCMR = 0x000000EB;
0738   timeout = 0xFFFF;
0739   while((tmpreg != 0) && (timeout-- > 0))
0740   {
0741     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
0742   }
0743
0744   FMC_Bank5_6_R->SDCMR = 0x0004400C;
0745   timeout = 0xFFFF;
0746   while((tmpreg != 0) && (timeout-- > 0))
0747   {
0748     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
0749   }
0750   /* Set refresh count */
0751   tmpreg = FMC_Bank5_6_R->SDRTR;
0752   FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603<<1));
0753
0754   /* Disable write protection */
0755   tmpreg = FMC_Bank5_6_R->SDCR[1];
0756   FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
0757
0758    /*FMC controller Enable*/
0759   FMC_Bank1_R->BTCR[0]  |= 0x80000000;
0760
0761 #elif defined(DATA_IN_ExtSRAM)
0762 /*-- GPIOs Configuration -----------------------------------------------------*/
0763    /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
0764   RCC->AHB4ENR   |= 0x00000078;
0765
0766   /* Connect PDx pins to FMC Alternate function */
0767   GPIOD->AFR[0]  = 0x00CC00CC;
0768   GPIOD->AFR[1]  = 0xCCCCCCCC;
0769   /* Configure PDx pins in Alternate function mode */
0770   GPIOD->MODER   = 0xAAAAFABA;
0771   /* Configure PDx pins speed to 100 MHz */
0772   GPIOD->OSPEEDR = 0xFFFF0F0F;
0773   /* Configure PDx pins Output type to push-pull */
0774   GPIOD->OTYPER  = 0x00000000;
0775   /* Configure PDx pins in Pull-up */
0776   GPIOD->PUPDR   = 0x55550505;
0777
0778   /* Connect PEx pins to FMC Alternate function */
0779   GPIOE->AFR[0]  = 0xC00CC0CC;
0780   GPIOE->AFR[1]  = 0xCCCCCCCC;
0781   /* Configure PEx pins in Alternate function mode */
0782   GPIOE->MODER   = 0xAAAABEBA;
0783   /* Configure PEx pins speed to 100 MHz */
0784   GPIOE->OSPEEDR = 0xFFFFC3CF;
0785   /* Configure PEx pins Output type to push-pull */
0786   GPIOE->OTYPER  = 0x00000000;
0787   /* Configure PEx pins in Pull-up */
0788   GPIOE->PUPDR   = 0x55554145;
0789
0790   /* Connect PFx pins to FMC Alternate function */
0791   GPIOF->AFR[0]  = 0x00CCCCCC;
0792   GPIOF->AFR[1]  = 0xCCCC0000;
0793   /* Configure PFx pins in Alternate function mode */
0794   GPIOF->MODER   = 0xAAFFFAAA;
0795   /* Configure PFx pins speed to 100 MHz */
0796   GPIOF->OSPEEDR = 0xFF000FFF;
0797   /* Configure PFx pins Output type to push-pull */
0798   GPIOF->OTYPER  = 0x00000000;
0799   /* Configure PFx pins in Pull-up */
0800   GPIOF->PUPDR   = 0x55000555;
0801
0802   /* Connect PGx pins to FMC Alternate function */
0803   GPIOG->AFR[0]  = 0x00CCCCCC;
0804   GPIOG->AFR[1]  = 0x00000C00;
0805   /* Configure PGx pins in Alternate function mode */
0806   GPIOG->MODER   = 0xFFEFFAAA;
0807   /* Configure PGx pins speed to 100 MHz */
0808   GPIOG->OSPEEDR = 0x00300FFF;
0809   /* Configure PGx pins Output type to push-pull */
0810   GPIOG->OTYPER  = 0x00000000;
0811   /* Configure PGx pins in Pull-up */
0812   GPIOG->PUPDR   = 0x00100555;
0813
0814 /*-- FMC/FSMC Configuration --------------------------------------------------*/
0815   /* Enable the FMC/FSMC interface clock */
0816   (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
0817
0818   /* Configure and enable Bank1_SRAM2 */
0819   FMC_Bank1_R->BTCR[4]  = 0x00001091;
0820   FMC_Bank1_R->BTCR[5]  = 0x00110212;
0821   FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
0822
0823   /*FMC controller Enable*/
0824   FMC_Bank1_R->BTCR[0]  |= 0x80000000;
0825
0826 #endif /* DATA_IN_ExtSRAM */
0827
0828   (void)(tmp);
0829 }
0830 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
0831
0832
0833 /**
0834   * @}
0835   */
0836
0837 /**
0838   * @}
0839   */
0840
0841 /**
0842   * @}
0843   */