stm/stm32h757i-eval/stm32h747i_eval_qspi.h

0001 /* SPDX-License-Identifier: BSD-3-Clause */
0002 /**
0003   ******************************************************************************
0004   * @file    stm32h747i_eval_qspi.h
0005   * @author  MCD Application Team
0006   * @brief   This file contains the common defines and functions prototypes for
0007   *          the stm32h747i_eval_qspi.c driver.
0008   ******************************************************************************
0009   * @attention
0010   *
0011   * Copyright (c) 2019 STMicroelectronics.
0012   * All rights reserved.
0013   *
0014   * This software is licensed under terms that can be found in the LICENSE file
0015   * in the root directory of this software component.
0016   * If no LICENSE file comes with this software, it is provided AS-IS.
0017   *
0018   ******************************************************************************
0019   */
0020 /*
0021  * RTEMS committer clarification comment on license above:
0022  *
0023  * This file comes from STM32CubeH7 project and is located here:
0024  * https://github.com/STMicroelectronics/STM32CubeH7/blob/master/Drivers/BSP/STM32H747I-EVAL/stm32h747i_eval_qspi.h
0025  *
0026  * The file root directory is:
0027  * https://github.com/STMicroelectronics/STM32CubeH7/tree/master/Drivers/BSP/STM32H747I-EVAL
0028  *
0029  * This directory contains LICENSE.md file with a following license text:
0030  *
0031  * Copyright 2019 STMicroelectronics.
0032  * All rights reserved.
0033  *
0034  * Redistribution and use in source and binary forms, with or without modification,
0035  * are permitted provided that the following conditions are met:
0036  *
0037  * 1. Redistributions of source code must retain the above copyright notice, this
0038  * list of conditions and the following disclaimer.
0039  *
0040  * 2. Redistributions in binary form must reproduce the above copyright notice,
0041  * this list of conditions and the following disclaimer in the documentation and/or
0042  * other materials provided with the distribution.
0043  *
0044  * 3. Neither the name of the copyright holder nor the names of its contributors
0045  * may be used to endorse or promote products derived from this software without
0046  * specific prior written permission.
0047  *
0048  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0049  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0050  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0051  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
0052  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0053  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0054  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0055  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0056  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0057  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0058  */
0059 /* Define to prevent recursive inclusion -------------------------------------*/
0060 #ifndef STM32H747I_EVAL_QSPI_H
0061 #define STM32H747I_EVAL_QSPI_H
0062
0063 #ifdef __cplusplus
0064  extern "C" {
0065 #endif
0066
0067 /* Includes ------------------------------------------------------------------*/
0068 #include "stm32h747i_eval_conf.h"
0069 #include "stm32h747i_eval_errno.h"
0070 #include "../Components/mt25tl01g/mt25tl01g.h"
0071
0072 /** @addtogroup BSP
0073   * @{
0074   */
0075
0076 /** @addtogroup STM32H747I_EVAL
0077   * @{
0078   */
0079
0080 /** @addtogroup STM32H747I_EVAL_QSPI
0081   * @{
0082   */
0083 /* Exported types ------------------------------------------------------------*/
0084 /** @defgroup STM32H747I_EVAL_QSPI_Exported_Types QSPI Exported Types
0085   * @{
0086   */
0087 #define BSP_QSPI_Info_t                 MT25TL01G_Info_t
0088 #define BSP_QSPI_Interface_t            MT25TL01G_Interface_t
0089 #define BSP_QSPI_Transfer_t             MT25TL01G_Transfer_t
0090 #define BSP_QSPI_DualFlash_t            MT25TL01G_DualFlash_t
0091 #define BSP_QSPI_ODS_t                  MT25TL01G_ODS_t
0092
0093 typedef enum
0094 {
0095   BSP_QSPI_ERASE_8K   =  MT25TL01G_ERASE_4K ,       /*!< 8K size Sector erase = 2 x 4K as Dual flash mode is used for this board   */
0096   BSP_QSPI_ERASE_64K  =  MT25TL01G_ERASE_32K ,      /*!< 64K size Sector erase = 2 x 32K as Dual flash mode is used for this board */
0097   BSP_QSPI_ERASE_128K =  MT25TL01G_ERASE_64K ,      /*!< 128K size Sector erase = 2 x 64K as Dual mode is used for this board      */
0098   BSP_QSPI_ERASE_CHIP =  MT25TL01G_ERASE_CHIP       /*!< Whole chip erase */
0099
0100 } BSP_QSPI_Erase_t;
0101
0102 typedef enum
0103 {
0104   QSPI_ACCESS_NONE = 0,          /*!<  Instance not initialized,             */
0105   QSPI_ACCESS_INDIRECT,          /*!<  Instance use indirect mode access     */
0106   QSPI_ACCESS_MMP                /*!<  Instance use Memory Mapped Mode read  */
0107 } BSP_QSPI_Access_t;
0108
0109 typedef struct
0110 {
0111   BSP_QSPI_Access_t    IsInitialized;   /*!<  Instance access Flash method     */
0112   BSP_QSPI_Interface_t InterfaceMode;   /*!<  Flash Interface mode of Instance */
0113   BSP_QSPI_Transfer_t  TransferRate;    /*!<  Flash Transfer mode of Instance  */
0114   uint32_t             DualFlashMode;   /*!<  Flash dual mode                  */
0115   uint32_t             IsMspCallbacksValid;
0116 } BSP_QSPI_Ctx_t;
0117
0118 typedef struct
0119 {
0120   BSP_QSPI_Interface_t        InterfaceMode;   /*!<  Current Flash Interface mode */
0121   BSP_QSPI_Transfer_t         TransferRate;    /*!<  Current Flash Transfer mode  */
0122   BSP_QSPI_DualFlash_t        DualFlashMode;   /*!<  Dual Flash mode              */
0123 } BSP_QSPI_Init_t;
0124
0125 typedef struct
0126 {
0127   uint32_t FlashSize;
0128   uint32_t ClockPrescaler;
0129   uint32_t SampleShifting;
0130   uint32_t DualFlashMode;
0131 }MX_QSPI_Init_t;
0132 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
0133 typedef struct
0134 {
0135  void(*pMspInitCb)(pQSPI_CallbackTypeDef);
0136  void(*pMspDeInitCb)(pQSPI_CallbackTypeDef);
0137 }BSP_QSPI_Cb_t;
0138 #endif /* (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) */
0139
0140 /**
0141   * @}
0142   */
0143
0144 /* Exported constants --------------------------------------------------------*/
0145 /** @defgroup STM32H747I_EVAL_QSPI_Exported_Constants QSPI Exported Constants
0146   * @{
0147   */
0148 /* QSPI instances number */
0149 #define QSPI_INSTANCES_NUMBER         1U
0150
0151 /* Definition for QSPI modes */
0152 #define BSP_QSPI_SPI_MODE            (BSP_QSPI_Interface_t)MT25TL01G_SPI_MODE      /* 1 Cmd Line, 1 Address Line and 1 Data Line    */
0153 #define BSP_QSPI_SPI_1I2O_MODE       (BSP_QSPI_Interface_t)MT25TL01G_SPI_1I2O_MODE /* 1 Cmd Line, 1 Address Line and 2 Data Lines   */
0154 #define BSP_QSPI_SPI_2IO_MODE        (BSP_QSPI_Interface_t)MT25TL01G_SPI_2IO_MODE  /* 1 Cmd Line, 2 Address Lines and 2 Data Lines  */
0155 #define BSP_QSPI_SPI_1I4O_MODE       (BSP_QSPI_Interface_t)MT25TL01G_SPI_1I4O_MODE /* 1 Cmd Line, 1 Address Line and 4 Data Lines   */
0156 #define BSP_QSPI_SPI_4IO_MODE        (BSP_QSPI_Interface_t)MT25TL01G_SPI_4IO_MODE  /* 1 Cmd Line, 4 Address Lines and 4 Data Lines  */
0157 #define BSP_QSPI_DPI_MODE            (BSP_QSPI_Interface_t)MT25TL01G_DPI_MODE      /* 2 Cmd Lines, 2 Address Lines and 2 Data Lines */
0158 #define BSP_QSPI_QPI_MODE            (BSP_QSPI_Interface_t)MT25TL01G_QPI_MODE      /* 4 Cmd Lines, 4 Address Lines and 4 Data Lines */
0159
0160 /* Definition for QSPI transfer rates */
0161 #define BSP_QSPI_STR_TRANSFER        (BSP_QSPI_Transfer_t)MT25TL01G_STR_TRANSFER /* Single Transfer Rate */
0162 #define BSP_QSPI_DTR_TRANSFER        (BSP_QSPI_Transfer_t)MT25TL01G_DTR_TRANSFER /* Double Transfer Rate */
0163
0164 /* Definition for QSPI dual flash mode */
0165 #define BSP_QSPI_DUALFLASH_DISABLE   (BSP_QSPI_DualFlash_t)MT25TL01G_DUALFLASH_DISABLE   /* Dual flash mode enabled  */
0166 /* Definition for QSPI Flash ID */
0167 #define BSP_QSPI_FLASH_ID            QSPI_FLASH_ID_1
0168
0169 /* QSPI block sizes for dual flash */
0170 #define BSP_QSPI_BLOCK_8K            MT25TL01G_SECTOR_4K
0171 #define BSP_QSPI_BLOCK_64K           MT25TL01G_BLOCK_32K
0172 #define BSP_QSPI_BLOCK_128K          MT25TL01G_BLOCK_64K
0173
0174 /* Definition for QSPI clock resources */
0175 #define QSPI_CLK_ENABLE()              __HAL_RCC_QSPI_CLK_ENABLE()
0176 #define QSPI_CLK_DISABLE()             __HAL_RCC_QSPI_CLK_DISABLE()
0177 #define QSPI_CLK_GPIO_CLK_ENABLE()     __HAL_RCC_GPIOB_CLK_ENABLE()
0178 #define QSPI_BK1_CS_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOG_CLK_ENABLE()
0179 #define QSPI_BK1_D0_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOF_CLK_ENABLE()
0180 #define QSPI_BK1_D1_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOF_CLK_ENABLE()
0181 #define QSPI_BK1_D2_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOF_CLK_ENABLE()
0182 #define QSPI_BK1_D3_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOF_CLK_ENABLE()
0183 #define QSPI_BK2_CS_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOC_CLK_ENABLE()
0184 #define QSPI_BK2_D0_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOH_CLK_ENABLE()
0185 #define QSPI_BK2_D1_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOH_CLK_ENABLE()
0186 #define QSPI_BK2_D2_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOG_CLK_ENABLE()
0187 #define QSPI_BK2_D3_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOG_CLK_ENABLE()
0188
0189
0190 #define QSPI_FORCE_RESET()         __HAL_RCC_QSPI_FORCE_RESET()
0191 #define QSPI_RELEASE_RESET()       __HAL_RCC_QSPI_RELEASE_RESET()
0192
0193 /* Definition for QSPI Pins */
0194 #define QSPI_CLK_PIN               GPIO_PIN_2
0195 #define QSPI_CLK_GPIO_PORT         GPIOB
0196 /* Bank 1 */
0197 #define QSPI_BK1_CS_PIN            GPIO_PIN_6
0198 #define QSPI_BK1_CS_GPIO_PORT      GPIOG
0199 #define QSPI_BK1_D0_PIN            GPIO_PIN_8
0200 #define QSPI_BK1_D0_GPIO_PORT      GPIOF
0201 #define QSPI_BK1_D1_PIN            GPIO_PIN_9
0202 #define QSPI_BK1_D1_GPIO_PORT      GPIOF
0203 #define QSPI_BK1_D2_PIN            GPIO_PIN_7
0204 #define QSPI_BK1_D2_GPIO_PORT      GPIOF
0205 #define QSPI_BK1_D3_PIN            GPIO_PIN_6
0206 #define QSPI_BK1_D3_GPIO_PORT      GPIOF
0207
0208 /* Bank 2 */
0209 #define QSPI_BK2_CS_PIN            GPIO_PIN_11
0210 #define QSPI_BK2_CS_GPIO_PORT      GPIOC
0211 #define QSPI_BK2_D0_PIN            GPIO_PIN_2
0212 #define QSPI_BK2_D0_GPIO_PORT      GPIOH
0213 #define QSPI_BK2_D1_PIN            GPIO_PIN_3
0214 #define QSPI_BK2_D1_GPIO_PORT      GPIOH
0215 #define QSPI_BK2_D2_PIN            GPIO_PIN_9
0216 #define QSPI_BK2_D2_GPIO_PORT      GPIOG
0217 #define QSPI_BK2_D3_PIN            GPIO_PIN_14
0218 #define QSPI_BK2_D3_GPIO_PORT      GPIOG
0219
0220
0221 /* MT25TL01G Micron memory */
0222 /* Size of the flash */
0223 #define QSPI_FLASH_SIZE            26     /* Address bus width to access whole memory space */
0224 #define QSPI_PAGE_SIZE             256
0225
0226 /* QSPI Base Address */
0227 #define QSPI_BASE_ADDRESS          0x90000000
0228 /**
0229   * @}
0230   */
0231
0232 /** @addtogroup STM32H747I_EVAL_QSPI_Exported_Variables
0233   * @{
0234   */
0235 extern QSPI_HandleTypeDef hqspi;
0236 extern BSP_QSPI_Ctx_t     QSPI_Ctx[];
0237 /**
0238   * @}
0239   */
0240
0241 /* Exported functions --------------------------------------------------------*/
0242 /** @addtogroup STM32H747I_EVAL_QSPI_Exported_Functions
0243   * @{
0244   */
0245 int32_t BSP_QSPI_Init(uint32_t Instance, BSP_QSPI_Init_t *Init);
0246 int32_t BSP_QSPI_DeInit(uint32_t Instance);
0247 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
0248 int32_t BSP_QSPI_RegisterMspCallbacks (uint32_t Instance, BSP_QSPI_Cb_t *CallBacks);
0249 int32_t BSP_QSPI_RegisterDefaultMspCallbacks (uint32_t Instance);
0250 #endif /* (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) */
0251 int32_t BSP_QSPI_Read(uint32_t Instance, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
0252 int32_t BSP_QSPI_Write(uint32_t Instance, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
0253 int32_t BSP_QSPI_EraseBlock(uint32_t Instance, uint32_t BlockAddress, BSP_QSPI_Erase_t BlockSize);
0254 int32_t BSP_QSPI_EraseChip(uint32_t Instance);
0255 int32_t BSP_QSPI_GetStatus(uint32_t Instance);
0256 int32_t BSP_QSPI_GetInfo(uint32_t Instance, BSP_QSPI_Info_t *pInfo);
0257 int32_t BSP_QSPI_EnableMemoryMappedMode(uint32_t Instance);
0258 int32_t BSP_QSPI_DisableMemoryMappedMode(uint32_t Instance);
0259 int32_t BSP_QSPI_ReadID(uint32_t Instance, uint8_t *Id);
0260 int32_t BSP_QSPI_ConfigFlash(uint32_t Instance, BSP_QSPI_Interface_t Mode, BSP_QSPI_Transfer_t Rate);
0261
0262 /* These functions can be modified in case the current settings
0263    need to be changed for specific application needs */
0264 HAL_StatusTypeDef MX_QSPI_Init(QSPI_HandleTypeDef *hQspi, MX_QSPI_Init_t *Config);
0265
0266 /**
0267   * @}
0268   */
0269
0270 /**
0271   * @}
0272   */
0273
0274 #ifdef __cplusplus
0275 }
0276 #endif
0277 #endif /* __STM32H747I_EVAL_QSPI_H */
0278 /**
0279   * @}
0280   */
0281
0282 /**
0283   * @}
0284   */