stm/nucleo-h755zi/stm32h7-config-per.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (C) 2020 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #ifdef HAVE_CONFIG_H
0029 #include "config.h"
0030 #endif
0031
0032 #include <stm32h7/hal.h>
0033
0034 const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
0035   .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3
0036     | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1
0037     | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG,
0038   .PLL2.PLL2M = 3,
0039   .PLL2.PLL2N = 48,
0040   .PLL2.PLL2P = 1,
0041   .PLL2.PLL2Q = 2,
0042   .PLL2.PLL2R = 2,
0043   .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3,
0044   .PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE,
0045   .PLL2.PLL2FRACN = 0,
0046   .PLL3.PLL3M = 25,
0047   .PLL3.PLL3N = 192,
0048   .PLL3.PLL3P = 2,
0049   .PLL3.PLL3Q = 4,
0050   .PLL3.PLL3R = 2,
0051   .PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0,
0052   .PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE,
0053   .PLL3.PLL3FRACN = 0,
0054   .FmcClockSelection = RCC_FMCCLKSOURCE_PLL2,
0055   .FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL,
0056   .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1,
0057   .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2,
0058   .I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1,
0059   .UsbClockSelection = RCC_USBCLKSOURCE_PLL3,
0060   .RTCClockSelection = RCC_RTCCLKSOURCE_NO_CLK,
0061   .RngClockSelection = RCC_RNGCLKSOURCE_LSI
0062 };