Components/mt25tl01g/mt25tl01g.h

0001 /* SPDX-License-Identifier: BSD-3-Clause */
0002 /**
0003   ******************************************************************************
0004   * @file    MT25TL01G.h
0005   * @author  MCD Application Team
0006   * @brief   This file contains all the description of the MT25TL01G QSPI memory.
0007   ******************************************************************************
0008   * @attention
0009   *
0010   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
0011   * All rights reserved.</center></h2>
0012   *
0013   * This software component is licensed by ST under BSD 3-Clause license,
0014   * the "License"; You may not use this file except in compliance with the
0015   * License. You may obtain a copy of the License at:
0016   *                        opensource.org/licenses/BSD-3-Clause
0017   *
0018   ******************************************************************************
0019   */
0020
0021 /* Define to prevent recursive inclusion -------------------------------------*/
0022 #ifndef MT25TL01G_H
0023 #define MT25TL01G_H
0024
0025 #ifdef __cplusplus
0026  extern "C" {
0027 #endif
0028
0029 /* Includes ------------------------------------------------------------------*/
0030 #include "mt25tl01g_conf.h"
0031 /** @addtogroup BSP
0032   * @{
0033   */
0034
0035 /** @addtogroup Components
0036   * @{
0037   */
0038
0039 /** @addtogroup MT25TL01G
0040   * @{
0041   */
0042
0043 /** @defgroup MT25TL01G_Exported_Types
0044   * @{
0045   */
0046    typedef struct {
0047   uint32_t FlashSize;          /*!< Size of the flash */
0048   uint32_t EraseSectorSize;    /*!< Size of sectors for the erase operation */
0049   uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */
0050   uint32_t ProgPageSize;       /*!< Size of pages for the program operation */
0051   uint32_t ProgPagesNumber;    /*!< Number of pages for the program operation */
0052 } MT25TL01G_Info;
0053
0054 /* MT25TL01G Component Error codes *********************************************/
0055 #define MT25TL01G_OK                           0
0056 #define MT25TL01G_ERROR_INIT                  -1
0057 #define MT25TL01G_ERROR_COMMAND               -2
0058 #define MT25TL01G_ERROR_TRANSMIT              -3
0059 #define MT25TL01G_ERROR_RECEIVE               -4
0060 #define MT25TL01G_ERROR_AUTOPOLLING           -5
0061 #define MT25TL01G_ERROR_MEMORYMAPPED          -6
0062 /**exported type **/
0063
0064
0065 /******************MT25TL01G_Info_t**********************/
0066 typedef struct
0067 {
0068   uint32_t FlashSize;          /*!< Size of the flash */
0069   uint32_t EraseSectorSize;    /*!< Size of sectors for the erase operation */
0070   uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */
0071   uint32_t ProgPageSize;       /*!< Size of pages for the program operation */
0072   uint32_t ProgPagesNumber;    /*!< Number of pages for the program operation */
0073 } MT25TL01G_Info_t;
0074
0075
0076
0077 /******************MT25TL01G_Transfer_t**********************/
0078 typedef enum
0079 {
0080   MT25TL01G_SPI_MODE = 0,                 /*!< 1-1-1 commands, Power on H/W default setting */
0081   MT25TL01G_SPI_2IO_MODE,                 /*!< 1-1-2, 1-2-2 read commands                   */
0082   MT25TL01G_SPI_4IO_MODE,                 /*!< 1-1-4, 1-4-4 read commands                   */
0083   MT25TL01G_QPI_MODE                      /*!< 4-4-4 commands                               */
0084 } MT25TL01G_Interface_t;
0085
0086 /******************MT25TL01G_Transfer_t**********************/
0087
0088 typedef enum
0089 {
0090   MT25TL01G_STR_TRANSFER = 0,             /* Single Transfer Rate */
0091   MT25TL01G_DTR_TRANSFER                  /* Double Transfer Rate */
0092 } MT25TL01G_Transfer_t;
0093
0094 /******************MT25TL01G_DualFlash_t**********************/
0095
0096
0097 typedef enum
0098 {
0099   MT25TL01G_DUALFLASH_DISABLE = QSPI_DUALFLASH_DISABLE, /*!<  Single flash mode              */
0100   MT25TL01G_DUALFLASH_ENABLE  =QSPI_DUALFLASH_ENABLE
0101 } MT25TL01G_DualFlash_t;
0102
0103
0104
0105 /******************MT25TL01G_Erase_t**********************/
0106
0107
0108 typedef enum
0109 {
0110   MT25TL01G_ERASE_4K = 0,                 /*!< 4K size Sector erase */
0111   MT25TL01G_ERASE_32K,                    /*!< 32K size Block erase */
0112   MT25TL01G_ERASE_64K,                    /*!< 64K size Block erase */
0113   MT25TL01G_ERASE_CHIP                    /*!< Whole chip erase     */
0114 } MT25TL01G_Erase_t;
0115 /**
0116   * @}
0117   */
0118
0119 /** @defgroup MT25TL01G_Exported_Constants
0120   * @{
0121   */
0122
0123 /**
0124   * @brief  MT25TL01G Configuration
0125   */
0126 #define MT25TL01G_FLASH_SIZE                  0x8000000 /* 2 * 512 MBits => 2 * 64MBytes => 128MBytes*/
0127 #define MT25TL01G_SECTOR_SIZE                 0x10000   /* 2 * 1024 sectors of 64KBytes */
0128 #define MT25TL01G_SUBSECTOR_SIZE              0x1000    /* 2 * 16384 subsectors of 4kBytes */
0129 #define MT25TL01G_PAGE_SIZE                   0x100     /* 2 * 262144 pages of 256 bytes */
0130
0131 #define MT25TL01G_DIE_ERASE_MAX_TIME          460000
0132 #define MT25TL01G_SECTOR_ERASE_MAX_TIME       1000
0133 #define MT25TL01G_SUBSECTOR_ERASE_MAX_TIME    400
0134
0135 /**
0136   * @brief  MT25TL01G Commands
0137   */
0138 /* Reset Operations */
0139 #define MT25TL01G_RESET_ENABLE_CMD                     0x66
0140 #define MT25TL01G_RESET_MEMORY_CMD                     0x99
0141
0142 /* Identification Operations */
0143 #define MT25TL01G_READ_ID_CMD                          0x9E
0144 #define MT25TL01G_READ_ID_CMD2                         0x9F
0145 #define MT25TL01G_MULTIPLE_IO_READ_ID_CMD              0xAF
0146 #define MT25TL01G_READ_SERIAL_FLASH_DISCO_PARAM_CMD    0x5A
0147
0148 /* Read Operations */
0149 #define MT25TL01G_READ_CMD                             0x03
0150 #define MT25TL01G_READ_4_BYTE_ADDR_CMD                 0x13
0151
0152 #define MT25TL01G_FAST_READ_CMD                        0x0B
0153 #define MT25TL01G_FAST_READ_DTR_CMD                    0x0D
0154 #define MT25TL01G_FAST_READ_4_BYTE_ADDR_CMD            0x0C
0155 #define MT25TL01G_FAST_READ_4_BYTE_DTR_CMD             0x0E
0156
0157 #define MT25TL01G_DUAL_OUT_FAST_READ_CMD               0x3B
0158 #define MT25TL01G_DUAL_OUT_FAST_READ_DTR_CMD           0x3D
0159 #define MT25TL01G_DUAL_OUT_FAST_READ_4_BYTE_ADDR_CMD   0x3C
0160
0161 #define MT25TL01G_DUAL_INOUT_FAST_READ_CMD             0xBB
0162 #define MT25TL01G_DUAL_INOUT_FAST_READ_DTR_CMD         0xBD
0163 #define MT25TL01G_DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xBC
0164
0165 #define MT25TL01G_QUAD_OUT_FAST_READ_CMD               0x6B
0166 #define MT25TL01G_QUAD_OUT_FAST_READ_DTR_CMD           0x6D
0167 #define MT25TL01G_QUAD_OUT_FAST_READ_4_BYTE_ADDR_CMD   0x6C
0168
0169 #define MT25TL01G_QUAD_INOUT_FAST_READ_CMD             0xEB
0170 #define MT25TL01G_QUAD_INOUT_FAST_READ_DTR_CMD         0xED
0171 #define MT25TL01G_QUAD_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xEC
0172 #define MT25TL01G_QUAD_INOUT_FAST_READ_4_BYTE_DTR_CMD  0xEE
0173 /* Write Operations */
0174 #define MT25TL01G_WRITE_ENABLE_CMD                     0x06
0175 #define MT25TL01G_WRITE_DISABLE_CMD                    0x04
0176
0177 /* Register Operations */
0178 #define MT25TL01G_READ_STATUS_REG_CMD                  0x05
0179 #define MT25TL01G_WRITE_STATUS_REG_CMD                 0x01
0180
0181 #define MT25TL01G_READ_LOCK_REG_CMD                    0xE8
0182 #define MT25TL01G_WRITE_LOCK_REG_CMD                   0xE5
0183
0184 #define MT25TL01G_READ_FLAG_STATUS_REG_CMD             0x70
0185 #define MT25TL01G_CLEAR_FLAG_STATUS_REG_CMD            0x50
0186
0187 #define MT25TL01G_READ_NONVOL_CFG_REG_CMD              0xB5
0188 #define MT25TL01G_WRITE_NONVOL_CFG_REG_CMD             0xB1
0189
0190 #define MT25TL01G_READ_VOL_CFG_REG_CMD                 0x85
0191 #define MT25TL01G_WRITE_VOL_CFG_REG_CMD                0x81
0192
0193 #define MT25TL01G_READ_ENHANCED_VOL_CFG_REG_CMD        0x65
0194 #define MT25TL01G_WRITE_ENHANCED_VOL_CFG_REG_CMD       0x61
0195
0196 #define MT25TL01G_READ_EXT_ADDR_REG_CMD                0xC8
0197 #define MT25TL01G_WRITE_EXT_ADDR_REG_CMD               0xC5
0198
0199 /* Program Operations */
0200 #define MT25TL01G_PAGE_PROG_CMD                        0x02
0201 #define MT25TL01G_PAGE_PROG_4_BYTE_ADDR_CMD            0x12
0202
0203 #define MT25TL01G_DUAL_IN_FAST_PROG_CMD                0xA2
0204 #define MT25TL01G_EXT_DUAL_IN_FAST_PROG_CMD            0xD2
0205
0206 #define MT25TL01G_QUAD_IN_FAST_PROG_CMD                0x32
0207 #define MT25TL01G_EXT_QUAD_IN_FAST_PROG_CMD            0x38
0208 #define MT25TL01G_QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD    0x34
0209
0210 /* Erase Operations */
0211 #define MT25TL01G_SUBSECTOR_ERASE_CMD_4K               0x20
0212 #define MT25TL01G_SUBSECTOR_ERASE_4_BYTE_ADDR_CMD_4K   0x21
0213
0214 #define MT25TL01G_SUBSECTOR_ERASE_CMD_32K              0x52
0215
0216 #define MT25TL01G_SECTOR_ERASE_CMD                     0xD8
0217 #define MT25TL01G_SECTOR_ERASE_4_BYTE_ADDR_CMD         0xDC
0218
0219 #define MT25TL01G_DIE_ERASE_CMD                        0xC7
0220
0221 #define MT25TL01G_PROG_ERASE_RESUME_CMD                0x7A
0222 #define MT25TL01G_PROG_ERASE_SUSPEND_CMD               0x75
0223
0224 /* One-Time Programmable Operations */
0225 #define MT25TL01G_READ_OTP_ARRAY_CMD                   0x4B
0226 #define MT25TL01G_PROG_OTP_ARRAY_CMD                   0x42
0227
0228 /* 4-byte Address Mode Operations */
0229 #define MT25TL01G_ENTER_4_BYTE_ADDR_MODE_CMD           0xB7
0230 #define MT25TL01G_EXIT_4_BYTE_ADDR_MODE_CMD            0xE9
0231
0232 /* Quad Operations */
0233 #define MT25TL01G_ENTER_QUAD_CMD                       0x35
0234 #define MT25TL01G_EXIT_QUAD_CMD                        0xF5
0235 #define MT25TL01G_ENTER_DEEP_POWER_DOWN                0xB9
0236 #define MT25TL01G_RELEASE_FROM_DEEP_POWER_DOWN         0xAB
0237
0238 /*ADVANCED SECTOR PROTECTION Operations*/
0239 #define MT25TL01G_READ_SECTOR_PROTECTION_CMD           0x2D
0240 #define MT25TL01G_PROGRAM_SECTOR_PROTECTION            0x2C
0241 #define MT25TL01G_READ_PASSWORD_CMD                    0x27
0242 #define MT25TL01G_WRITE_PASSWORD_CMD                   0x28
0243 #define MT25TL01G_UNLOCK_PASSWORD_CMD                  0x29
0244 #define MT25TL01G_READ_GLOBAL_FREEZE_BIT               0xA7
0245 #define MT25TL01G_READ_VOLATILE_LOCK_BITS              0xE8
0246 #define MT25TL01G_WRITE_VOLATILE_LOCK_BITS             0xE5
0247     /*ADVANCED SECTOR PROTECTION Operations with 4-Byte Address*/
0248 #define MT25TL01G_WRITE_4_BYTE_VOLATILE_LOCK_BITS      0xE1
0249 #define MT25TL01G_READ_4_BYTE_VOLATILE_LOCK_BITS       0xE0
0250     /*One Time Programmable Operations */
0251 #define MT25TL01G_READ_OTP_ARRAY                       0x4B
0252 #define MT25TL01G_PROGRAM_OTP_ARRAY                    0x42
0253
0254
0255 /**
0256   * @brief  MT25TL01G Registers
0257   */
0258 /* Status Register */
0259 #define MT25TL01G_SR_WIP                      ((uint8_t)0x01)    /*!< Write in progress */
0260 #define MT25TL01G_SR_WREN                     ((uint8_t)0x02)    /*!< Write enable latch */
0261 #define MT25TL01G_SR_BLOCKPR                  ((uint8_t)0x5C)    /*!< Block protected against program and erase operations */
0262 #define MT25TL01G_SR_PRBOTTOM                 ((uint8_t)0x20)    /*!< Protected memory area defined by BLOCKPR starts from top or bottom */
0263 #define MT25TL01G_SR_SRWREN                   ((uint8_t)0x80)    /*!< Status register write enable/disable */
0264
0265 /* Non volatile Configuration Register */
0266 #define MT25TL01G_NVCR_NBADDR                 ((uint16_t)0x0001) /*!< 3-bytes or 4-bytes addressing */
0267 #define MT25TL01G_NVCR_SEGMENT                ((uint16_t)0x0002) /*!< Upper or lower 128Mb segment selected by default */
0268 #define MT25TL01G_NVCR_DUAL                   ((uint16_t)0x0004) /*!< Dual I/O protocol */
0269 #define MT25TL01G_NVCR_QUAB                   ((uint16_t)0x0008) /*!< Quad I/O protocol */
0270 #define MT25TL01G_NVCR_RH                     ((uint16_t)0x0010) /*!< Reset/hold */
0271 #define MT25TL01G_NVCR_DTRP                   ((uint16_t)0x0020) /*!< Double transfer rate protocol */
0272 #define MT25TL01G_NVCR_ODS                    ((uint16_t)0x01C0) /*!< Output driver strength */
0273 #define MT25TL01G_NVCR_XIP                    ((uint16_t)0x0E00) /*!< XIP mode at power-on reset */
0274 #define MT25TL01G_NVCR_NB_DUMMY               ((uint16_t)0xF000) /*!< Number of dummy clock cycles */
0275
0276 /* Volatile Configuration Register */
0277 #define MT25TL01G_VCR_WRAP                    ((uint8_t)0x03)    /*!< Wrap */
0278 #define MT25TL01G_VCR_XIP                     ((uint8_t)0x08)    /*!< XIP */
0279 #define MT25TL01G_VCR_NB_DUMMY                ((uint8_t)0xF0)    /*!< Number of dummy clock cycles */
0280
0281 /* Extended Address Register */
0282 #define MT25TL01G_EAR_HIGHEST_SE              ((uint8_t)0x03)    /*!< Select the Highest 128Mb segment */
0283 #define MT25TL01G_EAR_THIRD_SEG               ((uint8_t)0x02)    /*!< Select the Third 128Mb segment */
0284 #define MT25TL01G_EAR_SECOND_SEG              ((uint8_t)0x01)    /*!< Select the Second 128Mb segment */
0285 #define MT25TL01G_EAR_LOWEST_SEG              ((uint8_t)0x00)    /*!< Select the Lowest 128Mb segment (default) */
0286
0287 /* Enhanced Volatile Configuration Register */
0288 #define MT25TL01G_EVCR_ODS                    ((uint8_t)0x07)    /*!< Output driver strength */
0289 #define MT25TL01G_EVCR_RH                     ((uint8_t)0x10)    /*!< Reset/hold */
0290 #define MT25TL01G_EVCR_DTRP                   ((uint8_t)0x20)    /*!< Double transfer rate protocol */
0291 #define MT25TL01G_EVCR_DUAL                   ((uint8_t)0x40)    /*!< Dual I/O protocol */
0292 #define MT25TL01G_EVCR_QUAD                   ((uint8_t)0x80)    /*!< Quad I/O protocol */
0293
0294 /* Flag Status Register */
0295 #define MT25TL01G_FSR_NBADDR                  ((uint8_t)0x01)    /*!< 3-bytes or 4-bytes addressing */
0296 #define MT25TL01G_FSR_PRERR                   ((uint8_t)0x02)    /*!< Protection error */
0297 #define MT25TL01G_FSR_PGSUS                   ((uint8_t)0x04)    /*!< Program operation suspended */
0298 #define MT25TL01G_FSR_PGERR                   ((uint8_t)0x10)    /*!< Program error */
0299 #define MT25TL01G_FSR_ERERR                   ((uint8_t)0x20)    /*!< Erase error */
0300 #define MT25TL01G_FSR_ERSUS                   ((uint8_t)0x40)    /*!< Erase operation suspended */
0301 #define MT25TL01G_FSR_READY                   ((uint8_t)0x80)    /*!< Ready or command in progress */
0302
0303
0304 /**
0305   * @}
0306   */
0307
0308 /** @defgroup MT25TL01G_Exported_Functions
0309   * @{
0310   */
0311
0312 int32_t MT25TL01G_GetFlashInfo(MT25TL01G_Info_t *pInfo);
0313 int32_t MT25TL01G_Enter4BytesAddressMode(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0314 int32_t MT25TL01G_Exit4BytesAddressMode(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0315 int32_t MT25TL01G_AutoPollingMemReady(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0316 /* Register/Setting Commands *************************************************/
0317 int32_t MT25TL01G_WriteEnable(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0318 int32_t MT25TL01G_BlockErase(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint32_t BlockAddress, MT25TL01G_Erase_t BlockSize);
0319 int32_t MT25TL01G_ChipErase(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0320 int32_t MT25TL01G_PageProgram(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
0321 int32_t MT25TL01G_ReadSTR(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
0322 int32_t MT25TL01G_ReadDTR(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
0323 int32_t MT25TL01G_ReadStatusRegister(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *Value);
0324 int32_t MT25TL01G_EnterQPIMode(QSPI_HandleTypeDef *Ctx);
0325 int32_t MT25TL01G_ExitQPIMode(QSPI_HandleTypeDef *Ctx);
0326
0327 int32_t MT25TL01G_EnableMemoryMappedModeSTR(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0328 int32_t MT25TL01G_EnableMemoryMappedModeDTR(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0329 int32_t MT25TL01G_WriteDisable(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0330 int32_t MT25TL01G_ReadID(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *ID);
0331
0332 int32_t MT25TL01G_ResetMemory(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0333 int32_t MT25TL01G_ResetEnable(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0334
0335 int32_t MT25TL01G_ReadSPBLockRegister(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *SPBRegister);
0336 int32_t MT25TL01G_ReleaseFromDeepPowerDown(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0337 int32_t MT25TL01G_EnterDeepPowerDown(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0338 int32_t MT25TL01G_ProgEraseResume(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0339 int32_t MT25TL01G_ProgEraseSuspend(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode);
0340 /**
0341   * @}
0342   */
0343
0344 #ifdef __cplusplus
0345 }
0346 #endif
0347
0348 #endif /* __MT25TL01G_H */
0349
0350 /**
0351   * @}
0352   */
0353
0354 /**
0355   * @}
0356   */
0357
0358 /**
0359   * @}
0360   */
0361
0362 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/