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File indexing completed on 2025-05-11 08:23:05 

0001 /* SPDX-License-Identifier: BSD-3-Clause */
0002 /**
0003   ******************************************************************************
0004   * @file    MT25TL01G.c
0005   * @author  MCD Application Team
0006   * @brief   This file provides the MT25TL01G QSPI driver.
0007   ******************************************************************************
0008   * @attention
0009   *
0010   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
0011   * All rights reserved.</center></h2>
0012   *
0013   * This software component is licensed by ST under BSD 3-Clause license,
0014   * the "License"; You may not use this file except in compliance with the
0015   * License. You may obtain a copy of the License at:
0016   *                        opensource.org/licenses/BSD-3-Clause
0017   *
0018   ******************************************************************************
0019   */
0020 /* Includes ------------------------------------------------------------------*/
0021 #include "mt25tl01g.h"
0022 /** @addtogroup BSP
0023   * @{
0024   */
0025 
0026 /** @addtogroup Components
0027   * @{
0028   */
0029 
0030 /** @addtogroup MT25TL01G
0031   * @brief     This file provides a set of functions needed to drive the
0032   *             MT25TL01G QSPI memory.
0033   * @{
0034   */
0035 /** @defgroup MT25TL01G_Exported_Functions MT25TL01G Exported Functions
0036   * @{
0037   */
0038 
0039 /**
0040   * @brief  Return the configuration of the QSPI memory.
0041   * @param  pInfo pointer on the configuration structure
0042   * @retval QSPI memory status
0043   */
0044 int32_t MT25TL01G_GetFlashInfo(MT25TL01G_Info_t *pInfo)
0045 {
0046   pInfo->FlashSize          = MT25TL01G_FLASH_SIZE;
0047   pInfo->EraseSectorSize    = (2 * MT25TL01G_SUBSECTOR_SIZE);
0048   pInfo->ProgPageSize       = MT25TL01G_PAGE_SIZE;
0049   pInfo->EraseSectorsNumber = (MT25TL01G_FLASH_SIZE/pInfo->EraseSectorSize);
0050   pInfo->ProgPagesNumber    = (MT25TL01G_FLASH_SIZE/pInfo->ProgPageSize);
0051   return MT25TL01G_OK;
0052 }
0053 
0054 /**
0055   * @brief  This function set the QSPI memory in 4-byte address mode
0056   *          SPI/QPI; 1-0-1/4-0-4
0057   * @param  Ctx Component object pointer
0058   * @param  Mode Interface mode
0059   * @retval QSPI memory status
0060   */
0061 int32_t MT25TL01G_Enter4BytesAddressMode(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0062 {
0063   QSPI_CommandTypeDef s_command;
0064 
0065   /* Initialize the command */
0066   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0067   s_command.Instruction       = MT25TL01G_ENTER_4_BYTE_ADDR_MODE_CMD;
0068   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0069   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0070   s_command.DataMode          = QSPI_DATA_NONE;
0071   s_command.DummyCycles       = 0;
0072   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0073   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0074   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0075 
0076   /*write enable */
0077   if( MT25TL01G_WriteEnable(Ctx,Mode)!=MT25TL01G_OK)
0078   {
0079     return MT25TL01G_ERROR_COMMAND;
0080   }
0081   /* Send the command */
0082   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0083   {
0084     return MT25TL01G_ERROR_COMMAND;
0085   }
0086 
0087   /* Configure automatic polling mode to wait the memory is ready */
0088   else if(MT25TL01G_AutoPollingMemReady(Ctx,Mode)!=MT25TL01G_OK)
0089   {
0090     return MT25TL01G_ERROR_COMMAND;
0091   }
0092 
0093   return MT25TL01G_OK;
0094 }
0095 
0096 /**
0097   * @brief  Flash exit 4 Byte address mode. Effect 3/4 address byte commands only.
0098   *         SPI/QPI; 1-0-0/4-0-0
0099   * @param  Ctx Component object pointer
0100   * @param  Mode Interface mode
0101   * @retval QSPI memory status
0102   */
0103 int32_t MT25TL01G_Exit4BytesAddressMode(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0104 {
0105   QSPI_CommandTypeDef s_command;
0106 
0107   /* Initialize the command */
0108   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0109   s_command.Instruction       = MT25TL01G_EXIT_4_BYTE_ADDR_MODE_CMD;
0110   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0111   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0112   s_command.DataMode          = QSPI_DATA_NONE;
0113   s_command.DummyCycles       = 0;
0114   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0115   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0116   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0117 
0118 
0119   /* Send the command */
0120   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0121   {
0122     return MT25TL01G_ERROR_COMMAND;
0123   }
0124 
0125   return MT25TL01G_OK;
0126 }
0127 /**
0128   * @brief  Polling WIP(Write In Progress) bit become to 0
0129   *         SPI/QPI;4-0-4
0130   * @param  Ctx Component object pointer
0131   * @param  Mode Interface mode
0132   * @retval QSPI memory status
0133   */
0134 int32_t MT25TL01G_AutoPollingMemReady(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0135 {
0136 
0137   QSPI_CommandTypeDef     s_command;
0138   QSPI_AutoPollingTypeDef s_config;
0139 
0140   /* Configure automatic polling mode to wait for memory ready */
0141   s_command.InstructionMode   = QSPI_INSTRUCTION_4_LINES;
0142   s_command.Instruction       = MT25TL01G_READ_STATUS_REG_CMD;
0143   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0144   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0145   s_command.DataMode          = QSPI_DATA_4_LINES;
0146   s_command.DummyCycles       = 2;
0147   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0148   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0149   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0150 
0151   s_config.Match           = 0;
0152   s_config.MatchMode       = QSPI_MATCH_MODE_AND;
0153   s_config.Interval        = 0x10;
0154   s_config.AutomaticStop   = QSPI_AUTOMATIC_STOP_ENABLE;
0155   s_config.Mask            = MT25TL01G_SR_WIP | (MT25TL01G_SR_WIP <<8);
0156   s_config.StatusBytesSize = 2;
0157 
0158   if (HAL_QSPI_AutoPolling(Ctx, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0159   {
0160     return MT25TL01G_ERROR_AUTOPOLLING;
0161   }
0162 
0163   return MT25TL01G_OK;
0164 
0165 }
0166 /**
0167   * @brief  This function send a Write Enable and wait it is effective.
0168   * @param  Ctx Component object pointer
0169   * @param  Mode Interface mode
0170   * @retval QSPI memory status
0171   */
0172 
0173 int32_t MT25TL01G_WriteEnable(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0174 {
0175   QSPI_CommandTypeDef     s_command;
0176   QSPI_AutoPollingTypeDef s_config;
0177 
0178   /* Enable write operations */
0179   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0180 
0181   s_command.Instruction       = MT25TL01G_WRITE_ENABLE_CMD;
0182   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0183   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0184   s_command.DataMode          = QSPI_DATA_NONE;
0185   s_command.DummyCycles       = 0;
0186   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0187   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0188   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0189 
0190   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0191   {
0192     return MT25TL01G_ERROR_COMMAND;
0193   }
0194 
0195   /* Configure automatic polling mode to wait for write enabling */
0196   s_config.Match           = MT25TL01G_SR_WREN | (MT25TL01G_SR_WREN << 8);
0197   s_config.Mask            = MT25TL01G_SR_WREN | (MT25TL01G_SR_WREN << 8);
0198   s_config.MatchMode       = QSPI_MATCH_MODE_AND;
0199   s_config.StatusBytesSize = 2;
0200   s_config.Interval        = 0x10;
0201   s_config.AutomaticStop   = QSPI_AUTOMATIC_STOP_ENABLE;
0202 
0203   s_command.Instruction    = MT25TL01G_READ_STATUS_REG_CMD;
0204   s_command.DataMode       = (Mode == MT25TL01G_QPI_MODE) ? QSPI_DATA_4_LINES : QSPI_DATA_1_LINE;
0205 
0206 
0207   if (HAL_QSPI_AutoPolling(Ctx, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0208   {
0209     return MT25TL01G_ERROR_AUTOPOLLING;
0210   }
0211 
0212   return MT25TL01G_OK;
0213 }
0214 
0215 /**
0216   * @brief  This function reset the (WEL) Write Enable Latch bit.
0217   *         SPI/QPI; 1-0-0/4-0-0
0218   * @param  Ctx Component object pointer
0219   * @param  Mode Interface mode
0220   * @retval QSPI memory status
0221   */
0222 int32_t MT25TL01G_WriteDisable(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0223 {
0224   QSPI_CommandTypeDef     s_command;
0225   /* Enable write operations */
0226   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0227   s_command.Instruction       = MT25TL01G_WRITE_DISABLE_CMD;
0228   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0229   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0230   s_command.DataMode          = QSPI_DATA_NONE;
0231   s_command.DummyCycles       = 0;
0232   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0233   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0234   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0235 
0236   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0237   {
0238     return MT25TL01G_ERROR_COMMAND;
0239   }
0240   return MT25TL01G_OK;
0241 }
0242 
0243 
0244 /**
0245   * @brief  Writes an amount of data to the QSPI memory.
0246   *         SPI/QPI; 1-1-1/1-2-2/1-4-4/4-4-4
0247   * @param  Ctx Component object pointer
0248   * @param  Mode Interface mode
0249   * @param  pData Pointer to data to be written
0250   * @param  WriteAddr Write start address
0251   * @param  Size Size of data to write. Range 1 ~ 256
0252   * @retval QSPI memory status
0253   */
0254 
0255 int32_t MT25TL01G_PageProgram(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *pData, uint32_t WriteAddr, uint32_t Size)
0256 {
0257   QSPI_CommandTypeDef s_command;
0258   switch(Mode)
0259   {
0260 
0261   case MT25TL01G_SPI_MODE :                   /* 1-1-1 commands, Power on H/W default setting */
0262     s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
0263     s_command.Instruction     = MT25TL01G_PAGE_PROG_CMD;
0264     s_command.AddressMode     = QSPI_ADDRESS_1_LINE;
0265     s_command.DataMode        = QSPI_DATA_1_LINE;
0266     break;
0267 
0268   case MT25TL01G_SPI_2IO_MODE :               /*  1-2-2 commands */
0269     s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
0270     s_command.Instruction     = MT25TL01G_EXT_DUAL_IN_FAST_PROG_CMD;
0271     s_command.AddressMode     = QSPI_ADDRESS_2_LINES;
0272     s_command.DataMode        = QSPI_DATA_2_LINES;
0273     break;
0274 
0275   case MT25TL01G_SPI_4IO_MODE :               /* 1-4-4 program commands */
0276     s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
0277     s_command.Instruction     = MT25TL01G_EXT_QUAD_IN_FAST_PROG_CMD;
0278     s_command.AddressMode     = QSPI_ADDRESS_4_LINES;
0279     s_command.DataMode        = QSPI_DATA_4_LINES;
0280     break;
0281 
0282   case MT25TL01G_QPI_MODE :                   /* 4-4-4 commands */
0283     s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
0284     s_command.Instruction     = MT25TL01G_QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD;
0285     s_command.AddressMode     = QSPI_ADDRESS_4_LINES;
0286     s_command.DataMode        = QSPI_DATA_4_LINES;
0287     break;
0288 
0289   }
0290 
0291   s_command.AddressSize       = QSPI_ADDRESS_32_BITS;
0292   s_command.Address           = WriteAddr;
0293   s_command.NbData            = Size;
0294   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0295   s_command.DummyCycles       = 0;
0296   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0297   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0298   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0299   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0300   {
0301     return MT25TL01G_ERROR_COMMAND;
0302   }
0303   if (HAL_QSPI_Transmit(Ctx, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0304   {
0305     return MT25TL01G_ERROR_TRANSMIT;
0306   }
0307   return MT25TL01G_OK;
0308 }
0309 /**
0310   * @brief  Reads an amount of data from the QSPI memory on DTR mode.
0311   *         SPI/QPI; 1-1-1/1-1-2/1-4-4/4-4-4
0312   * @param  Ctx Component object pointer
0313   * @param  Mode Interface mode
0314   * @param  pData Pointer to data to be read
0315   * @param  ReadAddr Read start address
0316   * @param  Size Size of data to read
0317   * @retval QSPI memory status
0318   */
0319 int32_t MT25TL01G_ReadDTR(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *pData, uint32_t ReadAddr, uint32_t Size)
0320 {
0321   QSPI_CommandTypeDef s_command;
0322   switch(Mode)
0323   {
0324   case MT25TL01G_SPI_MODE:                /* 1-1-1 commands, Power on H/W default setting */
0325     s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0326     s_command.Instruction       = MT25TL01G_FAST_READ_4_BYTE_DTR_CMD;
0327     s_command.AddressMode       = QSPI_ADDRESS_1_LINE;
0328     s_command.DataMode          = QSPI_DATA_1_LINE;
0329 
0330     break;
0331   case MT25TL01G_SPI_2IO_MODE:           /* 1-1-2 read commands */
0332 
0333     s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0334     s_command.Instruction       = MT25TL01G_DUAL_OUT_FAST_READ_DTR_CMD;
0335     s_command.AddressMode       = QSPI_ADDRESS_1_LINE;
0336     s_command.DataMode          = QSPI_DATA_2_LINES;
0337 
0338     break;
0339   case MT25TL01G_SPI_4IO_MODE:             /* 1-4-4 read commands */
0340 
0341     s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0342     s_command.Instruction       = MT25TL01G_QUAD_INOUT_FAST_READ_4_BYTE_DTR_CMD;
0343     s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
0344     s_command.DataMode          = QSPI_DATA_4_LINES;
0345 
0346     break;
0347   case MT25TL01G_QPI_MODE:                 /* 4-4-4 commands */
0348     s_command.InstructionMode   = QSPI_INSTRUCTION_4_LINES;
0349     s_command.Instruction       = MT25TL01G_QUAD_INOUT_FAST_READ_DTR_CMD;
0350     s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
0351     s_command.DataMode          = QSPI_DATA_4_LINES;
0352 
0353     break;
0354   }
0355   /* Initialize the read command */
0356   s_command.DummyCycles       = MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR;
0357   s_command.AddressSize       = QSPI_ADDRESS_32_BITS;
0358   s_command.Address           = ReadAddr;
0359   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0360   s_command.NbData            = Size;
0361   s_command.DdrMode           = QSPI_DDR_MODE_ENABLE;
0362   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_HALF_CLK_DELAY;
0363   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0364 
0365   /* Configure the command */
0366   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0367   {
0368     return MT25TL01G_ERROR_COMMAND;
0369   }
0370 
0371   /* Reception of the data */
0372   if (HAL_QSPI_Receive(Ctx, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0373   {
0374     return MT25TL01G_ERROR_RECEIVE;
0375   }
0376 
0377   return MT25TL01G_OK;
0378 
0379 }
0380 
0381 /**
0382   * @brief  Reads an amount of data from the QSPI memory on STR mode.
0383   *         SPI/QPI; 1-1-1/1-2-2/1-4-4/4-4-4
0384   * @param  Ctx Component object pointer
0385   * @param  Mode Interface mode
0386   * @param  pData Pointer to data to be read
0387   * @param  ReadAddr Read start address
0388   * @param  Size Size of data to read
0389   * @retval QSPI memory status
0390   */
0391 
0392 int32_t MT25TL01G_ReadSTR(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *pData, uint32_t ReadAddr, uint32_t Size)
0393 {
0394   QSPI_CommandTypeDef s_command;
0395   switch(Mode)
0396   {
0397   case MT25TL01G_SPI_MODE:           /* 1-1-1 read commands */
0398     s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0399     s_command.Instruction       = MT25TL01G_FAST_READ_4_BYTE_ADDR_CMD;
0400     s_command.AddressMode       = QSPI_ADDRESS_1_LINE;
0401     s_command.DataMode          = QSPI_DATA_1_LINE;
0402 
0403 
0404     break;
0405   case MT25TL01G_SPI_2IO_MODE:           /* 1-2-2 read commands */
0406 
0407     s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0408     s_command.Instruction       = MT25TL01G_DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD;
0409     s_command.AddressMode       = QSPI_ADDRESS_2_LINES;
0410     s_command.DataMode          = QSPI_DATA_2_LINES;
0411 
0412     break;
0413   case MT25TL01G_SPI_4IO_MODE:             /* 1-4-4 read commands */
0414 
0415     s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0416     s_command.Instruction       = MT25TL01G_QUAD_INOUT_FAST_READ_4_BYTE_ADDR_CMD;
0417     s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
0418     s_command.DataMode          = QSPI_DATA_4_LINES;
0419 
0420     break;
0421   case MT25TL01G_QPI_MODE:                 /* 4-4-4 commands */
0422     s_command.InstructionMode   = QSPI_INSTRUCTION_4_LINES;
0423     s_command.Instruction       = MT25TL01G_QUAD_INOUT_FAST_READ_CMD;
0424     s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
0425     s_command.DataMode          = QSPI_DATA_4_LINES;
0426 
0427     break;
0428   }
0429   /* Initialize the read command */
0430   s_command.DummyCycles       = MT25TL01G_DUMMY_CYCLES_READ;
0431   s_command.AddressSize       = QSPI_ADDRESS_32_BITS;
0432   s_command.Address           = ReadAddr;
0433   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0434   s_command.NbData            = Size;
0435   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0436   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0437   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0438 
0439   /* Configure the command */
0440   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0441   {
0442     return MT25TL01G_ERROR_COMMAND;
0443   }
0444 
0445   /* Reception of the data */
0446   if (HAL_QSPI_Receive(Ctx, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0447   {
0448     return MT25TL01G_ERROR_RECEIVE;
0449   }
0450 
0451 
0452   return MT25TL01G_OK;
0453 
0454 }
0455 
0456 /**
0457   * @brief  Erases the specified block of the QSPI memory.
0458   *         MT25TL01G support 4K, 32K, 64K size block erase commands.
0459   *         SPI/QPI; 1-1-0/4-4-0
0460   * @param  Ctx Component object pointer
0461   * @param  Mode Interface mode
0462   * @param  BlockAddress Block address to erase
0463   * @retval QSPI memory status
0464   */
0465 
0466 int32_t MT25TL01G_BlockErase(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode ,uint32_t BlockAddress, MT25TL01G_Erase_t BlockSize)
0467 {
0468   QSPI_CommandTypeDef s_command;
0469   switch(BlockSize)
0470   {
0471   default :
0472   case MT25TL01G_ERASE_4K :
0473     s_command.Instruction     = MT25TL01G_SUBSECTOR_ERASE_4_BYTE_ADDR_CMD_4K;
0474     break;
0475 
0476   case MT25TL01G_ERASE_32K :
0477     s_command.Instruction     = MT25TL01G_SUBSECTOR_ERASE_CMD_32K;
0478     break;
0479 
0480   case MT25TL01G_ERASE_64K :
0481     s_command.Instruction     = MT25TL01G_SECTOR_ERASE_4_BYTE_ADDR_CMD;
0482     break;
0483 
0484   case MT25TL01G_ERASE_CHIP :
0485     return MT25TL01G_ChipErase(Ctx, Mode);
0486   }
0487   /* Initialize the erase command */
0488 
0489   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0490   s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
0491   s_command.AddressSize       = QSPI_ADDRESS_32_BITS;
0492   s_command.Address           = BlockAddress;
0493   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0494   s_command.DataMode          = QSPI_DATA_NONE;
0495   s_command.DummyCycles       = 0;
0496   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0497   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0498   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0499 
0500   /* Send the command */
0501   MT25TL01G_WriteEnable(Ctx,Mode);
0502   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0503   {
0504     return MT25TL01G_ERROR_COMMAND;
0505   }
0506   MT25TL01G_AutoPollingMemReady(Ctx,Mode);
0507   return MT25TL01G_OK;
0508 }
0509 
0510 /**
0511   * @brief  Whole chip erase.
0512   *         SPI/QPI; 1-0-0/4-0-0
0513   * @param  Ctx Component object pointer
0514   * @param  Mode Interface mode
0515   * @retval QSPI memory status
0516   */
0517 
0518 int32_t MT25TL01G_ChipErase(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0519 {
0520   QSPI_CommandTypeDef s_command;
0521 
0522   /* Initialize the erase command */
0523   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0524   s_command.Instruction       = MT25TL01G_DIE_ERASE_CMD;
0525   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0526   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0527   s_command.DataMode          = QSPI_DATA_NONE;
0528   s_command.DummyCycles       = 0;
0529   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0530   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0531   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0532 
0533   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0534   {
0535     return MT25TL01G_ERROR_COMMAND;
0536   }
0537 
0538   return MT25TL01G_OK;
0539 
0540 }
0541 /**
0542   * @brief  Read Flash Status register value
0543   *         SPI/QPI; 1-0-1/4-0-4
0544   * @param  Ctx Component object pointer
0545   * @param  Mode Interface mode
0546   * @param  Value pointer to status register value
0547   * @retval QSPI memory status
0548   */
0549 int32_t MT25TL01G_ReadStatusRegister(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *Value)
0550 {
0551   QSPI_CommandTypeDef s_command;
0552   /* Initialize the read flag status register command */
0553   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0554   s_command.Instruction       = MT25TL01G_READ_STATUS_REG_CMD;
0555   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0556   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0557   s_command.DataMode          = (Mode == MT25TL01G_QPI_MODE) ? QSPI_DATA_4_LINES : QSPI_DATA_1_LINE;
0558   s_command.DummyCycles       = 0;
0559   s_command.NbData            = 1;
0560   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0561   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0562   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0563 
0564   /* Configure the command */
0565   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0566   {
0567     return MT25TL01G_ERROR_COMMAND;
0568   }
0569 
0570   /* Reception of the data */
0571   if (HAL_QSPI_Receive(Ctx,Value, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0572   {
0573     return MT25TL01G_ERROR_RECEIVE;
0574   }
0575 
0576   return MT25TL01G_OK;
0577 }
0578 
0579 /**
0580   * @brief  This function put QSPI memory in QPI mode (Quad I/O) from SPI mode.
0581   *         SPI -> QPI; 1-x-x -> 4-4-4
0582   *         SPI; 1-0-0
0583   * @param  Ctx Component object pointer
0584   * @param  Mode Interface mode
0585   * @retval QSPI memory status
0586   */
0587 int32_t MT25TL01G_EnterQPIMode(QSPI_HandleTypeDef *Ctx)
0588 {
0589   QSPI_CommandTypeDef s_command;
0590 
0591   s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0592   s_command.Instruction       = MT25TL01G_ENTER_QUAD_CMD;
0593   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0594   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0595   s_command.DataMode          = QSPI_DATA_NONE;
0596   s_command.DummyCycles       = 0;
0597   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0598   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0599   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0600 
0601   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0602   {
0603     return MT25TL01G_ERROR_COMMAND;
0604   }
0605 
0606   return MT25TL01G_OK;
0607 }
0608 /**
0609   * @brief  This function put QSPI memory in SPI mode (Single I/O) from QPI mode.
0610   *         QPI -> SPI; 4-4-4 -> 1-x-x
0611   *         QPI; 4-0-0
0612   * @param  Ctx Component object pointer
0613   * @param  Mode Interface mode
0614   * @retval QSPI memory status
0615   */
0616 int32_t MT25TL01G_ExitQPIMode(QSPI_HandleTypeDef *Ctx)
0617 {
0618   QSPI_CommandTypeDef s_command;
0619 
0620   s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0621   s_command.Instruction       = MT25TL01G_EXIT_QUAD_CMD;
0622   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0623   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0624   s_command.DataMode          = QSPI_DATA_NONE;
0625   s_command.DummyCycles       = 0;
0626   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0627   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0628   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0629 
0630   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0631   {
0632     return MT25TL01G_ERROR_COMMAND;
0633   }
0634 
0635   return MT25TL01G_OK;
0636 }
0637 
0638 /**
0639   * @brief  Reads an amount of data from the QSPI memory on DTR mode.
0640   *         SPI/QPI; 1-1-1/1-1-2/1-4-4/4-4-4
0641   * @param  Ctx Component object pointer
0642   * @param  Mode Interface mode
0643   * @retval QSPI memory status
0644   */
0645 int32_t MT25TL01G_EnableMemoryMappedModeDTR(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0646 {
0647   QSPI_CommandTypeDef      s_command;
0648   QSPI_MemoryMappedTypeDef s_mem_mapped_cfg;
0649   switch(Mode)
0650   {
0651   case MT25TL01G_SPI_MODE:                /* 1-1-1 commands, Power on H/W default setting */
0652     s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0653     s_command.Instruction       = MT25TL01G_FAST_READ_4_BYTE_DTR_CMD;
0654     s_command.AddressMode       = QSPI_ADDRESS_1_LINE;
0655     s_command.DataMode          = QSPI_DATA_1_LINE;
0656 
0657     break;
0658   case MT25TL01G_SPI_2IO_MODE:           /* 1-1-2 read commands */
0659 
0660     s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0661     s_command.Instruction       = MT25TL01G_DUAL_OUT_FAST_READ_DTR_CMD;
0662     s_command.AddressMode       = QSPI_ADDRESS_1_LINE;
0663     s_command.DataMode          = QSPI_DATA_2_LINES;
0664 
0665     break;
0666   case MT25TL01G_SPI_4IO_MODE:             /* 1-4-4 read commands */
0667 
0668     s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0669     s_command.Instruction       = MT25TL01G_QUAD_INOUT_FAST_READ_4_BYTE_DTR_CMD;
0670     s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
0671     s_command.DataMode          = QSPI_DATA_4_LINES;
0672 
0673     break;
0674   case MT25TL01G_QPI_MODE:                 /* 4-4-4 commands */
0675     s_command.InstructionMode   = QSPI_INSTRUCTION_4_LINES;
0676     s_command.Instruction       = MT25TL01G_QUAD_INOUT_FAST_READ_DTR_CMD;
0677     s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
0678     s_command.DataMode          = QSPI_DATA_4_LINES;
0679 
0680     break;
0681   }
0682   /* Configure the command for the read instruction */
0683   s_command.AddressSize       = QSPI_ADDRESS_32_BITS;
0684   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0685   s_command.DummyCycles       = MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR;
0686   s_command.DdrMode           = QSPI_DDR_MODE_ENABLE;
0687   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_HALF_CLK_DELAY;
0688   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0689 
0690   /* Configure the memory mapped mode */
0691   s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE;
0692   s_mem_mapped_cfg.TimeOutPeriod     = 0;
0693 
0694   if (HAL_QSPI_MemoryMapped(Ctx, &s_command, &s_mem_mapped_cfg) != HAL_OK)
0695   {
0696     return MT25TL01G_ERROR_MEMORYMAPPED;
0697   }
0698 
0699   return MT25TL01G_OK;
0700 }
0701 
0702 /**
0703   * @brief  Reads an amount of data from the QSPI memory on STR mode.
0704   *         SPI/QPI; 1-1-1/1-2-2/1-4-4/4-4-4
0705   * @param  Ctx Component object pointer
0706   * @param  Mode Interface mode
0707   * @retval QSPI memory status
0708   */
0709 
0710 int32_t MT25TL01G_EnableMemoryMappedModeSTR(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0711 {
0712   QSPI_CommandTypeDef      s_command;
0713   QSPI_MemoryMappedTypeDef s_mem_mapped_cfg;
0714   switch(Mode)
0715   {
0716   case MT25TL01G_SPI_MODE:           /* 1-1-1 read commands */
0717     s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0718     s_command.Instruction       = MT25TL01G_FAST_READ_4_BYTE_ADDR_CMD;
0719     s_command.AddressMode       = QSPI_ADDRESS_1_LINE;
0720     s_command.DataMode          = QSPI_DATA_1_LINE;
0721 
0722 
0723     break;
0724   case MT25TL01G_SPI_2IO_MODE:           /* 1-2-2 read commands */
0725 
0726     s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0727     s_command.Instruction       = MT25TL01G_DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD;
0728     s_command.AddressMode       = QSPI_ADDRESS_2_LINES;
0729     s_command.DataMode          = QSPI_DATA_2_LINES;
0730 
0731     break;
0732 
0733   case MT25TL01G_SPI_4IO_MODE:             /* 1-4-4 read commands */
0734 
0735     s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
0736     s_command.Instruction       = MT25TL01G_QUAD_INOUT_FAST_READ_4_BYTE_ADDR_CMD;
0737     s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
0738     s_command.DataMode          = QSPI_DATA_4_LINES;
0739 
0740     break;
0741 
0742   case MT25TL01G_QPI_MODE:                 /* 4-4-4 commands */
0743     s_command.InstructionMode   = QSPI_INSTRUCTION_4_LINES;
0744     s_command.Instruction       = MT25TL01G_QUAD_INOUT_FAST_READ_CMD;
0745     s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
0746     s_command.DataMode          = QSPI_DATA_4_LINES;
0747 
0748     break;
0749 
0750   }
0751   /* Configure the command for the read instruction */
0752   s_command.DummyCycles       = MT25TL01G_DUMMY_CYCLES_READ;
0753   s_command.AddressSize       = QSPI_ADDRESS_32_BITS;
0754   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0755   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0756   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0757   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0758 
0759   /* Configure the memory mapped mode */
0760   s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE;
0761   s_mem_mapped_cfg.TimeOutPeriod     = 0;
0762 
0763   if (HAL_QSPI_MemoryMapped(Ctx, &s_command, &s_mem_mapped_cfg) != HAL_OK)
0764   {
0765     return MT25TL01G_ERROR_MEMORYMAPPED;
0766   }
0767 
0768   return MT25TL01G_OK;
0769 }
0770 
0771 
0772 
0773 /**
0774   * @brief  Flash reset enable command
0775   *         SPI/QPI; 1-0-0, 4-0-0
0776   * @param  Ctx Component object pointer
0777   * @param  Mode Interface mode
0778   * @retval QSPI memory status
0779   */
0780 int32_t MT25TL01G_ResetEnable(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0781 {
0782   QSPI_CommandTypeDef s_command;
0783 
0784   /* Initialize the reset enable command */
0785   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0786   s_command.Instruction       = MT25TL01G_RESET_ENABLE_CMD;
0787   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0788   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0789   s_command.DataMode          = QSPI_DATA_NONE;
0790   s_command.DummyCycles       = 0;
0791   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0792   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0793   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0794 
0795   /* Send the command */
0796   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0797   {
0798     return MT25TL01G_ERROR_COMMAND;
0799   }
0800 
0801   return MT25TL01G_OK;
0802 }
0803 
0804 
0805 /**
0806   * @brief  Flash reset memory command
0807   *         SPI/QPI; 1-0-0, 4-0-0
0808   * @param  Ctx Component object pointer
0809   * @param  Mode Interface mode
0810   * @retval QSPI memory status
0811   */
0812 int32_t MT25TL01G_ResetMemory(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0813 {
0814   QSPI_CommandTypeDef s_command;
0815 
0816   /* Initialize the reset enable command */
0817   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0818   s_command.Instruction       = MT25TL01G_RESET_MEMORY_CMD ;
0819   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0820   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0821   s_command.DataMode          = QSPI_DATA_NONE;
0822   s_command.DummyCycles       = 0;
0823   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0824   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0825   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0826 
0827   /* Send the command */
0828   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0829   {
0830     return MT25TL01G_ERROR_COMMAND;
0831   }
0832 
0833   return MT25TL01G_OK;
0834 }
0835 
0836 
0837 /**
0838   * @brief  Read Flash 3 Byte IDs.
0839   *         Manufacturer ID, Memory type, Memory density
0840   *         SPI/QPI; 1-0-1/4-0-4
0841   * @param  Ctx Component object pointer
0842   * @param  Mode Interface mode
0843   * @param  ID pointer to flash id value
0844   * @retval QSPI memory status
0845   */
0846 int32_t MT25TL01G_ReadID(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *ID)
0847 {
0848   QSPI_CommandTypeDef s_command;
0849 
0850   /* Initialize the read ID command */
0851   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0852   s_command.Instruction       = (Mode == MT25TL01G_QPI_MODE) ? MT25TL01G_MULTIPLE_IO_READ_ID_CMD  : MT25TL01G_READ_ID_CMD;
0853   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0854   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0855   s_command.DummyCycles       = 0;
0856   s_command.DataMode          = (Mode == MT25TL01G_QPI_MODE) ? QSPI_DATA_4_LINES : QSPI_DATA_1_LINE;
0857   s_command.NbData            = 3;
0858   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0859   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0860   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0861 
0862   /* Configure the command */
0863   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0864   {
0865     return MT25TL01G_ERROR_COMMAND;
0866   }
0867 
0868   /* Reception of the data */
0869   if (HAL_QSPI_Receive(Ctx, ID, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0870   {
0871     return MT25TL01G_ERROR_RECEIVE;
0872   }
0873 
0874   return MT25TL01G_OK;
0875 }
0876 
0877 /**
0878   * @brief  Program/Erases suspend. Interruption Program/Erase operations.
0879   *         After the device has entered Erase-Suspended mode,
0880   *         system can read any address except the block/sector being Program/Erased.
0881   *         SPI/QPI; 1-0-0/4-0-0
0882   * @param  Ctx Component object pointer
0883   * @param  Mode Interface mode
0884   * @retval QSPI memory status
0885   */
0886 
0887 int32_t MT25TL01G_ProgEraseSuspend(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0888 {
0889   QSPI_CommandTypeDef s_command;
0890 
0891   /* Initialize the read ID command */
0892   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0893   s_command.Instruction       = MT25TL01G_PROG_ERASE_SUSPEND_CMD ;
0894   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0895   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0896   s_command.DummyCycles       = 0;
0897   s_command.DataMode          = QSPI_DATA_NONE;
0898   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0899   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0900   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0901 
0902   /* Configure the command */
0903   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0904   {
0905     return MT25TL01G_ERROR_COMMAND;
0906   }
0907 
0908   return MT25TL01G_OK;
0909 }
0910 
0911 /**
0912   * @brief  Program/Erases resume.
0913   *         SPI/QPI; 1-0-0/4-0-0
0914   * @param  Ctx Component object pointer
0915   * @param  Mode Interface mode
0916   * @retval QSPI memory status
0917   */
0918 int32_t MT25TL01G_ProgEraseResume(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0919 {
0920   QSPI_CommandTypeDef s_command;
0921 
0922   /* Initialize the read ID command */
0923   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0924   s_command.Instruction       = MT25TL01G_PROG_ERASE_RESUME_CMD;
0925   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0926   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0927   s_command.DummyCycles       = 0;
0928   s_command.DataMode          = QSPI_DATA_NONE;
0929   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0930   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0931   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0932 
0933   /* Configure the command */
0934   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0935   {
0936     return MT25TL01G_ERROR_COMMAND;
0937   }
0938 
0939   return MT25TL01G_OK;
0940 }
0941 
0942 /**
0943   * @brief  Deep power down.
0944   *         The device is not active and all Write/Program/Erase instruction are ignored.
0945   *         SPI/QPI; 1-0-0/4-0-0
0946   * @param  Ctx Component object pointer
0947   * @param  Mode Interface mode
0948   * @retval QSPI memory status
0949   */
0950 int32_t MT25TL01G_EnterDeepPowerDown(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0951 {
0952   QSPI_CommandTypeDef s_command;
0953 
0954   /* Initialize the read ID command */
0955   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0956   s_command.Instruction       = MT25TL01G_ENTER_DEEP_POWER_DOWN;
0957   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0958   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0959   s_command.DummyCycles       = 0;
0960   s_command.DataMode          = QSPI_DATA_NONE;
0961   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0962   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0963   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0964 
0965   /* Configure the command */
0966   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0967   {
0968     return MT25TL01G_ERROR_COMMAND;
0969   }
0970 
0971   return MT25TL01G_OK;
0972 }
0973 
0974 /**
0975   * @brief  Release from deep power down.
0976   *         After CS# go high, system need wait tRES1 time for device ready.
0977   *         SPI/QPI; 1-0-0/4-0-0
0978   * @param  Ctx Component object pointer
0979   * @param  Mode Interface mode
0980   * @retval QSPI memory status
0981   */
0982 int32_t MT25TL01G_ReleaseFromDeepPowerDown(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode)
0983 {
0984   QSPI_CommandTypeDef s_command;
0985 
0986   /* Initialize the read ID command */
0987   s_command.InstructionMode   = (Mode == MT25TL01G_QPI_MODE) ? QSPI_INSTRUCTION_4_LINES : QSPI_INSTRUCTION_1_LINE;
0988   s_command.Instruction       = MT25TL01G_RELEASE_FROM_DEEP_POWER_DOWN ;
0989   s_command.AddressMode       = QSPI_ADDRESS_NONE;
0990   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
0991   s_command.DummyCycles       = 0;
0992   s_command.DataMode          = QSPI_DATA_NONE;
0993   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
0994   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
0995   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
0996 
0997   /* Configure the command */
0998   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
0999   {
1000     return MT25TL01G_ERROR_COMMAND;
1001   }
1002 
1003   return MT25TL01G_OK;
1004 }
1005 
1006 /**
1007   * @brief  Read SECTOR PROTECTION Block register value.
1008   *         SPI; 1-0-1
1009   * @param  Ctx Component object pointer
1010   * @param  Mode Interface mode
1011   * @param  SPBRegister pointer to SPBRegister value
1012   * @retval QSPI memory status
1013   */
1014 int32_t MT25TL01G_ReadSPBLockRegister(QSPI_HandleTypeDef *Ctx, MT25TL01G_Interface_t Mode, uint8_t *SPBRegister)
1015 {
1016   QSPI_CommandTypeDef s_command;
1017 
1018   /* Initialize the reading of SPB lock register command */
1019   s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
1020   s_command.Instruction       = MT25TL01G_READ_SECTOR_PROTECTION_CMD;
1021   s_command.AddressMode       = QSPI_ADDRESS_NONE;
1022   s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
1023   s_command.DummyCycles       = 0;
1024   s_command.DataMode          = QSPI_DATA_1_LINE;
1025   s_command.NbData            = 1;
1026   s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
1027   s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
1028   s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
1029 
1030   /* Configure the command */
1031   if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1032   {
1033     return MT25TL01G_ERROR_COMMAND;
1034   }
1035 
1036   /* Reception of the data */
1037   if (HAL_QSPI_Receive(Ctx, SPBRegister, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
1038   {
1039     return MT25TL01G_ERROR_RECEIVE;
1040   }
1041 
1042   return MT25TL01G_OK;
1043 }
1044 
1045 
1046
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