stm32f4/start/io.c

0001 /*
0002  * Copyright (c) 2012 Sebastian Huber.  All rights reserved.
0003  *
0004  * The license and distribution terms for this file may be
0005  * found in the file LICENSE in this distribution or at
0006  * http://www.rtems.org/license/LICENSE.
0007  */
0008
0009 #include <bsp/io.h>
0010 #include <bsp/rcc.h>
0011 #include <bsp/stm32f4.h>
0012
0013 #include <rtems.h>
0014
0015 RTEMS_STATIC_ASSERT(sizeof(stm32f4_gpio_config) == 4, size_of_config);
0016
0017 void stm32f4_gpio_set_clock(int pin, bool set)
0018 {
0019   int port = STM32F4_GPIO_PORT_OF_PIN(pin);
0020   stm32f4_rcc_index index = STM32F4_RCC_GPIOA + port;
0021
0022   stm32f4_rcc_set_clock(index, set);
0023 }
0024
0025 static void clear_and_set(
0026   volatile uint32_t *reg,
0027   unsigned index,
0028   unsigned width,
0029   uint32_t set
0030 )
0031 {
0032   uint32_t mask = (1U << width) - 1U;
0033   unsigned shift = width * index;
0034   uint32_t val = *reg;
0035
0036   val &= ~(mask << shift);
0037   val |= set << shift;
0038
0039   *reg = val;
0040 }
0041
0042 #ifdef STM32F4_FAMILY_F10XXX
0043 #define STM32F4_AFIO_REMAP_ENTRY(mod, afio_reg_v, start_v, width_v, value_v) \
0044   [mod] = { \
0045     .afio_reg = afio_reg_v, \
0046     .start = start_v, \
0047     .width = width_v, \
0048     .value = value_v, \
0049     .reserved = 0 \
0050   }
0051
0052 typedef struct {
0053   uint16_t afio_reg : 3;
0054   uint16_t start : 5;
0055   uint16_t width : 2;
0056   uint16_t value : 3;
0057   uint16_t reserved : 3;
0058 } stm32f4_afio_remap_entry;
0059
0060 static const stm32f4_afio_remap_entry stm32f4_afio_remap_table [] = {
0061   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_DONT_CHANGE, 0, 0, 0, 0),
0062   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI1_0, 1, 0, 1, 0),
0063   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI1_1, 1, 0, 1, 1),
0064   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_I2C1_0, 1, 1, 1, 0),
0065   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_I2C1_1, 1, 1, 1, 1),
0066   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART1_0, 1, 2, 1, 0),
0067   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART1_1, 1, 2, 1, 1),
0068   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART2_0, 1, 3, 1, 0),
0069   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART2_1, 1, 3, 1, 1),
0070   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART3_0, 1, 4, 2, 0),
0071   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART3_1, 1, 4, 2, 1),
0072   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART3_3, 1, 4, 2, 3),
0073   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_0, 1, 6, 2, 0),
0074   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_1, 1, 6, 2, 1),
0075   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_3, 1, 6, 2, 3),
0076   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_0, 1, 8, 2, 0),
0077   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_1, 1, 8, 2, 1),
0078   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_2, 1, 8, 2, 2),
0079   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_3, 1, 8, 2, 3),
0080   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM3_0, 1, 10, 2, 0),
0081   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM3_2, 1, 10, 2, 2),
0082   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM3_3, 1, 10, 2, 3),
0083   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM4_0, 1, 12, 1, 0),
0084   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM4_1, 1, 12, 1, 1),
0085   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN1_0, 1, 13, 2, 0),
0086   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN1_2, 1, 13, 2, 2),
0087   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN1_3, 1, 13, 2, 3),
0088   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PD01_0, 1, 15, 1, 0),
0089   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PD01_1, 1, 15, 1, 1),
0090   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM5CH4_0, 1, 16, 1, 0),
0091   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM5CH4_1, 1, 16, 1, 1),
0092   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0, 1, 17, 1, 0),
0093   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1, 1, 17, 1, 1),
0094   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGREG_0, 1, 18, 1, 0),
0095   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGREG_1, 1, 18, 1, 1),
0096   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0, 1, 19, 1, 0),
0097   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1, 1, 19, 1, 1),
0098   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGREG_0, 1, 20, 1, 0),
0099   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGREG_1, 1, 20, 1, 1),
0100   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ETH_0, 1, 21, 1, 0),
0101   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ETH_1, 1, 21, 1, 1),
0102   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN2_0, 1, 22, 1, 0),
0103   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN2_1, 1, 22, 1, 1),
0104   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MII_RMII_0, 1, 23, 1, 0),
0105   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MII_RMII_1, 1, 23, 1, 1),
0106   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_0, 1, 24, 3, 0),
0107   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_1, 1, 24, 3, 1),
0108   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_2, 1, 24, 3, 2),
0109   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_4, 1, 24, 3, 4),
0110   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI3_0, 1, 28, 1, 0),
0111   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI3_1, 1, 28, 1, 1),
0112   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2ITR1_0, 1, 29, 1, 0),
0113   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2ITR1_1, 1, 29, 1, 1),
0114   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PTP_PPS_0, 1, 30, 1, 0),
0115   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PTP_PPS_1, 1, 30, 1, 1),
0116   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM15_0, 6, 0, 1, 0),
0117   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM15_1, 6, 0, 1, 1),
0118   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM16_0, 6, 1, 1, 0),
0119   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM16_1, 6, 1, 1, 1),
0120   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM17_0, 6, 2, 1, 0),
0121   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM17_1, 6, 2, 1, 1),
0122   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CEC_0, 6, 3, 1, 0),
0123   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CEC_1, 6, 3, 1, 1),
0124   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_DMA_0, 6, 4, 1, 0),
0125   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_DMA_1, 6, 4, 1, 1),
0126   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM9_0, 6, 5, 1, 0),
0127   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM9_1, 6, 5, 1, 1),
0128   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM10_0, 6, 6, 1, 0),
0129   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM10_1, 6, 6, 1, 1),
0130   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM11_0, 6, 7, 1, 0),
0131   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM11_1, 6, 7, 1, 1),
0132   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM13_0, 6, 8, 1, 0),
0133   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM13_1, 6, 8, 1, 1),
0134   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM14_0, 6, 9, 1, 0),
0135   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM14_1, 6, 9, 1, 1),
0136   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_FSMC_0, 6, 10, 1, 0),
0137   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_FSMC_1, 6, 10, 1, 1),
0138   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0, 6, 11, 1, 0),
0139   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1, 6, 11, 1, 1),
0140   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM12_0, 6, 12, 1, 0),
0141   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM12_1, 6, 12, 1, 1),
0142   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MISC_0, 6, 13, 1, 0),
0143   STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MISC_1, 6, 13, 1, 1),
0144 };
0145
0146 static void set_remap_config(stm32f4_gpio_remap remap)
0147 {
0148   if(remap != STM32F4_GPIO_REMAP_DONT_CHANGE)
0149   {
0150     stm32f4_afio_remap_entry entry = stm32f4_afio_remap_table[remap];
0151     volatile stm32f4_afio *afio = STM32F4_AFIO;
0152     volatile uint32_t *reg = ((uint32_t*) afio) + entry.afio_reg;
0153     uint32_t mask = (1 << entry.width) - 1;
0154     uint32_t value = *reg;
0155
0156     value &= mask << entry.start;
0157     value |= entry.value << entry.start;
0158
0159     *reg = value;
0160   }
0161 }
0162
0163 #endif /* STM32F4_FAMILY_F10XXX */
0164
0165 static void set_config(unsigned pin, const stm32f4_gpio_config *config)
0166 {
0167   unsigned port = STM32F4_GPIO_PORT_OF_PIN(pin);
0168   volatile stm32f4_gpio *gpio = STM32F4_GPIO(port);
0169   unsigned index = STM32F4_GPIO_INDEX_OF_PIN(pin);
0170   rtems_interrupt_level level;
0171   int set_or_clear_offset = config->fields.output ? 0 : 16;
0172 #ifdef STM32F4_FAMILY_F4XXXX
0173   unsigned af_reg = index >> 3;
0174   unsigned af_index = index & 0x7;
0175
0176   rtems_interrupt_disable(level);
0177   gpio->bsrr = 1U << (index + set_or_clear_offset);
0178   clear_and_set(&gpio->pupdr, index, 2, config->fields.pupd);
0179   clear_and_set(&gpio->otyper, index, 1, config->fields.otype);
0180   clear_and_set(&gpio->ospeedr, index, 2, config->fields.ospeed);
0181   clear_and_set(&gpio->afr [af_reg], af_index, 4, config->fields.af);
0182   clear_and_set(&gpio->moder, index, 2, config->fields.mode);
0183   rtems_interrupt_enable(level);
0184
0185 #endif /* STM32F4_FAMILY_F4XXXX */
0186 #ifdef STM32F4_FAMILY_F10XXX
0187   unsigned cr_reg = index >> 3;
0188   unsigned cr_index = index & 0x7;
0189
0190   rtems_interrupt_disable(level);
0191   gpio->bsrr = 1U << (index + set_or_clear_offset);
0192   clear_and_set(&gpio->cr[cr_reg], cr_index, 4,
0193     (config->fields.cnf << 2) | config->fields.mode);
0194   set_remap_config(config->fields.remap);
0195   rtems_interrupt_enable(level);
0196
0197 #endif /* STM32F4_FAMILY_F10XXX */
0198 }
0199
0200 void stm32f4_gpio_set_config(const stm32f4_gpio_config *config)
0201 {
0202   int current = config->fields.pin_first;
0203   int last = config->fields.pin_last;
0204
0205 #ifdef STM32F4_FAMILY_F10XXX
0206   stm32f4_rcc_set_clock(STM32F4_RCC_AFIO, true);
0207 #endif /* STM32F4_FAMILY_F10XXX */
0208
0209   while (current <= last) {
0210     stm32f4_gpio_set_clock(current, true);
0211     set_config(current, config);
0212     ++current;
0213   }
0214 }
0215
0216 void stm32f4_gpio_set_config_array(const stm32f4_gpio_config *configs)
0217 {
0218   stm32f4_gpio_config terminal = STM32F4_GPIO_CONFIG_TERMINAL;
0219
0220   while (configs->value != terminal.value) {
0221     stm32f4_gpio_set_config(configs);
0222     ++configs;
0223   }
0224 }
0225
0226 void stm32f4_gpio_set_output(int pin, bool set)
0227 {
0228   int port = STM32F4_GPIO_PORT_OF_PIN(pin);
0229   volatile stm32f4_gpio *gpio = STM32F4_GPIO(port);
0230   int index = STM32F4_GPIO_INDEX_OF_PIN(pin);
0231   int set_or_clear_offset = set ? 0 : 16;
0232
0233   gpio->bsrr = 1U << (index + set_or_clear_offset);
0234 }
0235
0236 bool stm32f4_gpio_get_input(int pin)
0237 {
0238   int port = STM32F4_GPIO_PORT_OF_PIN(pin);
0239   volatile stm32f4_gpio *gpio = STM32F4_GPIO(port);
0240   int index = STM32F4_GPIO_INDEX_OF_PIN(pin);
0241
0242   return (gpio->idr & (1U << index)) != 0;
0243 }