include/bsp/stm32f4xxxx_tim.h

0001 /*
0002  * Copyright (c) 2013 Chris Nott.  All rights reserved.
0003  *
0004  *  Virtual Logic
0005  *  21-25 King St.
0006  *  Rockdale NSW 2216
0007  *  Australia
0008  *  <rtems@vl.com.au>
0009  *
0010  * The license and distribution terms for this file may be
0011  * found in the file LICENSE in this distribution or at
0012  * http://www.rtems.org/license/LICENSE.
0013  */
0014
0015 #ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H
0016 #define LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H
0017
0018 #include <bsp/utility.h>
0019
0020 struct stm32f4_tim_s {
0021   uint16_t cr1; // Control register 1
0022 #define STM32F4_TIMER_CR1_CKD_DIV           0x0300
0023 #define STM32F4_TIMER_CR1_CKD_DIV1          0x0000
0024 #define STM32F4_TIMER_CR1_CKD_DIV2          0x0100
0025 #define STM32F4_TIMER_CR1_CKD_DIV3          0x0200
0026 #define STM32F4_TIMER_CR1_ARPE              BSP_BIT16(7)
0027 #define STM32F4_TIMER_CR1_CMS               0x0060
0028 #define STM32F4_TIMER_CR1_CMS_EDGE          0x0000
0029 #define STM32F4_TIMER_CR1_CMS_CENTER1       0x0020
0030 #define STM32F4_TIMER_CR1_CMS_CENTER2       0x0040
0031 #define STM32F4_TIMER_CR1_CMS_CENTER3       0x0060
0032 #define STM32F4_TIMER_CR1_DIR               BSP_BIT16(4)
0033 #define STM32F4_TIMER_CR1_DIR_UP            0x0000
0034 #define STM32F4_TIMER_CR1_DIR_DOWN          0x0010
0035 #define STM32F4_TIMER_CR1_DIR_OPM           0x0008
0036 #define STM32F4_TIMER_CR1_DIR_OPM_CONT      0x0000
0037 #define STM32F4_TIMER_CR1_DIR_OPM_STOP      0x0008
0038 #define STM32F4_TIMER_CR1_DIR_URS           0x0004
0039 #define STM32F4_TIMER_CR1_DIR_UDIS          0x0002
0040 #define STM32F4_TIMER_CR1_DIR_UDIS_EN       0x0000
0041 #define STM32F4_TIMER_CR1_DIR_UDIS_DIS      0x0002
0042 #define STM32F4_TIMER_CR1_CEN               0x0001
0043   uint16_t reserved_02;
0044   uint16_t cr2; // Control register 2
0045   uint16_t reserved_06;
0046   uint16_t smcr;  // Slave mode control register
0047   uint16_t reserved_0a;
0048   uint16_t dier;  // DMA / interrupt enable register
0049 #define STM32F4_TIMER_DIER_TDE              BSP_BIT16(14) // Trigger DMA request enable
0050 #define STM32F4_TIMER_DIER_CC4DE            BSP_BIT16(12) // Capture/compare 4 DMA request enable
0051 #define STM32F4_TIMER_DIER_CC3DE            BSP_BIT16(11) // Capture/compare 3 DMA request enable
0052 #define STM32F4_TIMER_DIER_CC2DE            BSP_BIT16(10) // Capture/compare 2 DMA request enable
0053 #define STM32F4_TIMER_DIER_CC1DE            BSP_BIT16(9)  // Capture/compare 1 DMA request enable
0054 #define STM32F4_TIMER_DIER_UDE              BSP_BIT16(8)  // Update DMA request enable
0055 #define STM32F4_TIMER_DIER_TIE              BSP_BIT16(6)  // Trigger interrupt enable
0056 #define STM32F4_TIMER_DIER_CC4IE            BSP_BIT16(4)  // Capture/compare 4 interrupt request enable
0057 #define STM32F4_TIMER_DIER_CC3IE            BSP_BIT16(3)  // Capture/compare 3 interrupt request enable
0058 #define STM32F4_TIMER_DIER_CC2IE            BSP_BIT16(2)  // Capture/compare 2 interrupt request enable
0059 #define STM32F4_TIMER_DIER_CC1IE            BSP_BIT16(1)  // Capture/compare 1 interrupt request enable
0060 #define STM32F4_TIMER_DIER_UIE              BSP_BIT16(0)  // Update interrupt request enable
0061
0062   uint16_t reserved_0e;
0063   uint16_t sr;  // Status register
0064 #define STM32F4_TIMER_SR_CC4OF              BSP_BIT16(12) // Capture/compare 4 overcapture flag
0065 #define STM32F4_TIMER_SR_CC3OF              BSP_BIT16(11) // Capture/compare 3 overcapture flag
0066 #define STM32F4_TIMER_SR_CC2OF              BSP_BIT16(10) // Capture/compare 2 overcapture flag
0067 #define STM32F4_TIMER_SR_CC1OF              BSP_BIT16(9)  // Capture/compare 1 overcapture flag
0068 #define STM32F4_TIMER_SR_TIF                BSP_BIT16(6)  // Trigger interrupt flag
0069 #define STM32F4_TIMER_SR_CC4IF              BSP_BIT16(4)  // Capture/compare 4 interrupt flag
0070 #define STM32F4_TIMER_SR_CC3IF              BSP_BIT16(3)  // Capture/compare 3 interrupt flag
0071 #define STM32F4_TIMER_SR_CC2IF              BSP_BIT16(2)  // Capture/compare 2 interrupt flag
0072 #define STM32F4_TIMER_SR_CC1IF              BSP_BIT16(1)  // Capture/compare 1 interrupt flag
0073 #define STM32F4_TIMER_SR_UIF                BSP_BIT16(0)  // Update interrupt flag
0074   uint16_t reserved_12;
0075   uint16_t egr; // Event generation register
0076 #define STM32F4_TIMER_EGR_TG                BSP_BIT16(6)  // Trigger event
0077 #define STM32F4_TIMER_EGR_CC4G              BSP_BIT16(4)  // Capture/compare 4 event
0078 #define STM32F4_TIMER_EGR_CC3G              BSP_BIT16(3)  // Capture/compare 3 generation)
0079 #define STM32F4_TIMER_EGR_CC2G              BSP_BIT16(2)  // Capture/compare 2 generation)
0080 #define STM32F4_TIMER_EGR_CC1G              BSP_BIT16(1)  // Capture/compare 1 generation)
0081 #define STM32F4_TIMER_EGR_UG                BSP_BIT16(0)  // Update event
0082   uint16_t reserved_16;
0083   uint16_t ccmr1; // Capture / compare mode register 1
0084 #define STM32F4_TIMER_CCMR1_OC2CE           BSP_BIT16(15) // Output compare 2 clear enable
0085 #define STM32F4_TIMER_CCMR1_OC2M(val)       BSP_FLD16(val, 12, 14)
0086 #define STM32F4_TIMER_CCMR1_OC2M_GET(reg)   BSP_FLD16GET(reg, 12, 14)
0087 #define STM32F4_TIMER_CCMR1_OC2M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14)
0088 #define STM32F4_TIMER_CCMR1_OC2M_FROZEN     STM32F4_TIMER_CCMR1_OC2M(0)
0089 #define STM32F4_TIMER_CCMR1_OC2M_ACTIVE     STM32F4_TIMER_CCMR1_OC2M(1)
0090 #define STM32F4_TIMER_CCMR1_OC2M_INACTIVE   STM32F4_TIMER_CCMR1_OC2M(2)
0091 #define STM32F4_TIMER_CCMR1_OC2M_TOGGLE     STM32F4_TIMER_CCMR1_OC2M(3)
0092 #define STM32F4_TIMER_CCMR1_OC2M_FORCE_LOW  STM32F4_TIMER_CCMR1_OC2M(4)
0093 #define STM32F4_TIMER_CCMR1_OC2M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC2M(5)
0094 #define STM32F4_TIMER_CCMR1_OC2M_PWM1       STM32F4_TIMER_CCMR1_OC2M(6)
0095 #define STM32F4_TIMER_CCMR1_OC2M_PWM2       STM32F4_TIMER_CCMR1_OC2M(7)
0096 #define STM32F4_TIMER_CCMR1_OC2PE           BSP_BIT16(11) // Output compare 2 preload enable
0097 #define STM32F4_TIMER_CCMR1_OC2FE           BSP_BIT16(10) // Output compare 2 fast enable
0098 #define STM32F4_TIMER_CCMR1_CC2S(val)       BSP_FLD16(val, 8, 9)
0099 #define STM32F4_TIMER_CCMR1_CC2S_GET(reg)   BSP_FLD16GET(reg, 8, 9)
0100 #define STM32F4_TIMER_CCMR1_CC2S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9)
0101 #define STM32F4_TIMER_CCMR1_CC2S_OUTPUT     STM32F4_TIMER_CCMR1_OC2S(0)
0102 #define STM32F4_TIMER_CCMR1_CC2S_TI2        STM32F4_TIMER_CCMR1_OC2S(1)
0103 #define STM32F4_TIMER_CCMR1_CC2S_TI1        STM32F4_TIMER_CCMR1_OC2S(2)
0104 #define STM32F4_TIMER_CCMR1_CC2S_TRC        STM32F4_TIMER_CCMR1_OC2S(3)
0105 #define STM32F4_TIMER_CCMR1_OC1CE           BSP_BIT16(7)  // Output compare 1 clear enable
0106 #define STM32F4_TIMER_CCMR1_OC1M(val)       BSP_FLD16(val, 4, 6)
0107 #define STM32F4_TIMER_CCMR1_OC1M_GET(reg)   BSP_FLD16GET(reg, 4, 6)
0108 #define STM32F4_TIMER_CCMR1_OC1M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6)
0109 #define STM32F4_TIMER_CCMR1_OC1M_FROZEN     STM32F4_TIMER_CCMR1_OC1M(0)
0110 #define STM32F4_TIMER_CCMR1_OC1M_ACTIVE     STM32F4_TIMER_CCMR1_OC1M(1)
0111 #define STM32F4_TIMER_CCMR1_OC1M_INACTIVE   STM32F4_TIMER_CCMR1_OC1M(2)
0112 #define STM32F4_TIMER_CCMR1_OC1M_TOGGLE     STM32F4_TIMER_CCMR1_OC1M(3)
0113 #define STM32F4_TIMER_CCMR1_OC1M_FORCE_LOW  STM32F4_TIMER_CCMR1_OC1M(4)
0114 #define STM32F4_TIMER_CCMR1_OC1M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC1M(5)
0115 #define STM32F4_TIMER_CCMR1_OC1M_PWM1       STM32F4_TIMER_CCMR1_OC1M(6)
0116 #define STM32F4_TIMER_CCMR1_OC1M_PWM2       STM32F4_TIMER_CCMR1_OC1M(7)
0117 #define STM32F4_TIMER_CCMR1_OC1PE           BSP_BIT16(3)  // Output compare 1 preload enable
0118 #define STM32F4_TIMER_CCMR1_OC1FE           BSP_BIT16(2)  // Output compare 1 fast enable
0119 #define STM32F4_TIMER_CCMR1_CC1S(val)       BSP_FLD16(val, 0, 1)
0120 #define STM32F4_TIMER_CCMR1_CC1S_GET(reg)   BSP_FLD16GET(reg, 0, 1)
0121 #define STM32F4_TIMER_CCMR1_CC1S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1)
0122 #define STM32F4_TIMER_CCMR1_CC1S_OUTPUT     STM32F4_TIMER_CCMR1_OC1S(0)
0123 #define STM32F4_TIMER_CCMR1_CC1S_TI2        STM32F4_TIMER_CCMR1_OC1S(1)
0124 #define STM32F4_TIMER_CCMR1_CC1S_TI1        STM32F4_TIMER_CCMR1_OC1S(2)
0125 #define STM32F4_TIMER_CCMR1_CC1S_TRC        STM32F4_TIMER_CCMR1_OC1S(3)
0126   uint16_t reserved_1a;
0127   uint16_t ccmr2; // Capture / compare mode register 2
0128 #define STM32F4_TIMER_CCMR2_OC4CE           BSP_BIT16(15) // Output compare 4 clear enable
0129 #define STM32F4_TIMER_CCMR2_OC4M(val)       BSP_FLD16(val, 12, 14)
0130 #define STM32F4_TIMER_CCMR2_OC4M_GET(reg)   BSP_FLD16GET(reg, 12, 14)
0131 #define STM32F4_TIMER_CCMR2_OC4M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14)
0132 #define STM32F4_TIMER_CCMR2_OC4M_FROZEN     STM32F4_TIMER_CCMR2_OC4M(0)
0133 #define STM32F4_TIMER_CCMR2_OC4M_ACTIVE     STM32F4_TIMER_CCMR2_OC4M(1)
0134 #define STM32F4_TIMER_CCMR2_OC4M_INACTIVE   STM32F4_TIMER_CCMR2_OC4M(2)
0135 #define STM32F4_TIMER_CCMR2_OC4M_TOGGLE     STM32F4_TIMER_CCMR2_OC4M(3)
0136 #define STM32F4_TIMER_CCMR2_OC4M_FORCE_LOW  STM32F4_TIMER_CCMR2_OC4M(4)
0137 #define STM32F4_TIMER_CCMR2_OC4M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC4M(5)
0138 #define STM32F4_TIMER_CCMR2_OC4M_PWM1       STM32F4_TIMER_CCMR2_OC4M(6)
0139 #define STM32F4_TIMER_CCMR2_OC4M_PWM2       STM32F4_TIMER_CCMR2_OC4M(7)
0140 #define STM32F4_TIMER_CCMR2_OC4PE           BSP_BIT16(11) // Output compare 4 preload enable
0141 #define STM32F4_TIMER_CCMR2_OC4FE           BSP_BIT16(10) // Output compare 4 fast enable
0142 #define STM32F4_TIMER_CCMR2_CC4S(val)       BSP_FLD16(val, 8, 9)
0143 #define STM32F4_TIMER_CCMR2_CC4S_GET(reg)   BSP_FLD16GET(reg, 8, 9)
0144 #define STM32F4_TIMER_CCMR2_CC4S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9)
0145 #define STM32F4_TIMER_CCMR2_CC4S_OUTPUT     STM32F4_TIMER_CCMR2_OC4S(0)
0146 #define STM32F4_TIMER_CCMR2_CC4S_TI2        STM32F4_TIMER_CCMR2_OC4S(1)
0147 #define STM32F4_TIMER_CCMR2_CC4S_TI1        STM32F4_TIMER_CCMR2_OC4S(2)
0148 #define STM32F4_TIMER_CCMR2_CC4S_TRC        STM32F4_TIMER_CCMR2_OC4S(3)
0149 #define STM32F4_TIMER_CCMR2_OC3CE           BSP_BIT16(7)  // Output compare 3 clear enable
0150 #define STM32F4_TIMER_CCMR2_OC3M(val)       BSP_FLD16(val, 4, 6)
0151 #define STM32F4_TIMER_CCMR2_OC3M_GET(reg)   BSP_FLD16GET(reg, 4, 6)
0152 #define STM32F4_TIMER_CCMR2_OC3M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6)
0153 #define STM32F4_TIMER_CCMR2_OC3M_FROZEN     STM32F4_TIMER_CCMR2_OC3M(0)
0154 #define STM32F4_TIMER_CCMR2_OC3M_ACTIVE     STM32F4_TIMER_CCMR2_OC3M(1)
0155 #define STM32F4_TIMER_CCMR2_OC3M_INACTIVE   STM32F4_TIMER_CCMR2_OC3M(2)
0156 #define STM32F4_TIMER_CCMR2_OC3M_TOGGLE     STM32F4_TIMER_CCMR2_OC3M(3)
0157 #define STM32F4_TIMER_CCMR2_OC3M_FORCE_LOW  STM32F4_TIMER_CCMR2_OC3M(4)
0158 #define STM32F4_TIMER_CCMR2_OC3M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC3M(5)
0159 #define STM32F4_TIMER_CCMR2_OC3M_PWM1       STM32F4_TIMER_CCMR2_OC3M(6)
0160 #define STM32F4_TIMER_CCMR2_OC3M_PWM2       STM32F4_TIMER_CCMR2_OC3M(7)
0161 #define STM32F4_TIMER_CCMR2_OC3PE           BSP_BIT16(3)  // Output compare 3 preload enable
0162 #define STM32F4_TIMER_CCMR2_OC3FE           BSP_BIT16(2)  // Output compare 3 fast enable
0163 #define STM32F4_TIMER_CCMR2_CC3S(val)       BSP_FLD16(val, 0, 1)
0164 #define STM32F4_TIMER_CCMR2_CC3S_GET(reg)   BSP_FLD16GET(reg, 0, 1)
0165 #define STM32F4_TIMER_CCMR2_CC3S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1)
0166 #define STM32F4_TIMER_CCMR2_CC3S_OUTPUT     STM32F4_TIMER_CCMR2_OC3S(0)
0167 #define STM32F4_TIMER_CCMR2_CC3S_TI2        STM32F4_TIMER_CCMR2_OC3S(1)
0168 #define STM32F4_TIMER_CCMR2_CC3S_TI1        STM32F4_TIMER_CCMR2_OC3S(2)
0169 #define STM32F4_TIMER_CCMR2_CC3S_TRC        STM32F4_TIMER_CCMR2_OC3S(3)
0170   uint16_t reserved_1e;
0171   uint16_t ccer;  // Capture / compare enable register
0172 #define STM32F4_TIMER_CCER_CC4NP            BSP_BIT16(15) // Capture / compare 4 output polarity
0173 #define STM32F4_TIMER_CCER_CC4P             BSP_BIT16(13) // Capture / compare 4 output polarity
0174 #define STM32F4_TIMER_CCER_CC4E             BSP_BIT16(12) // Capture / compare 4 output enable
0175 #define STM32F4_TIMER_CCER_CC3NP            BSP_BIT16(11) // Capture / compare 3 output polarity
0176 #define STM32F4_TIMER_CCER_CC3P             BSP_BIT16(9)  // Capture / compare 3 output polarity
0177 #define STM32F4_TIMER_CCER_CC3E             BSP_BIT16(8)  // Capture / compare 3 output enable
0178 #define STM32F4_TIMER_CCER_CC2NP            BSP_BIT16(7)  // Capture / compare 2 output polarity
0179 #define STM32F4_TIMER_CCER_CC2P             BSP_BIT16(5)  // Capture / compare 2 output polarity
0180 #define STM32F4_TIMER_CCER_CC2E             BSP_BIT16(4)  // Capture / compare 2 output enable
0181 #define STM32F4_TIMER_CCER_CC1NP            BSP_BIT16(3)  // Capture / compare 1 output polarity
0182 #define STM32F4_TIMER_CCER_CC1P             BSP_BIT16(1)  // Capture / compare 1 output polarity
0183 #define STM32F4_TIMER_CCER_CC1E             BSP_BIT16(0)  // Capture / compare 1 output enable
0184   uint16_t reserved_22;
0185   uint32_t cnt; // Counter register
0186 #define STM32F4_TIMER_DR(val) BSP_FLD32(val, 0, 31)
0187 #define STM32F4_TIMER_DR_GET(reg) BSP_FLD32GET(reg, 0, 31)
0188 #define STM32F4_TIMER_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
0189   uint16_t psc; // Prescalar
0190   uint16_t reserved_2a;
0191   uint32_t arr; // Auto-reload register
0192   uint16_t rcr; // Repetition counter register
0193   uint16_t rserved_32;
0194   uint32_t ccr[4];// Capture / compare registers
0195   uint16_t bdtr;  // Break and dead-time register
0196   uint16_t reserved_46;
0197   uint16_t dcr; // DMA control register
0198   uint16_t reserved_4a;
0199   uint16_t dmar;  // DMA address for full transfer
0200   uint16_t reserved_4e;
0201   uint16_t or;  // Option register
0202   uint16_t reserved_52;
0203 } __attribute__ ((packed));
0204 typedef struct stm32f4_tim_s stm32f4_tim;
0205
0206 #endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H */