include/bsp/stm32f4xxxx_adc.h

0001 /*
0002  * Copyright (c) 2014 Chris Nott.  All rights reserved.
0003  *
0004  *  Virtual Logic
0005  *  21-25 King St.
0006  *  Rockdale NSW 2216
0007  *  Australia
0008  *  <rtems@vl.com.au>
0009  *
0010  * The license and distribution terms for this file may be
0011  * found in the file LICENSE in this distribution or at
0012  * http://www.rtems.org/license/LICENSE.
0013  */
0014
0015 #ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H
0016 #define LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H
0017
0018 #include <bsp/utility.h>
0019
0020 struct stm32f4_adc_chan_s {
0021     uint32_t sr;    // 0x00: Status register
0022 #define STM32F4_ADC_SR_OVR          BSP_BIT32(5)    // Overrun
0023 #define STM32F4_ADC_SR_STRT         BSP_BIT32(4)    // Regular channel start flag
0024 #define STM32F4_ADC_SR_JSTRT        BSP_BIT32(3)    // Injected channel start flag
0025 #define STM32F4_ADC_SR_JEOC         BSP_BIT32(2)    // Injected channel end of conversion
0026 #define STM32F4_ADC_SR_EOC          BSP_BIT32(1)    // Regular channel end of conversion
0027 #define STM32F4_ADC_SR_AWD          BSP_BIT32(0)    // Analog watchdog flag
0028
0029     uint32_t cr1;   // 0x04: Control register 1
0030 #define STM32F4_ADC_CR1_OVRIE       BSP_BIT32(26)   // Overrun interrupt enable
0031 #define STM32F4_ADC_CR1_RES(val)    BSP_FLD32(val, 24, 25)  // Resolution
0032 #define STM32F4_ADC_CR1_RES_GET(reg)    BSP_FLD32GET(reg, 24, 25)
0033 #define STM32F4_ADC_CR1_RES_SET(reg, val)   BSP_FLD32SET(reg, val, 24, 25)
0034 #define ADC_CR1_RES_12BIT   0
0035 #define ADC_CR1_RES_10BIT   1
0036 #define ADC_CR1_RES_8BIT    2
0037 #define ADC_CR1_RES_6BIT    3
0038 #define STM32F4_ADC_CR1_AWDEN       BSP_BIT32(23)   // Analog watchdog enable on regular channels
0039 #define STM32F4_ADC_CR1_JAWDEN      BSP_BIT32(22)   // Analog watchdog enable on injected channels
0040 #define STM32F4_ADC_CR1_DISCNUM(val)    BSP_FLD32(val, 13, 15)  // Discontinuous mode channel count
0041 #define STM32F4_ADC_CR1_DISCNUM_GET(reg)    BSP_FLD32GET(reg, 13, 15)
0042 #define STM32F4_ADC_CR1_DISCNUM_SET(reg, val)   BSP_FLD32SET(reg, val, 13, 15)
0043 #define STM32F4_ADC_CR1_JDISCEN     BSP_BIT32(12)   // Discontinous mode on injected channels
0044 #define STM32F4_ADC_CR1_DISCEN      BSP_BIT32(11)   // Discontinous mode on regular channels
0045 #define STM32F4_ADC_CR1_JAUTO       BSP_BIT32(10)   // Automated injected group conversion
0046 #define STM32F4_ADC_CR1_AWDSGL      BSP_BIT32(9)    // Enable watchdog on single channel in scan mode
0047 #define STM32F4_ADC_CR1_SCAN        BSP_BIT32(8)    // Scan mode
0048 #define STM32F4_ADC_CR1_JEOCIE      BSP_BIT32(7)    // Interrupt enable for injected channels
0049 #define STM32F4_ADC_CR1_AWDIE       BSP_BIT32(6)    // Analog watchdog interrupt enable
0050 #define STM32F4_ADC_CR1_EOCIE       BSP_BIT32(5)    // Interrupt enable for EOC
0051 #define STM32F4_ADC_CR1_AWDCH(val)  BSP_FLD32(val, 0, 4)    // Analog watchdog channel select bits
0052 #define STM32F4_ADC_CR1_AWDCH_GET(reg)  BSP_FLD32GET(reg, 0, 4)
0053 #define STM32F4_ADC_CR1_AWDCH_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
0054
0055     uint32_t cr2;   // 0x08: Control register 2
0056 #define STM32F4_ADC_CR2_SWSTART     BSP_BIT32(30)   // Start conversion of regular channels
0057 #define STM32F4_ADC_CR2_EXTEN(val)  BSP_FLD32(val, 28, 29)  // External trigger enable for regular channels
0058 #define STM32F4_ADC_CR2_EXTEN_GET(reg)  BSP_FLD32GET(reg, 28, 29)
0059 #define STM32F4_ADC_CR2_EXTEN_SET(reg, val) BSP_FLD32SET(reg, val, 28, 29)
0060 #define STM32F4_ADC_CR2_JEXTEN(val) BSP_FLD32(val, 20, 21)  // External trigger enable for injected channels
0061 #define STM32F4_ADC_CR2_JEXTEN_GET(reg) BSP_FLD32GET(reg, 20, 21)
0062 #define STM32F4_ADC_CR2_JEXTEN_SET(reg, val)    BSP_FLD32SET(reg, val, 20, 21)
0063 #define ADC_CR2_TRIGGER_DISABLE 0
0064 #define ADC_CR2_TRIGGER_RISING 1
0065 #define ADC_CR2_TRIGGER_FALLING 2
0066 #define ADC_CR2_TRIGGER_BOTH 3
0067 #define STM32F4_ADC_CR2_EXTSEL(val) BSP_FLD32(val, 24, 27)  // External event select for regular group
0068 #define STM32F4_ADC_CR2_EXTSEL_GET(reg) BSP_FLD32GET(reg, 24, 27)
0069 #define STM32F4_ADC_CR2_EXTSEL_SET(reg, val)    BSP_FLD32SET(reg, val, 24, 27)
0070 #define ADC_CR2_EVT_TIMER1_CC1 0x0
0071 #define ADC_CR2_EVT_TIMER1_CC2 0x1
0072 #define ADC_CR2_EVT_TIMER1_CC3 0x2
0073 #define ADC_CR2_EVT_TIMER2_CC2 0x3
0074 #define ADC_CR2_EVT_TIMER2_CC3 0x4
0075 #define ADC_CR2_EVT_TIMER2_CC4 0x5
0076 #define ADC_CR2_EVT_TIMER2_TRGO 0x6
0077 #define ADC_CR2_EVT_TIMER3_CC1 0x7
0078 #define ADC_CR2_EVT_TIMER3_TRGO 0x8
0079 #define ADC_CR2_EVT_TIMER4_CC1 0x9
0080 #define ADC_CR2_EVT_TIMER5_CC1 0xa
0081 #define ADC_CR2_EVT_TIMER5_CC2 0xb
0082 #define ADC_CR2_EVT_TIMER5_CC3 0xc
0083 #define ADC_CR2_EVT_TIMER8_CC1 0xd
0084 #define ADC_CR2_EVT_TIMER8_TRGO 0xe
0085 #define ADC_CR2_EVT_EXTI_11 0xf
0086 #define STM32F4_ADC_CR2_JSWSTART    BSP_BIT32(22)   // Start conversion of injected channels
0087 #define STM32F4_ADC_CR2_JEXTSEL(val)    BSP_FLD32(val, 16, 19)  // External event select for injected group
0088 #define STM32F4_ADC_CR2_JEXTSEL_GET(reg)    BSP_FLD32GET(reg, 16, 19)
0089 #define STM32F4_ADC_CR2_JEXTSEL_SET(reg, val)   BSP_FLD32SET(reg, val, 16, 19)
0090 #define ADC_CR2_JEVT_TIMER1_CC4 0x0
0091 #define ADC_CR2_JEVT_TIMER1_TRGO 0x1
0092 #define ADC_CR2_JEVT_TIMER2_CC1 0x2
0093 #define ADC_CR2_JEVT_TIMER2_TRGO 0x3
0094 #define ADC_CR2_JEVT_TIMER3_CC2 0x4
0095 #define ADC_CR2_JEVT_TIMER3_CC4 0x5
0096 #define ADC_CR2_JEVT_TIMER4_CC1 0x6
0097 #define ADC_CR2_JEVT_TIMER4_CC2 0x7
0098 #define ADC_CR2_JEVT_TIMER4_CC3 0x8
0099 #define ADC_CR2_JEVT_TIMER4_TRGO 0x9
0100 #define ADC_CR2_JEVT_TIMER5_CC4 0xa
0101 #define ADC_CR2_JEVT_TIMER5_TRGO 0xb
0102 #define ADC_CR2_JEVT_TIMER8_CC2 0xc
0103 #define ADC_CR2_JEVT_TIMER8_CC3 0xd
0104 #define ADC_CR2_JEVT_TIMER8_CC4 0xe
0105 #define ADC_CR2_JEVT_EXTI_15 0xf
0106 #define STM32F4_ADC_CR2_ALIGN   BSP_BIT32(11)   // Data alignment
0107 #define STM32F4_ADC_CR2_ALIGN_RIGHT     0
0108 #define STM32F4_ADC_CR2_ALIGN_LEFT      STM32F4_ADC_CR2_ALIGN
0109 #define STM32F4_ADC_CR2_EOCS    BSP_BIT32(10)   // End of conversion selection
0110 #define STM32F4_ADC_CR2_DDS     BSP_BIT32(9)    // DMA disable selection (single ADC mode)
0111 #define STM32F4_ADC_CR2_DMA     BSP_BIT32(8)    // DMA access mode (single ADC)
0112 #define STM32F4_ADC_CR2_CONT    BSP_BIT32(1)    // Continuous conversion
0113 #define STM32F4_ADC_CR2_ADON    BSP_BIT32(0)    // A/D converter ON
0114
0115     uint32_t smpr1; // 0x0C: Sample time register 1
0116 #define ADC_SAMPLE_3CYCLE   0
0117 #define ADC_SAMPLE_15CYCLE  1
0118 #define ADC_SAMPLE_28CYCLE  2
0119 #define ADC_SAMPLE_56CYCLE  3
0120 #define ADC_SAMPLE_84CYCLE  4
0121 #define ADC_SAMPLE_112CYCLE 5
0122 #define ADC_SAMPLE_144CYCLE 6
0123 #define ADC_SAMPLE_480CYCLE 7
0124 #define STM32F4_ADC_SMP18(val)  BSP_FLD32(val, 24, 26)  // Channel 18 sampling time selection
0125 #define STM32F4_ADC_SMP18_GET(reg)  BSP_FLD32GET(reg, 24, 26)
0126 #define STM32F4_ADC_SMP18_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26)
0127 #define STM32F4_ADC_SMP17(val)  BSP_FLD32(val, 21, 23)  // Channel 17 sampling time selection
0128 #define STM32F4_ADC_SMP17_GET(reg)  BSP_FLD32GET(reg, 21, 23)
0129 #define STM32F4_ADC_SMP17_SET(reg, val) BSP_FLD32SET(reg, val, 21, 23)
0130 #define STM32F4_ADC_SMP16(val)  BSP_FLD32(val, 18, 20)  // Channel 16 sampling time selection
0131 #define STM32F4_ADC_SMP16_GET(reg)  BSP_FLD32GET(reg, 18, 20)
0132 #define STM32F4_ADC_SMP16_SET(reg, val) BSP_FLD32SET(reg, val, 18, 20)
0133 #define STM32F4_ADC_SMP15(val)  BSP_FLD32(val, 15, 17)  // Channel 15 sampling time selection
0134 #define STM32F4_ADC_SMP15_GET(reg)  BSP_FLD32GET(reg, 15, 17)
0135 #define STM32F4_ADC_SMP15_SET(reg, val) BSP_FLD32SET(reg, val, 15, 17)
0136 #define STM32F4_ADC_SMP14(val)  BSP_FLD32(val, 12, 14)  // Channel 14 sampling time selection
0137 #define STM32F4_ADC_SMP14_GET(reg)  BSP_FLD32GET(reg, 12, 14)
0138 #define STM32F4_ADC_SMP14_SET(reg, val) BSP_FLD32SET(reg, val, 12, 14)
0139 #define STM32F4_ADC_SMP13(val)  BSP_FLD32(val, 9, 11)   // Channel 13 sampling time selection
0140 #define STM32F4_ADC_SMP13_GET(reg)  BSP_FLD32GET(reg, 9, 11)
0141 #define STM32F4_ADC_SMP13_SET(reg, val) BSP_FLD32SET(reg, val, 9, 11)
0142 #define STM32F4_ADC_SMP12(val)  BSP_FLD32(val, 6, 8)    // Channel 12 sampling time selection
0143 #define STM32F4_ADC_SMP12_GET(reg)  BSP_FLD32GET(reg, 6, 8)
0144 #define STM32F4_ADC_SMP12_SET(reg, val) BSP_FLD32SET(reg, val, 6, 8)
0145 #define STM32F4_ADC_SMP11(val)  BSP_FLD32(val, 3, 5)    // Channel 11 sampling time selection
0146 #define STM32F4_ADC_SMP11_GET(reg)  BSP_FLD32GET(reg, 3, 5)
0147 #define STM32F4_ADC_SMP11_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
0148 #define STM32F4_ADC_SMP10(val)  BSP_FLD32(val, 0, 2)    // Channel 10 sampling time selection
0149 #define STM32F4_ADC_SMP10_GET(reg)  BSP_FLD32GET(reg, 0, 2)
0150 #define STM32F4_ADC_SMP10_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
0151
0152     uint32_t smpr2;     // 0x10: Sample time register 2
0153 #define STM32F4_ADC_SMP9(val)   BSP_FLD32(val, 27, 29)  // Channel 9 sampling time selection
0154 #define STM32F4_ADC_SMP9_GET(reg)   BSP_FLD32GET(reg, 27, 29)
0155 #define STM32F4_ADC_SMP9_SET(reg, val)  BSP_FLD32SET(reg, val, 27, 29)
0156 #define STM32F4_ADC_SMP8(val)   BSP_FLD32(val, 24, 26)  // Channel 8 sampling time selection
0157 #define STM32F4_ADC_SMP8_GET(reg)   BSP_FLD32GET(reg, 24, 26)
0158 #define STM32F4_ADC_SMP8_SET(reg, val)  BSP_FLD32SET(reg, val, 24, 26)
0159 #define STM32F4_ADC_SMP7(val)   BSP_FLD32(val, 21, 23)  // Channel 7 sampling time selection
0160 #define STM32F4_ADC_SMP7_GET(reg)   BSP_FLD32GET(reg, 21, 23)
0161 #define STM32F4_ADC_SMP7_SET(reg, val)  BSP_FLD32SET(reg, val, 21, 23)
0162 #define STM32F4_ADC_SMP6(val)   BSP_FLD32(val, 18, 20)  // Channel 6 sampling time selection
0163 #define STM32F4_ADC_SMP6_GET(reg)   BSP_FLD32GET(reg, 18, 20)
0164 #define STM32F4_ADC_SMP6_SET(reg, val)  BSP_FLD32SET(reg, val, 18, 20)
0165 #define STM32F4_ADC_SMP5(val)   BSP_FLD32(val, 15, 17)  // Channel 5 sampling time selection
0166 #define STM32F4_ADC_SMP5_GET(reg)   BSP_FLD32GET(reg, 15, 17)
0167 #define STM32F4_ADC_SMP5_SET(reg, val)  BSP_FLD32SET(reg, val, 15, 17)
0168 #define STM32F4_ADC_SMP4(val)   BSP_FLD32(val, 12, 14)  // Channel 4 sampling time selection
0169 #define STM32F4_ADC_SMP4_GET(reg)   BSP_FLD32GET(reg, 12, 14)
0170 #define STM32F4_ADC_SMP4_SET(reg, val)  BSP_FLD32SET(reg, val, 12, 14)
0171 #define STM32F4_ADC_SMP3(val)   BSP_FLD32(val, 9, 11)   // Channel 3 sampling time selection
0172 #define STM32F4_ADC_SMP3_GET(reg)   BSP_FLD32GET(reg, 9, 11)
0173 #define STM32F4_ADC_SMP3_SET(reg, val)  BSP_FLD32SET(reg, val, 9, 11)
0174 #define STM32F4_ADC_SMP2(val)   BSP_FLD32(val, 6, 8)    // Channel 2 sampling time selection
0175 #define STM32F4_ADC_SMP2_GET(reg)   BSP_FLD32GET(reg, 6, 8)
0176 #define STM32F4_ADC_SMP2_SET(reg, val)  BSP_FLD32SET(reg, val, 6, 8)
0177 #define STM32F4_ADC_SMP1(val)   BSP_FLD32(val, 3, 5)    // Channel 1 sampling time selection
0178 #define STM32F4_ADC_SMP1_GET(reg)   BSP_FLD32GET(reg, 3, 5)
0179 #define STM32F4_ADC_SMP1_SET(reg, val)  BSP_FLD32SET(reg, val, 3, 5)
0180 #define STM32F4_ADC_SMP0(val)   BSP_FLD32(val, 0, 2)    // Channel 0 sampling time selection
0181 #define STM32F4_ADC_SMP0_GET(reg)   BSP_FLD32GET(reg, 0, 2)
0182 #define STM32F4_ADC_SMP0_SET(reg, val)  BSP_FLD32SET(reg, val, 0, 2)
0183
0184     uint32_t jofr[4];   // 0x14-0x20: Injected channel data offset registers
0185 #define STM32F4_ADC_JOFFSET(val)    BSP_FLD32(val, 0, 11)   // Data offset for injected channel
0186 #define STM32F4_ADC_JOFFSET_GET(reg)    BSP_FLD32GET(reg, 0, 11)
0187 #define STM32F4_ADC_JOFFSET_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 11)
0188
0189     uint32_t htr;       // 0x24: Watchdog higher threshold register
0190 #define STM32F4_ADC_HT(val) BSP_FLD32(val, 0, 11)   // Analog watchdog higher threshold
0191 #define STM32F4_ADC_HT_GET(reg) BSP_FLD32GET(reg, 0, 11)
0192 #define STM32F4_ADC_HT_SET(reg, val)    BSP_FLD32SET(reg, val, 0, 11)
0193
0194     uint32_t ltr;       // 0x28: Watchdog lower threshold register
0195 #define STM32F4_ADC_LT(val) BSP_FLD32(val, 0, 11)   // Analog watchdog lower threshold
0196 #define STM32F4_ADC_LT_GET(reg) BSP_FLD32GET(reg, 0, 11)
0197 #define STM32F4_ADC_LT_SET(reg, val)    BSP_FLD32SET(reg, val, 0, 11)
0198
0199     uint32_t sqr[3];    // 0x2c-0x34: Regular sequence registers
0200 #define STM32F4_ADC_SQR_L(val)  BSP_FLD32(val, 20, 23)  // Regular channel sequence length
0201 #define STM32F4_ADC_SQR_L_GET(reg)  BSP_FLD32GET(reg, 20, 23)
0202 #define STM32F4_ADC_SQR_L_SET(reg, val) BSP_FLD32SET(reg, val, 20, 23)
0203
0204     uint32_t jsqr;      // 0x38: Injected sequence register
0205 #define STM32F4_ADC_JSQR_JL(val)    BSP_FLD32(val, 20, 21)  // Injected sequence length
0206 #define STM32F4_ADC_JSQR_JL_GET(reg)    BSP_FLD32GET(reg, 20, 21)
0207 #define STM32F4_ADC_JSQR_JL_SET(reg, val)   BSP_FLD32SET(reg, val, 20, 21)
0208 #define STM32F4_ADC_JSQR_JSQ4(val)  BSP_FLD32(val, 15, 19)  // 4th conversion in injected sequence
0209 #define STM32F4_ADC_JSQR_JSQ4_GET(reg)  BSP_FLD32GET(reg, 15, 19)
0210 #define STM32F4_ADC_JSQR_JSQ4_SET(reg, val) BSP_FLD32SET(reg, val, 15, 19)
0211 #define STM32F4_ADC_JSQR_JSQ3(val)  BSP_FLD32(val, 10, 14)  // 3rd conversion in injected sequence
0212 #define STM32F4_ADC_JSQR_JSQ3_GET(reg)  BSP_FLD32GET(reg, 10, 14)
0213 #define STM32F4_ADC_JSQR_JSQ3_SET(reg, val) BSP_FLD32SET(reg, val, 10, 14)
0214 #define STM32F4_ADC_JSQR_JSQ2(val)  BSP_FLD32(val, 5, 9)    // 2nd conversion in injected sequence
0215 #define STM32F4_ADC_JSQR_JSQ2_GET(reg)  BSP_FLD32GET(reg, 5, 9)
0216 #define STM32F4_ADC_JSQR_JSQ2_SET(reg, val) BSP_FLD32SET(reg, val, 5, 9)
0217 #define STM32F4_ADC_JSQR_JSQ1(val)  BSP_FLD32(val, 0, 4)    // 1st conversion in injected sequence
0218 #define STM32F4_ADC_JSQR_JSQ1_GET(reg)  BSP_FLD32GET(reg, 0, 4)
0219 #define STM32F4_ADC_JSQR_JSQ1_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
0220
0221     uint32_t jdr[4];    // 0x3c-0x48: Injected data registers
0222 #define STM32F4_ADC_JDATA(val)  BSP_FLD32(val, 0, 15)   // Injected data
0223 #define STM32F4_ADC_JDATA_GET(reg)  BSP_FLD32GET(reg, 0, 15)
0224 #define STM32F4_ADC_JDATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
0225
0226     uint32_t dr;        // 0x4c: Regular data register
0227 #define STM32F4_ADC_DATA(val)   BSP_FLD32(val, 0, 15)   // Regular data
0228 #define STM32F4_ADC_DATA_GET(reg)   BSP_FLD32GET(reg, 0, 15)
0229 #define STM32F4_ADC_DATA_SET(reg, val)  BSP_FLD32SET(reg, val, 0, 15)
0230
0231 } __attribute__ ((packed));
0232 typedef struct stm32f4_adc_chan_s stm32f4_adc_chan;
0233
0234 struct stm32f4_adc_com_s {
0235     uint32_t csr;       // 0x00: Common status register
0236 #define STM32F4_ADC_CSR_OVR3    BSP_BIT32(21)   // Overrun flag ADC3
0237 #define STM32F4_ADC_CSR_STRT3   BSP_BIT32(20)   // Regular start flag ADC3
0238 #define STM32F4_ADC_CSR_JSTRT3  BSP_BIT32(19)   // Injected start flag ADC3
0239 #define STM32F4_ADC_CSR_JEOC3   BSP_BIT32(18)   // Injected channel end of conversion flag ADC3
0240 #define STM32F4_ADC_CSR_EOC3    BSP_BIT32(17)   // Channel end of conversion flag ADC3
0241 #define STM32F4_ADC_CSR_AWD3    BSP_BIT32(16)   // Analog watchdog flag ADC3
0242 #define STM32F4_ADC_CSR_OVR2    BSP_BIT32(13)   // Overrun flag ADC2
0243 #define STM32F4_ADC_CSR_STRT2   BSP_BIT32(12)   // Regular start flag ADC2
0244 #define STM32F4_ADC_CSR_JSTRT2  BSP_BIT32(11)   // Injected start flag ADC2
0245 #define STM32F4_ADC_CSR_JEOC2   BSP_BIT32(10)   // Injected channel end of conversion flag ADC2
0246 #define STM32F4_ADC_CSR_EOC2    BSP_BIT32(9)    // Channel end of conversion flag ADC2
0247 #define STM32F4_ADC_CSR_AWD2    BSP_BIT32(8)    // Analog watchdog flag ADC2
0248 #define STM32F4_ADC_CSR_OVR1    BSP_BIT32(5)    // Overrun flag ADC1
0249 #define STM32F4_ADC_CSR_STRT1   BSP_BIT32(4)    // Regular start flag ADC1
0250 #define STM32F4_ADC_CSR_JSTRT1  BSP_BIT32(3)    // Injected start flag ADC1
0251 #define STM32F4_ADC_CSR_JEOC1   BSP_BIT32(2)    // Injected channel end of conversion flag ADC1
0252 #define STM32F4_ADC_CSR_EOC1    BSP_BIT32(1)    // Channel end of conversion flag ADC1
0253 #define STM32F4_ADC_CSR_AWD1    BSP_BIT32(0)    // Analog watchdog flag ADC1
0254
0255     uint32_t ccr;       // 0x00: Common control register
0256 #define STM32F4_ADC_CCR_TSVREFE BSP_BIT32(23)   // Temp sensor and Vrefint enable
0257 #define STM32F4_ADC_CCR_VBATE   BSP_BIT32(22)   // Vbat enable
0258 #define STM32F4_ADC_CCR_ADCPRE(val) BSP_FLD32(val, 16, 17)  // ADC prescalar
0259 #define STM32F4_ADC_CCR_ADCPRE_GET(reg) BSP_FLD32GET(reg, 16, 17)
0260 #define STM32F4_ADC_CCR_ADCPRE_SET(reg, val)    BSP_FLD32SET(reg, val, 16, 17)
0261 #define ADC_ADCPRE_PCLK2_2 0
0262 #define ADC_ADCPRE_PCLK2_4 1
0263 #define ADC_ADCPRE_PCLK2_6 2
0264 #define ADC_ADCPRE_PCLK2_8 3
0265 #define STM32F4_ADC_CCR_DMA(val)    BSP_FLD32(val, 14, 15)  // DMA access mode for multi ADC
0266 #define STM32F4_ADC_CCR_DMA_GET(reg)    BSP_FLD32GET(reg, 14, 15)
0267 #define STM32F4_ADC_CCR_DMA_SET(reg, val)   BSP_FLD32SET(reg, val, 14, 15)
0268 #define ADC_DMA_DISABLE 0
0269 #define ADC_DMA_MODE1 1
0270 #define ADC_DMA_MODE2 2
0271 #define ADC_DMA_MODE3 3
0272 #define STM32F4_ADC_CCR_DDS BSP_BIT32(13)   // DMA disable selection
0273 #define STM32F4_ADC_CCR_DELAY(val)  BSP_FLD32(val, 8, 11)   // Delay between sampling phases
0274 #define STM32F4_ADC_CCR_DELAY_GET(reg)  BSP_FLD32GET(reg, 8, 11)
0275 #define STM32F4_ADC_CCR_DELAY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
0276 #define ADC_DELAY_5T 0
0277 #define ADC_DELAY_6T 1
0278 #define ADC_DELAY_7T 2
0279 #define ADC_DELAY_8T 3
0280 #define ADC_DELAY_9T 4
0281 #define ADC_DELAY_10T 5
0282 #define ADC_DELAY_11T 6
0283 #define ADC_DELAY_12T 7
0284 #define ADC_DELAY_13T 8
0285 #define ADC_DELAY_14T 9
0286 #define ADC_DELAY_15T 10
0287 #define ADC_DELAY_16T 11
0288 #define ADC_DELAY_17T 12
0289 #define ADC_DELAY_18T 13
0290 #define ADC_DELAY_19T 14
0291 #define ADC_DELAY_20T 15
0292 #define STM32F4_ADC_CCR_MULTI(val)  BSP_FLD32(val, 0, 4)    // Multi ADC mode
0293 #define STM32F4_ADC_CCR_MULTI_GET(reg)  BSP_FLD32GET(reg, 0, 4)
0294 #define STM32F4_ADC_CCR_MULTI_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
0295 #define ADC_MULTI_INDEPENDENT       0x00
0296 #define ADC_MULTI_DUAL_REG_INJ      0x01
0297 #define ADC_MULTI_DUAL_REG_ALT      0x02
0298 #define ADC_MULTI_DUAL_INJ          0x05
0299 #define ADC_MULTI_DUAL_REG          0x06
0300 #define ADC_MULTI_DUAL_INTRL        0x07
0301 #define ADC_MULTI_DUAL_ALT_TRIG     0x09
0302 #define ADC_MULTI_TRIPLE_REG_INJ    0x11
0303 #define ADC_MULTI_TRIPLE_REG_ALT    0x12
0304 #define ADC_MULTI_TRIPLE_INJ        0x15
0305 #define ADC_MULTI_TRIPLE_REG        0x16
0306 #define ADC_MULTI_TRIPLE_INTRL      0x17
0307 #define ADC_MULTI_TRIPLE_ALT_TRIG   0x19
0308
0309     uint32_t cdr;       // 0x00: Common regular data register
0310 #define STM32F4_ADC_CDR_DATA2(val)  BSP_FLD32(val, 16, 31)  // 2nd data item
0311 #define STM32F4_ADC_CDR_DATA2_GET(reg)  BSP_FLD32GET(reg, 16, 31)
0312 #define STM32F4_ADC_CDR_DATA2_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31)
0313 #define STM32F4_ADC_CDR_DATA1(val)  BSP_FLD32(val, 0, 15)   // 1st data item
0314 #define STM32F4_ADC_CDR_DATA1_GET(reg)  BSP_FLD32GET(reg, 0, 15)
0315 #define STM32F4_ADC_CDR_DATA1_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
0316
0317 } __attribute__ ((packed));
0318 typedef struct stm32f4_adc_com_s stm32f4_adc_com;
0319
0320 #endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H */