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File indexing completed on 2025-05-11 08:23:05

0001 /**
0002  * @file
0003  * @ingroup stm32_i2c
0004  * @brief STM32 I2C support.
0005  */
0006 
0007 /*
0008  * Copyright (c) 2013 Christian Mauderer.  All rights reserved.
0009  *
0010  * The license and distribution terms for this file may be
0011  * found in the file LICENSE in this distribution or at
0012  * http://www.rtems.org/license/LICENSE.
0013  */
0014 
0015 #ifndef LIBBSP_ARM_STM32F4_STM32_I2C_H
0016 #define LIBBSP_ARM_STM32F4_STM32_I2C_H
0017 
0018 #include <bsp/utility.h>
0019 
0020 /**
0021  * @defgroup stm32_i2c STM32 I2C Support
0022  * @ingroup stm32f4_i2c
0023  * @brief STM32 I2C Support
0024  * @{
0025  */
0026 
0027 typedef struct {
0028     uint32_t cr1;
0029 #define STM32F4_I2C_CR1_SWRST BSP_BIT32(15)
0030 #define STM32F4_I2C_CR1_ALERT BSP_BIT32(13)
0031 #define STM32F4_I2C_CR1_PEC BSP_BIT32(12)
0032 #define STM32F4_I2C_CR1_POS BSP_BIT32(11)
0033 #define STM32F4_I2C_CR1_ACK BSP_BIT32(10)
0034 #define STM32F4_I2C_CR1_STOP BSP_BIT32(9)
0035 #define STM32F4_I2C_CR1_START BSP_BIT32(8)
0036 #define STM32F4_I2C_CR1_NOSTRETCH BSP_BIT32(7)
0037 #define STM32F4_I2C_CR1_ENGC BSP_BIT32(6)
0038 #define STM32F4_I2C_CR1_ENPEC BSP_BIT32(5)
0039 #define STM32F4_I2C_CR1_ENARP BSP_BIT32(4)
0040 #define STM32F4_I2C_CR1_SMBTYPE BSP_BIT32(3)
0041 #define STM32F4_I2C_CR1_SMBUS BSP_BIT32(1)
0042 #define STM32F4_I2C_CR1_PE BSP_BIT32(0)
0043     uint32_t cr2;
0044 #define STM32F4_I2C_CR2_LAST BSP_BIT32(12)
0045 #define STM32F4_I2C_CR2_DMAEN BSP_BIT32(11)
0046 #define STM32F4_I2C_CR2_ITBUFEN BSP_BIT32(10)
0047 #define STM32F4_I2C_CR2_ITEVTEN BSP_BIT32(9)
0048 #define STM32F4_I2C_CR2_ITERREN BSP_BIT32(8)
0049 #define STM32F4_I2C_CR2_FREQ(val) BSP_FLD32(val, 0, 5)
0050 #define STM32F4_I2C_CR2_FREQ_GET(reg) BSP_FLD32GET(reg, 0, 5)
0051 #define STM32F4_I2C_CR2_FREQ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
0052     uint32_t oar1;
0053 #define STM32F4_I2C_OAR1_ADDMODE BSP_BIT32(15)
0054 #define STM32F4_I2C_OAR1_ADD(val) BSP_FLD32(val, 0, 9)
0055 #define STM32F4_I2C_OAR1_ADD_GET(reg) BSP_FLD32GET(reg, 0, 9)
0056 #define STM32F4_I2C_OAR1_ADD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
0057     uint32_t oar2;
0058 #define STM32F4_I2C_OAR2_ADD2(val) BSP_FLD32(val, 1, 7)
0059 #define STM32F4_I2C_OAR2_ADD2_GET(reg) BSP_FLD32GET(reg, 1, 7)
0060 #define STM32F4_I2C_OAR2_ADD2_SET(reg, val) BSP_FLD32SET(reg, val, 1, 7)
0061 #define STM32F4_I2C_OAR2_ENDUAL BSP_BIT32(0)
0062     uint32_t dr;
0063 #define STM32F4_I2C_DR(val) BSP_FLD32(val, 0, 7)
0064 #define STM32F4_I2C_DR_GET(reg) BSP_FLD32GET(reg, 0, 7)
0065 #define STM32F4_I2C_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
0066     uint32_t sr1;
0067 #define STM32F4_I2C_SR1_SMBALERT BSP_BIT32(15)
0068 #define STM32F4_I2C_SR1_TIMEOUT BSP_BIT32(14)
0069 #define STM32F4_I2C_SR1_PECERR BSP_BIT32(12)
0070 #define STM32F4_I2C_SR1_OVR BSP_BIT32(11)
0071 #define STM32F4_I2C_SR1_AF BSP_BIT32(10)
0072 #define STM32F4_I2C_SR1_ARLO BSP_BIT32(9)
0073 #define STM32F4_I2C_SR1_BERR BSP_BIT32(8)
0074 #define STM32F4_I2C_SR1_TxE BSP_BIT32(7)
0075 #define STM32F4_I2C_SR1_RxNE BSP_BIT32(6)
0076 #define STM32F4_I2C_SR1_STOPF BSP_BIT32(4)
0077 #define STM32F4_I2C_SR1_ADD10 BSP_BIT32(3)
0078 #define STM32F4_I2C_SR1_BTF BSP_BIT32(2)
0079 #define STM32F4_I2C_SR1_ADDR BSP_BIT32(1)
0080 #define STM32F4_I2C_SR1_SB BSP_BIT32(0)
0081     uint32_t sr2;
0082 #define STM32F4_I2C_SR2_PEC(val) BSP_FLD32(val, 8, 15)
0083 #define STM32F4_I2C_SR2_PEC_GET(reg) BSP_FLD32GET(reg, 8, 15)
0084 #define STM32F4_I2C_SR2_PEC_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
0085 #define STM32F4_I2C_SR2_DUALF BSP_BIT32(7)
0086 #define STM32F4_I2C_SR2_SMBHOST BSP_BIT32(6)
0087 #define STM32F4_I2C_SR2_SMBDEFAULT BSP_BIT32(5)
0088 #define STM32F4_I2C_SR2_GENCALL BSP_BIT32(4)
0089 #define STM32F4_I2C_SR2_TRA BSP_BIT32(2)
0090 #define STM32F4_I2C_SR2_BUSY BSP_BIT32(1)
0091 #define STM32F4_I2C_SR2_MSL BSP_BIT32(0)
0092     uint32_t ccr;
0093 #define STM32F4_I2C_CCR_FS BSP_BIT32(15)
0094 #define STM32F4_I2C_CCR_DUTY BSP_BIT32(14)
0095 #define STM32F4_I2C_CCR_CCR(val) BSP_FLD32(val, 0, 11)
0096 #define STM32F4_I2C_CCR_CCR_GET(reg) BSP_FLD32GET(reg, 0, 11)
0097 #define STM32F4_I2C_CCR_CCR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
0098 #define STM32F4_I2C_CCR_CCR_MAX STM32F4_I2C_CCR_CCR_GET(BSP_MSK32(0, 11))
0099     uint32_t trise;
0100 #define STM32F4_I2C_TRISE(val) BSP_FLD32(val, 0, 5)
0101 #define STM32F4_I2C_TRISE_GET(reg) BSP_FLD32GET(reg, 0, 5)
0102 #define STM32F4_I2C_TRISE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
0103 } stm32f4_i2c;
0104 
0105 /** @} */
0106 
0107 #endif /* LIBBSP_ARM_STM32F4_STM32_I2C_H */