include/bsp/io.h

0001 /**
0002  * @file
0003  * @ingroup stm32f4_io
0004  * @brief IO support.
0005  */
0006
0007 /*
0008  * Copyright (c) 2012 Sebastian Huber.  All rights reserved.
0009  *
0010  * The license and distribution terms for this file may be
0011  * found in the file LICENSE in this distribution or at
0012  * http://www.rtems.org/license/LICENSE.
0013  */
0014
0015 #ifndef LIBBSP_ARM_STM32F4_IO_H
0016 #define LIBBSP_ARM_STM32F4_IO_H
0017
0018 #include <stdbool.h>
0019 #include <stdint.h>
0020 #include <bspopts.h>
0021
0022 #ifdef __cplusplus
0023 extern "C" {
0024 #endif /* __cplusplus */
0025
0026 /**
0027  * @defgroup stm32f4_io IO Support
0028  * @ingroup RTEMSBSPsARMSTM32F4
0029  * @brief IO Support
0030  * @{
0031  */
0032
0033 #define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff)
0034
0035 #define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf)
0036
0037 #define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf)
0038
0039 #ifdef STM32F4_FAMILY_F4XXXX
0040
0041 /**
0042  * @name Family F4XXXX
0043  * @{
0044  */
0045
0046 typedef enum {
0047   STM32F4_GPIO_MODE_INPUT,
0048   STM32F4_GPIO_MODE_OUTPUT,
0049   STM32F4_GPIO_MODE_AF,
0050   STM32F4_GPIO_MODE_ANALOG
0051 } stm32f4_gpio_mode;
0052
0053 typedef enum {
0054   STM32F4_GPIO_OTYPE_PUSH_PULL,
0055   STM32F4_GPIO_OTYPE_OPEN_DRAIN
0056 } stm32f4_gpio_otype;
0057
0058 typedef enum {
0059   STM32F4_GPIO_OSPEED_2_MHZ,
0060   STM32F4_GPIO_OSPEED_25_MHZ,
0061   STM32F4_GPIO_OSPEED_50_MHZ,
0062   STM32F4_GPIO_OSPEED_100_MHZ
0063 } stm32f4_gpio_ospeed;
0064
0065 typedef enum {
0066   STM32F4_GPIO_NO_PULL,
0067   STM32F4_GPIO_PULL_UP,
0068   STM32F4_GPIO_PULL_DOWN
0069 } stm32f4_gpio_pull;
0070
0071 typedef enum {
0072   STM32F4_GPIO_AF_SYSTEM = 0,
0073   STM32F4_GPIO_AF_TIM1 = 1,
0074   STM32F4_GPIO_AF_TIM2 = 1,
0075   STM32F4_GPIO_AF_TIM3 = 2,
0076   STM32F4_GPIO_AF_TIM4 = 2,
0077   STM32F4_GPIO_AF_TIM5 = 2,
0078   STM32F4_GPIO_AF_TIM8 = 3,
0079   STM32F4_GPIO_AF_TIM9 = 3,
0080   STM32F4_GPIO_AF_TIM10 = 3,
0081   STM32F4_GPIO_AF_TIM11 = 3,
0082   STM32F4_GPIO_AF_I2C1 = 4,
0083   STM32F4_GPIO_AF_I2C2 = 4,
0084   STM32F4_GPIO_AF_I2C3 = 4,
0085   STM32F4_GPIO_AF_SPI1 = 5,
0086   STM32F4_GPIO_AF_SPI2 = 5,
0087   STM32F4_GPIO_AF_SPI3 = 6,
0088   STM32F4_GPIO_AF_USART1 = 7,
0089   STM32F4_GPIO_AF_USART2 = 7,
0090   STM32F4_GPIO_AF_USART3 = 7,
0091   STM32F4_GPIO_AF_UART4 = 8,
0092   STM32F4_GPIO_AF_UART5 = 8,
0093   STM32F4_GPIO_AF_USART6 = 8,
0094   STM32F4_GPIO_AF_CAN1 = 9,
0095   STM32F4_GPIO_AF_CAN2 = 9,
0096   STM32F4_GPIO_AF_TIM12 = 9,
0097   STM32F4_GPIO_AF_TIM13 = 9,
0098   STM32F4_GPIO_AF_TIM14 = 9,
0099   STM32F4_GPIO_AF_OTG_FS = 10,
0100   STM32F4_GPIO_AF_OTG_HS = 10,
0101   STM32F4_GPIO_AF_ETH = 11,
0102   STM32F4_GPIO_AF_FSMC = 12,
0103   STM32F4_GPIO_AF_OTG_HS_FS = 12,
0104   STM32F4_GPIO_AF_SDIO = 12,
0105   STM32F4_GPIO_AF_DCMI = 13,
0106   STM32F4_GPIO_AF_EVENTOUT = 15
0107 } stm32f4_gpio_af;
0108
0109 typedef union {
0110   struct {
0111     uint32_t pin_first : 8;
0112     uint32_t pin_last : 8;
0113     uint32_t mode : 2;
0114     uint32_t otype : 1;
0115     uint32_t ospeed : 2;
0116     uint32_t pupd : 2;
0117     uint32_t output : 1;
0118     uint32_t af : 4;
0119     uint32_t reserved : 4;
0120   } fields;
0121
0122   uint32_t value;
0123 } stm32f4_gpio_config;
0124
0125 #define STM32F4_GPIO_CONFIG_TERMINAL \
0126   { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } }
0127
0128 /** @} */
0129
0130 #endif /* STM32F4_FAMILY_F4XXXX */
0131 #ifdef STM32F4_FAMILY_F10XXX
0132
0133 /**
0134  * @name Family F10XXX
0135  * @{
0136  */
0137
0138 typedef enum {
0139   STM32F4_GPIO_MODE_INPUT,
0140   STM32F4_GPIO_MODE_OUTPUT_10MHz,
0141   STM32F4_GPIO_MODE_OUTPUT_2MHz,
0142   STM32F4_GPIO_MODE_OUTPUT_50MHz
0143 } stm32f4_gpio_mode;
0144
0145 typedef enum {
0146   STM32F4_GPIO_CNF_IN_ANALOG = 0,
0147   STM32F4_GPIO_CNF_IN_FLOATING = 1,
0148   STM32F4_GPIO_CNF_IN_PULL_UPDOWN = 2,
0149
0150   STM32F4_GPIO_CNF_OUT_GPIO_PP = 0,
0151   STM32F4_GPIO_CNF_OUT_GPIO_OD = 1,
0152   STM32F4_GPIO_CNF_OUT_AF_PP = 2,
0153   STM32F4_GPIO_CNF_OUT_AF_OD = 3,
0154 } stm32f4_gpio_cnf;
0155
0156 typedef enum {
0157   STM32F4_GPIO_REMAP_DONT_CHANGE,
0158   STM32F4_GPIO_REMAP_SPI1_0,
0159   STM32F4_GPIO_REMAP_SPI1_1,
0160   STM32F4_GPIO_REMAP_I2C1_0,
0161   STM32F4_GPIO_REMAP_I2C1_1,
0162   STM32F4_GPIO_REMAP_USART1_0,
0163   STM32F4_GPIO_REMAP_USART1_1,
0164   STM32F4_GPIO_REMAP_USART2_0,
0165   STM32F4_GPIO_REMAP_USART2_1,
0166   STM32F4_GPIO_REMAP_USART3_0,
0167   STM32F4_GPIO_REMAP_USART3_1,
0168   STM32F4_GPIO_REMAP_USART3_3,
0169   STM32F4_GPIO_REMAP_TIM1_0,
0170   STM32F4_GPIO_REMAP_TIM1_1,
0171   STM32F4_GPIO_REMAP_TIM1_3,
0172   STM32F4_GPIO_REMAP_TIM2_0,
0173   STM32F4_GPIO_REMAP_TIM2_1,
0174   STM32F4_GPIO_REMAP_TIM2_2,
0175   STM32F4_GPIO_REMAP_TIM2_3,
0176   STM32F4_GPIO_REMAP_TIM3_0,
0177   STM32F4_GPIO_REMAP_TIM3_2,
0178   STM32F4_GPIO_REMAP_TIM3_3,
0179   STM32F4_GPIO_REMAP_TIM4_0,
0180   STM32F4_GPIO_REMAP_TIM4_1,
0181   STM32F4_GPIO_REMAP_CAN1_0,
0182   STM32F4_GPIO_REMAP_CAN1_2,
0183   STM32F4_GPIO_REMAP_CAN1_3,
0184   STM32F4_GPIO_REMAP_PD01_0,
0185   STM32F4_GPIO_REMAP_PD01_1,
0186   STM32F4_GPIO_REMAP_TIM5CH4_0,
0187   STM32F4_GPIO_REMAP_TIM5CH4_1,
0188   STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0,
0189   STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1,
0190   STM32F4_GPIO_REMAP_ADC1_ETRGREG_0,
0191   STM32F4_GPIO_REMAP_ADC1_ETRGREG_1,
0192   STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0,
0193   STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1,
0194   STM32F4_GPIO_REMAP_ADC2_ETRGREG_0,
0195   STM32F4_GPIO_REMAP_ADC2_ETRGREG_1,
0196   STM32F4_GPIO_REMAP_ETH_0,
0197   STM32F4_GPIO_REMAP_ETH_1,
0198   STM32F4_GPIO_REMAP_CAN2_0,
0199   STM32F4_GPIO_REMAP_CAN2_1,
0200   STM32F4_GPIO_REMAP_MII_RMII_0,
0201   STM32F4_GPIO_REMAP_MII_RMII_1,
0202   STM32F4_GPIO_REMAP_SWJ_0,
0203   STM32F4_GPIO_REMAP_SWJ_1,
0204   STM32F4_GPIO_REMAP_SWJ_2,
0205   STM32F4_GPIO_REMAP_SWJ_4,
0206   STM32F4_GPIO_REMAP_SPI3_0,
0207   STM32F4_GPIO_REMAP_SPI3_1,
0208   STM32F4_GPIO_REMAP_TIM2ITR1_0,
0209   STM32F4_GPIO_REMAP_TIM2ITR1_1,
0210   STM32F4_GPIO_REMAP_PTP_PPS_0,
0211   STM32F4_GPIO_REMAP_PTP_PPS_1,
0212   STM32F4_GPIO_REMAP_TIM15_0,
0213   STM32F4_GPIO_REMAP_TIM15_1,
0214   STM32F4_GPIO_REMAP_TIM16_0,
0215   STM32F4_GPIO_REMAP_TIM16_1,
0216   STM32F4_GPIO_REMAP_TIM17_0,
0217   STM32F4_GPIO_REMAP_TIM17_1,
0218   STM32F4_GPIO_REMAP_CEC_0,
0219   STM32F4_GPIO_REMAP_CEC_1,
0220   STM32F4_GPIO_REMAP_TIM1_DMA_0,
0221   STM32F4_GPIO_REMAP_TIM1_DMA_1,
0222   STM32F4_GPIO_REMAP_TIM9_0,
0223   STM32F4_GPIO_REMAP_TIM9_1,
0224   STM32F4_GPIO_REMAP_TIM10_0,
0225   STM32F4_GPIO_REMAP_TIM10_1,
0226   STM32F4_GPIO_REMAP_TIM11_0,
0227   STM32F4_GPIO_REMAP_TIM11_1,
0228   STM32F4_GPIO_REMAP_TIM13_0,
0229   STM32F4_GPIO_REMAP_TIM13_1,
0230   STM32F4_GPIO_REMAP_TIM14_0,
0231   STM32F4_GPIO_REMAP_TIM14_1,
0232   STM32F4_GPIO_REMAP_FSMC_0,
0233   STM32F4_GPIO_REMAP_FSMC_1,
0234   STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0,
0235   STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1,
0236   STM32F4_GPIO_REMAP_TIM12_0,
0237   STM32F4_GPIO_REMAP_TIM12_1,
0238   STM32F4_GPIO_REMAP_MISC_0,
0239   STM32F4_GPIO_REMAP_MISC_1,
0240 } stm32f4_gpio_remap;
0241
0242 typedef union {
0243   struct {
0244     uint32_t pin_first : 8;
0245     uint32_t pin_last : 8;
0246     uint32_t mode : 2;
0247     uint32_t cnf : 2;
0248     uint32_t output : 1;
0249     uint32_t remap : 8;
0250     uint32_t reserved : 3;
0251   } fields;
0252
0253   uint32_t value;
0254 } stm32f4_gpio_config;
0255
0256 #define STM32F4_GPIO_CONFIG_TERMINAL \
0257   { { 0xff, 0xff, 0x3, 0x3, 0x1, 0xff, 0x7 } }
0258
0259 /** @} */
0260
0261 #endif /* STM32F4_FAMILY_F10XXX */
0262
0263 extern const stm32f4_gpio_config stm32f4_start_config_gpio [];
0264
0265 void stm32f4_gpio_set_clock(int pin, bool set);
0266
0267 void stm32f4_gpio_set_config(const stm32f4_gpio_config *config);
0268
0269 /**
0270  * @brief Sets the GPIO configuration of an array terminated by
0271  * STM32F4_GPIO_CONFIG_TERMINAL.
0272  */
0273 void stm32f4_gpio_set_config_array(const stm32f4_gpio_config *configs);
0274
0275 void stm32f4_gpio_set_output(int pin, bool set);
0276
0277 bool stm32f4_gpio_get_input(int pin);
0278
0279 #ifdef STM32F4_FAMILY_F4XXXX
0280
0281 /**
0282  * @name Family F4XXXX
0283  * @{
0284  */
0285
0286 #define STM32F4_PIN_USART(port, idx, altfunc) \
0287   { \
0288     { \
0289       .pin_first = STM32F4_GPIO_PIN(port, idx), \
0290       .pin_last = STM32F4_GPIO_PIN(port, idx), \
0291       .mode = STM32F4_GPIO_MODE_AF, \
0292       .otype = STM32F4_GPIO_OTYPE_PUSH_PULL, \
0293       .ospeed = STM32F4_GPIO_OSPEED_2_MHZ, \
0294       .pupd = STM32F4_GPIO_PULL_UP, \
0295       .af = altfunc \
0296     } \
0297   }
0298
0299 #define STM32F4_PIN_USART1_TX_PA9 STM32F4_PIN_USART(0, 9, STM32F4_GPIO_AF_USART1)
0300 #define STM32F4_PIN_USART1_TX_PB6 STM32F4_PIN_USART(1, 6, STM32F4_GPIO_AF_USART1)
0301 #define STM32F4_PIN_USART1_RX_PA10 STM32F4_PIN_USART(0, 10, STM32F4_GPIO_AF_USART1)
0302 #define STM32F4_PIN_USART1_RX_PB7 STM32F4_PIN_USART(1, 7, STM32F4_GPIO_AF_USART1)
0303
0304 #define STM32F4_PIN_USART2_TX_PA2 STM32F4_PIN_USART(0, 2, STM32F4_GPIO_AF_USART2)
0305 #define STM32F4_PIN_USART2_TX_PD5 STM32F4_PIN_USART(3, 5, STM32F4_GPIO_AF_USART2)
0306 #define STM32F4_PIN_USART2_RX_PA3 STM32F4_PIN_USART(0, 3, STM32F4_GPIO_AF_USART2)
0307 #define STM32F4_PIN_USART2_RX_PD6 STM32F4_PIN_USART(3, 6, STM32F4_GPIO_AF_USART2)
0308
0309 #define STM32F4_PIN_USART3_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_USART3)
0310 #define STM32F4_PIN_USART3_TX_PD8 STM32F4_PIN_USART(3, 8, STM32F4_GPIO_AF_USART3)
0311 #define STM32F4_PIN_USART3_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_USART3)
0312 #define STM32F4_PIN_USART3_RX_PD9 STM32F4_PIN_USART(3, 9, STM32F4_GPIO_AF_USART3)
0313
0314 #define STM32F4_PIN_UART4_TX_PA0 STM32F4_PIN_USART(0, 0, STM32F4_GPIO_AF_UART4)
0315 #define STM32F4_PIN_UART4_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_UART4)
0316 #define STM32F4_PIN_UART4_RX_PA1 STM32F4_PIN_USART(0, 1, STM32F4_GPIO_AF_UART4)
0317 #define STM32F4_PIN_UART4_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_UART4)
0318
0319 #define STM32F4_PIN_UART5_TX_PC12 STM32F4_PIN_USART(2, 12, STM32F4_GPIO_AF_UART5)
0320 #define STM32F4_PIN_UART5_RX_PD2 STM32F4_PIN_USART(3, 2, STM32F4_GPIO_AF_UART5)
0321
0322 #define STM32F4_PIN_USART6_TX_PC6 STM32F4_PIN_USART(2, 6, STM32F4_GPIO_AF_USART6)
0323 #define STM32F4_PIN_USART6_RX_PC7 STM32F4_PIN_USART(2, 7, STM32F4_GPIO_AF_USART6)
0324
0325 /** @} */
0326
0327 #endif /* STM32F4_FAMILY_F4XXXX */
0328 #ifdef STM32F4_FAMILY_F10XXX
0329
0330 /**
0331  * @name Family F10XXX
0332  * @{
0333  */
0334
0335 #define STM32F4_PIN_USART_TX(port, idx, remapvalue) \
0336   { \
0337     { \
0338       .pin_first = STM32F4_GPIO_PIN(port, idx), \
0339       .pin_last = STM32F4_GPIO_PIN(port, idx), \
0340       .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \
0341       .cnf = STM32F4_GPIO_CNF_OUT_AF_PP, \
0342       .output = 0, \
0343       .remap = remapvalue \
0344     } \
0345   }
0346
0347 #define STM32F4_PIN_USART_RX(port, idx, remapvalue) \
0348   { \
0349     { \
0350       .pin_first = STM32F4_GPIO_PIN(port, idx), \
0351       .pin_last = STM32F4_GPIO_PIN(port, idx), \
0352       .mode = STM32F4_GPIO_MODE_INPUT, \
0353       .cnf = STM32F4_GPIO_CNF_IN_FLOATING, \
0354       .output = 0, \
0355       .remap = remapvalue \
0356     } \
0357   }
0358
0359 #define STM32F4_PIN_USART1_TX_MAP_0 STM32F4_PIN_USART_TX(0,  9, STM32F4_GPIO_REMAP_USART1_0)
0360 #define STM32F4_PIN_USART1_RX_MAP_0 STM32F4_PIN_USART_RX(0, 10, STM32F4_GPIO_REMAP_USART1_0)
0361 #define STM32F4_PIN_USART1_TX_MAP_1 STM32F4_PIN_USART_TX(1,  6, STM32F4_GPIO_REMAP_USART1_1)
0362 #define STM32F4_PIN_USART1_RX_MAP_1 STM32F4_PIN_USART_RX(1,  7, STM32F4_GPIO_REMAP_USART1_1)
0363
0364 #define STM32F4_PIN_USART2_TX_MAP_0 STM32F4_PIN_USART_TX(0,  2, STM32F4_GPIO_REMAP_USART2_0)
0365 #define STM32F4_PIN_USART2_RX_MAP_0 STM32F4_PIN_USART_RX(0,  3, STM32F4_GPIO_REMAP_USART2_0)
0366 #define STM32F4_PIN_USART2_TX_MAP_1 STM32F4_PIN_USART_TX(3,  5, STM32F4_GPIO_REMAP_USART2_1)
0367 #define STM32F4_PIN_USART2_RX_MAP_1 STM32F4_PIN_USART_RX(3,  6, STM32F4_GPIO_REMAP_USART2_1)
0368
0369 #define STM32F4_PIN_USART3_TX_MAP_0 STM32F4_PIN_USART_TX(1, 10, STM32F4_GPIO_REMAP_USART3_0)
0370 #define STM32F4_PIN_USART3_RX_MAP_0 STM32F4_PIN_USART_RX(1, 11, STM32F4_GPIO_REMAP_USART3_0)
0371 #define STM32F4_PIN_USART3_TX_MAP_1 STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_USART3_1)
0372 #define STM32F4_PIN_USART3_RX_MAP_1 STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_USART3_1)
0373 #define STM32F4_PIN_USART3_TX_MAP_3 STM32F4_PIN_USART_TX(3,  8, STM32F4_GPIO_REMAP_USART3_3)
0374 #define STM32F4_PIN_USART3_RX_MAP_3 STM32F4_PIN_USART_RX(3,  9, STM32F4_GPIO_REMAP_USART3_3)
0375
0376 #define STM32F4_PIN_UART4_TX        STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_DONT_CHANGE)
0377 #define STM32F4_PIN_UART4_RX        STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_DONT_CHANGE)
0378
0379 #define STM32F4_PIN_UART5_TX        STM32F4_PIN_USART_TX(2, 12, STM32F4_GPIO_REMAP_DONT_CHANGE)
0380 #define STM32F4_PIN_UART5_RX        STM32F4_PIN_USART_RX(3,  2, STM32F4_GPIO_REMAP_DONT_CHANGE)
0381
0382 #define STM32F4_PIN_I2C(port, idx, remapvalue) \
0383   { \
0384     { \
0385       .pin_first = STM32F4_GPIO_PIN(port, idx), \
0386       .pin_last = STM32F4_GPIO_PIN(port, idx), \
0387       .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \
0388       .cnf = STM32F4_GPIO_CNF_OUT_AF_OD, \
0389       .output = 0, \
0390       .remap = remapvalue \
0391     } \
0392   }
0393
0394 #define STM32F4_PIN_I2C1_SCL_MAP0 STM32F4_PIN_I2C(1, 6, STM32F4_GPIO_REMAP_I2C1_0)
0395 #define STM32F4_PIN_I2C1_SDA_MAP0 STM32F4_PIN_I2C(1, 7, STM32F4_GPIO_REMAP_I2C1_0)
0396 #define STM32F4_PIN_I2C1_SCL_MAP1 STM32F4_PIN_I2C(1, 8, STM32F4_GPIO_REMAP_I2C1_1)
0397 #define STM32F4_PIN_I2C1_SDA_MAP1 STM32F4_PIN_I2C(1, 9, STM32F4_GPIO_REMAP_I2C1_1)
0398
0399 #define STM32F4_PIN_I2C2_SCL      STM32F4_PIN_I2C(1, 10, STM32F4_GPIO_REMAP_DONT_CHANGE)
0400 #define STM32F4_PIN_I2C2_SDA      STM32F4_PIN_I2C(1, 11, STM32F4_GPIO_REMAP_DONT_CHANGE)
0401
0402 /** @} */
0403
0404 #endif /* STM32F4_FAMILY_F10XXX */
0405
0406 #ifdef __cplusplus
0407 }
0408 #endif /* __cplusplus */
0409
0410 #endif /* LIBBSP_ARM_STM32F4_IO_H */