smdk2410/start/start.S

0001 /*
0002  * SMDK2410 startup code
0003  */
0004
0005 /*
0006  *  The license and distribution terms for this file may be
0007  *  found in the file LICENSE in this distribution or at
0008  *  http://www.rtems.org/license/LICENSE.
0009  */
0010
0011 #include <rtems/asm.h>
0012 #include <rtems/score/cpu.h>
0013
0014 .text
0015 .globl  _start
0016 _start:
0017     b       _start2
0018
0019 @---------------------------------------------------------------------------------
0020 @ AXF addresses
0021 @---------------------------------------------------------------------------------
0022     .word   bsp_section_text_begin
0023     .word   bsp_section_rodata_end
0024     .word   bsp_section_data_begin
0025     .word   bsp_section_bss_end
0026     .word   bsp_section_bss_begin
0027     .word   bsp_section_bss_end
0028
0029 @---------------------------------------------------------------------------------
0030 @ GamePark magic sequence
0031 @---------------------------------------------------------------------------------
0032     .word   0x44450011
0033     .word   0x44450011
0034     .word   0x01234567
0035     .word   0x12345678
0036     .word   0x23456789
0037     .word   0x34567890
0038     .word   0x45678901
0039     .word   0x56789012
0040     .word   0x23456789
0041     .word   0x34567890
0042     .word   0x45678901
0043     .word   0x56789012
0044     .word   0x23456789
0045     .word   0x34567890
0046     .word   0x45678901
0047     .word   0x56789012
0048
0049 @---------------------------------------------------------------------------------
0050 _start2:
0051 @---------------------------------------------------------------------------------
0052
0053         /*
0054          * Since I don't plan to return to the bootloader,
0055          * I don't have to save the registers.
0056          */
0057
0058         /* Set end of interrupt stack area */
0059         ldr     r7, =_ISR_Stack_area_end
0060
0061         /* Enter FIQ mode and set up the FIQ stack pointer */
0062         mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
0063         msr     cpsr, r0
0064         ldr     r1, =bsp_stack_fiq_size
0065         mov     sp, r7
0066         sub     r7, r7, r1
0067
0068         /* Enter ABT mode and set up the ABT stack pointer */
0069         mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
0070         msr     cpsr, r0
0071         ldr     r1, =bsp_stack_abt_size
0072         mov     sp, r7
0073         sub     r7, r7, r1
0074
0075         /* Enter UND mode and set up the UND stack pointer */
0076         mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
0077         msr     cpsr, r0
0078         ldr     r1, =bsp_stack_und_size
0079         mov     sp, r7
0080         sub     r7, r7, r1
0081
0082         /* Enter IRQ mode and set up the IRQ stack pointer */
0083         mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
0084         msr     cpsr, r0
0085         mov     sp, r7
0086
0087         /*
0088          * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
0089          * (interrupts are disabled).
0090          */
0091         mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
0092         msr     cpsr, r0
0093         mov     sp, r7
0094
0095         /* Stay in SVC mode */
0096
0097     /* disable mmu, I and D caches*/
0098     nop
0099     nop
0100     mrc p15, 0, r0, c1, c0, 0
0101     bic r0, r0, #0x01
0102     bic r0, r0, #0x04
0103     bic r0, r0, #0x01000
0104     mcr p15, 0, r0, c1, c0, 0
0105     nop
0106     nop
0107
0108     /* clean data cache */
0109     mov   r1,#0x00
0110 Loop1:
0111     mov   r2,#0x00
0112 Loop2:
0113     mov r3, r2, lsl#26
0114     orr r3, r3, r1, lsl#5
0115     mcr p15, 0, r3, c7, c14, 2
0116     add r2, r2, #0x01
0117     cmp r2, #64
0118     bne Loop2
0119     add r1, r1, #0x01
0120     cmp r1, #8
0121     bne Loop1
0122
0123
0124         /*
0125          * Initialize the MMU. After we return, the MMU is enabled,
0126          * and memory may be remapped. I hope we don't remap this
0127          * memory away.
0128          */
0129         ldr     r0, =mem_map
0130         bl      mmu_init
0131
0132         /*
0133          * Initialize the exception vectors. This includes the
0134          * exceptions vectors (0x00000000-0x0000001c), and the
0135          * pointers to the exception handlers (0x00000020-0x0000003c).
0136          */
0137         mov     r0, #0
0138         adr     r1, vector_block
0139         ldmia   r1!, {r2-r9}
0140         stmia   r0!, {r2-r9}
0141         ldmia   r1!, {r2-r9}
0142         stmia   r0!, {r2-r9}
0143
0144         /* Now we are prepared to start the BSP's C code */
0145         mov     r0, #0
0146         bl      boot_card
0147
0148         /*
0149          * Theoretically, we could return to what started us up,
0150          * but we'd have to have saved the registers and stacks.
0151          * Instead, we'll just reset.
0152          */
0153         bl      bsp_reset
0154
0155         /* We shouldn't get here. If we do, hang */
0156 _hang:  b       _hang
0157
0158
0159 /*
0160  * This is the exception vector table and the pointers to
0161  * the functions that handle the exceptions. It's a total
0162  * of 16 words (64 bytes)
0163  */
0164 vector_block:
0165         ldr    pc, handler_addr_reset
0166         ldr    pc, handler_addr_undef
0167         ldr    pc, handler_addr_swi
0168         ldr    pc, handler_addr_prefetch
0169         ldr    pc, handler_addr_abort
0170         nop
0171         ldr    pc, handler_addr_irq
0172         ldr    pc, handler_addr_fiq
0173
0174 handler_addr_reset:
0175         .word  bsp_reset
0176
0177 handler_addr_undef:
0178         .word  _ARMV4_Exception_undef_default
0179
0180 handler_addr_swi:
0181         .word  _ARMV4_Exception_swi_default
0182
0183 handler_addr_prefetch:
0184         .word  _ARMV4_Exception_pref_abort_default
0185
0186 handler_addr_abort:
0187         .word  _ARMV4_Exception_data_abort_default
0188
0189 handler_addr_reserved:
0190         .word  0
0191
0192 handler_addr_irq:
0193         .word  _ARMV4_Exception_interrupt
0194
0195 handler_addr_fiq:
0196         .word  _ARMV4_Exception_fiq_default