smdk2410/include/s3c2410.h

0001 /************************************************
0002  * NAME     : s3c2410.h
0003  * Version  : 3.7.2002
0004  *
0005  * Based on 24x.h for the Samsung Development Board
0006  ************************************************/
0007
0008 #ifndef S3C2410_H_
0009 #define S3C2410_H_
0010
0011 /* to be used in assembly code */
0012 #define rINTOFFSET_ADDR 0x4A000014
0013 /* Memory control */
0014 #define rBWSCON         (*(volatile unsigned *)0x48000000)
0015 #define rBANKCON0       (*(volatile unsigned *)0x48000004)
0016 #define rBANKCON1       (*(volatile unsigned *)0x48000008)
0017 #define rBANKCON2       (*(volatile unsigned *)0x4800000C)
0018 #define rBANKCON3       (*(volatile unsigned *)0x48000010)
0019 #define rBANKCON4       (*(volatile unsigned *)0x48000014)
0020 #define rBANKCON5       (*(volatile unsigned *)0x48000018)
0021 #define rBANKCON6       (*(volatile unsigned *)0x4800001C)
0022 #define rBANKCON7       (*(volatile unsigned *)0x48000020)
0023 #define rREFRESH        (*(volatile unsigned *)0x48000024)
0024 #define rBANKSIZE       (*(volatile unsigned *)0x48000028)
0025 #define rMRSRB6         (*(volatile unsigned *)0x4800002C)
0026 #define rMRSRB7         (*(volatile unsigned *)0x48000030)
0027
0028 /* USB Host Controller */
0029 #define rHcRevision     (*(volatile unsigned *)0x49000000)
0030 #define rHcControl      (*(volatile unsigned *)0x49000004)
0031 #define rHcCommonStatus     (*(volatile unsigned *)0x49000008)
0032 #define rHcInterruptStatus  (*(volatile unsigned *)0x4900000C)
0033 #define rHcInterruptEnable  (*(volatile unsigned *)0x49000010)
0034 #define rHcInterruptDisable (*(volatile unsigned *)0x49000014)
0035 #define rHcHCCA         (*(volatile unsigned *)0x49000018)
0036 #define rHcPeriodCuttendED  (*(volatile unsigned *)0x4900001C)
0037 #define rHcControlHeadED    (*(volatile unsigned *)0x49000020)
0038 #define rHcControlCurrentED (*(volatile unsigned *)0x49000024)
0039 #define rHcBulkHeadED       (*(volatile unsigned *)0x49000028)
0040 #define rHcBuldCurrentED    (*(volatile unsigned *)0x4900002C)
0041 #define rHcDoneHead     (*(volatile unsigned *)0x49000030)
0042 #define rHcRmInterval       (*(volatile unsigned *)0x49000034)
0043 #define rHcFmRemaining      (*(volatile unsigned *)0x49000038)
0044 #define rHcFmNumber     (*(volatile unsigned *)0x4900003C)
0045 #define rHcPeriodicStart    (*(volatile unsigned *)0x49000040)
0046 #define rHcLSThreshold      (*(volatile unsigned *)0x49000044)
0047 #define rHcRhDescriptorA    (*(volatile unsigned *)0x49000048)
0048 #define rHcRhDescriptorB    (*(volatile unsigned *)0x4900004C)
0049 #define rHcRhStatus     (*(volatile unsigned *)0x49000050)
0050 #define rHcRhPortStatus1    (*(volatile unsigned *)0x49000054)
0051 #define rHcRhPortStatus2    (*(volatile unsigned *)0x49000058)
0052
0053 /* INTERRUPT */
0054 #define rSRCPND         (*(volatile unsigned *)0x4A000000)
0055 #define rINTMOD         (*(volatile unsigned *)0x4A000004)
0056 #define rINTMSK         (*(volatile unsigned *)0x4A000008)
0057 #define rPRIORITY       (*(volatile unsigned *)0x4A00000C)
0058 #define rINTPND         (*(volatile unsigned *)0x4A000010)
0059 #define rINTOFFSET      (*(volatile unsigned *)0x4A000014)
0060 #define rSUBSRCPND      (*(volatile unsigned *)0x4A000018)
0061 #define rINTSUBMSK      (*(volatile unsigned *)0x4A00001c)
0062
0063
0064 /* DMA */
0065 #define rDISRC0         (*(volatile unsigned *)0x4B000000)
0066 #define rDISRCC0        (*(volatile unsigned *)0x4B000004)
0067 #define rDIDST0         (*(volatile unsigned *)0x4B000008)
0068 #define rDIDSTC0        (*(volatile unsigned *)0x4B00000C)
0069 #define rDCON0          (*(volatile unsigned *)0x4B000010)
0070 #define rDSTAT0         (*(volatile unsigned *)0x4B000014)
0071 #define rDCSRC0         (*(volatile unsigned *)0x4B000018)
0072 #define rDCDST0         (*(volatile unsigned *)0x4B00001C)
0073 #define rDMASKTRIG0     (*(volatile unsigned *)0x4B000020)
0074 #define rDISRC1         (*(volatile unsigned *)0x4B000040)
0075 #define rDISRCC1        (*(volatile unsigned *)0x4B000044)
0076 #define rDIDST1         (*(volatile unsigned *)0x4B000048)
0077 #define rDIDSTC1        (*(volatile unsigned *)0x4B00004C)
0078 #define rDCON1          (*(volatile unsigned *)0x4B000050)
0079 #define rDSTAT1         (*(volatile unsigned *)0x4B000054)
0080 #define rDCSRC1         (*(volatile unsigned *)0x4B000058)
0081 #define rDCDST1         (*(volatile unsigned *)0x4B00005C)
0082 #define rDMASKTRIG1     (*(volatile unsigned *)0x4B000060)
0083 #define rDISRC2         (*(volatile unsigned *)0x4B000080)
0084 #define rDISRCC2        (*(volatile unsigned *)0x4B000084)
0085 #define rDIDST2         (*(volatile unsigned *)0x4B000088)
0086 #define rDIDSTC2        (*(volatile unsigned *)0x4B00008C)
0087 #define rDCON2          (*(volatile unsigned *)0x4B000090)
0088 #define rDSTAT2         (*(volatile unsigned *)0x4B000094)
0089 #define rDCSRC2         (*(volatile unsigned *)0x4B000098)
0090 #define rDCDST2         (*(volatile unsigned *)0x4B00009C)
0091 #define rDMASKTRIG2     (*(volatile unsigned *)0x4B0000A0)
0092 #define rDISRC3         (*(volatile unsigned *)0x4B0000C0)
0093 #define rDISRCC3        (*(volatile unsigned *)0x4B0000C4)
0094 #define rDIDST3         (*(volatile unsigned *)0x4B0000C8)
0095 #define rDIDSTC3        (*(volatile unsigned *)0x4B0000CC)
0096 #define rDCON3          (*(volatile unsigned *)0x4B0000D0)
0097 #define rDSTAT3         (*(volatile unsigned *)0x4B0000D4)
0098 #define rDCSRC3         (*(volatile unsigned *)0x4B0000D8)
0099 #define rDCDST3         (*(volatile unsigned *)0x4B0000DC)
0100 #define rDMASKTRIG3     (*(volatile unsigned *)0x4B0000E0)
0101
0102
0103 /* CLOCK & POWER MANAGEMENT */
0104 #define rLOCKTIME       (*(volatile unsigned *)0x4C000000)
0105 #define rMPLLCON        (*(volatile unsigned *)0x4C000004)
0106 #define rUPLLCON        (*(volatile unsigned *)0x4C000008)
0107 #define rCLKCON         (*(volatile unsigned *)0x4C00000C)
0108 #define rCLKSLOW        (*(volatile unsigned *)0x4C000010)
0109 #define rCLKDIVN        (*(volatile unsigned *)0x4C000014)
0110
0111
0112 /* LCD CONTROLLER */
0113 #define rLCDCON1        (*(volatile unsigned *)0x4D000000)
0114 #define rLCDCON2        (*(volatile unsigned *)0x4D000004)
0115 #define rLCDCON3        (*(volatile unsigned *)0x4D000008)
0116 #define rLCDCON4        (*(volatile unsigned *)0x4D00000C)
0117 #define rLCDCON5        (*(volatile unsigned *)0x4D000010)
0118 #define rLCDSADDR1      (*(volatile unsigned *)0x4D000014)
0119 #define rLCDSADDR2      (*(volatile unsigned *)0x4D000018)
0120 #define rLCDSADDR3      (*(volatile unsigned *)0x4D00001C)
0121 #define rREDLUT         (*(volatile unsigned *)0x4D000020)
0122 #define rGREENLUT       (*(volatile unsigned *)0x4D000024)
0123 #define rBLUELUT        (*(volatile unsigned *)0x4D000028)
0124 #define rREDLUT         (*(volatile unsigned *)0x4D000020)
0125 #define rGREENLUT       (*(volatile unsigned *)0x4D000024)
0126 #define rBLUELUT        (*(volatile unsigned *)0x4D000028)
0127 #define rDITHMODE       (*(volatile unsigned *)0x4D00004C)
0128 #define rTPAL           (*(volatile unsigned *)0x4D000050)
0129 #define rLCDINTPND      (*(volatile unsigned *)0x4D000054)
0130 #define rLCDSRCPND      (*(volatile unsigned *)0x4D000058)
0131 #define rLCDINTMSK      (*(volatile unsigned *)0x4D00005C)
0132 #define rTCONSEL        (*(volatile unsigned *)0x4D000060)
0133 #define PALETTE         0x4d000400
0134
0135 /* NAND Flash */
0136 #define rNFCONF         (*(volatile unsigned *)0x4E000000)
0137 #define rNFCMD          (*(volatile unsigned *)0x4E000004)
0138 #define rNFADDR         (*(volatile unsigned *)0x4E000008)
0139 #define rNFDATA         (*(volatile unsigned *)0x4E00000C)
0140 #define rNFSTAT         (*(volatile unsigned *)0x4E000010)
0141 #define rNFECC          (*(volatile unsigned *)0x4E000014)
0142
0143 /* UART */
0144 #define rULCON0         (*(volatile unsigned char  *)0x50000000)
0145 #define rUCON0          (*(volatile unsigned short *)0x50000004)
0146 #define rUFCON0         (*(volatile unsigned char  *)0x50000008)
0147 #define rUMCON0         (*(volatile unsigned char  *)0x5000000C)
0148 #define rUTRSTAT0       (*(volatile unsigned char  *)0x50000010)
0149 #define rUERSTAT0       (*(volatile unsigned char  *)0x50000014)
0150 #define rUFSTAT0        (*(volatile unsigned short *)0x50000018)
0151 #define rUMSTAT0        (*(volatile unsigned char  *)0x5000001C)
0152 #define rUBRDIV0        (*(volatile unsigned short *)0x50000028)
0153
0154 #define rULCON1         (*(volatile unsigned char  *)0x50004000)
0155 #define rUCON1          (*(volatile unsigned short *)0x50004004)
0156 #define rUFCON1         (*(volatile unsigned char  *)0x50004008)
0157 #define rUMCON1         (*(volatile unsigned char  *)0x5000400C)
0158 #define rUTRSTAT1       (*(volatile unsigned char  *)0x50004010)
0159 #define rUERSTAT1       (*(volatile unsigned char  *)0x50004014)
0160 #define rUFSTAT1        (*(volatile unsigned short *)0x50004018)
0161 #define rUMSTAT1        (*(volatile unsigned char  *)0x5000401C)
0162 #define rUBRDIV1        (*(volatile unsigned short *)0x50004028)
0163
0164 #define rULCON2         (*(volatile unsigned char  *)0x50008000)
0165 #define rUCON2          (*(volatile unsigned short *)0x50008004)
0166 #define rUFCON2         (*(volatile unsigned char  *)0x50008008)
0167 #define rUTRSTAT2       (*(volatile unsigned char  *)0x50008010)
0168 #define rUERSTAT2       (*(volatile unsigned char  *)0x50008014)
0169 #define rUFSTAT2        (*(volatile unsigned short *)0x50008018)
0170 #define rUBRDIV2        (*(volatile unsigned short *)0x50008028)
0171
0172 #ifdef __BIG_ENDIAN
0173 #define rUTXH0          (*(volatile unsigned char *)0x50000023)
0174 #define rURXH0          (*(volatile unsigned char *)0x50000027)
0175 #define rUTXH1          (*(volatile unsigned char *)0x50004023)
0176 #define rURXH1          (*(volatile unsigned char *)0x50004027)
0177 #define rUTXH2          (*(volatile unsigned char *)0x50008023)
0178 #define rURXH2          (*(volatile unsigned char *)0x50008027)
0179
0180 #define WrUTXH0(ch)     (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
0181 #define RdURXH0()       (*(volatile unsigned char *)0x50000027)
0182 #define WrUTXH1(ch)     (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
0183 #define RdURXH1()       (*(volatile unsigned char *)0x50004027)
0184 #define WrUTXH2(ch)     (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
0185 #define RdURXH2()       (*(volatile unsigned char *)0x50008027)
0186
0187 #define UTXH0           (0x50000020+3)  /* byte_access address by DMA */
0188 #define URXH0           (0x50000024+3)
0189 #define UTXH1           (0x50004020+3)
0190 #define URXH1           (0x50004024+3)
0191 #define UTXH2           (0x50008020+3)
0192 #define URXH2           (0x50008024+3)
0193
0194 #else /* Little Endian */
0195 #define rUTXH0          (*(volatile unsigned char *)0x50000020)
0196 #define rURXH0          (*(volatile unsigned char *)0x50000024)
0197 #define rUTXH1          (*(volatile unsigned char *)0x50004020)
0198 #define rURXH1          (*(volatile unsigned char *)0x50004024)
0199 #define rUTXH2          (*(volatile unsigned char *)0x50008020)
0200 #define rURXH2          (*(volatile unsigned char *)0x50008024)
0201
0202 #define WrUTXH0(ch)     (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
0203 #define RdURXH0()       (*(volatile unsigned char *)0x50000024)
0204 #define WrUTXH1(ch)     (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
0205 #define RdURXH1()       (*(volatile unsigned char *)0x50004024)
0206 #define WrUTXH2(ch)     (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
0207 #define RdURXH2()       (*(volatile unsigned char *)0x50008024)
0208
0209 #define UTXH0           (0x50000020)
0210 #define URXH0           (0x50000024)
0211 #define UTXH1           (0x50004020)
0212 #define URXH1           (0x50004024)
0213 #define UTXH2           (0x50008020)
0214 #define URXH2           (0x50008024)
0215 #endif
0216
0217
0218 /* PWM TIMER */
0219 #define rTCFG0          (*(volatile unsigned *)0x51000000)
0220 #define rTCFG1          (*(volatile unsigned *)0x51000004)
0221 #define rTCON           (*(volatile unsigned *)0x51000008)
0222 #define rTCNTB0         (*(volatile unsigned *)0x5100000C)
0223 #define rTCMPB0         (*(volatile unsigned *)0x51000010)
0224 #define rTCNTO0         (*(volatile unsigned *)0x51000014)
0225 #define rTCNTB1         (*(volatile unsigned *)0x51000018)
0226 #define rTCMPB1         (*(volatile unsigned *)0x5100001C)
0227 #define rTCNTO1         (*(volatile unsigned *)0x51000020)
0228 #define rTCNTB2         (*(volatile unsigned *)0x51000024)
0229 #define rTCMPB2         (*(volatile unsigned *)0x51000028)
0230 #define rTCNTO2         (*(volatile unsigned *)0x5100002C)
0231 #define rTCNTB3         (*(volatile unsigned *)0x51000030)
0232 #define rTCMPB3         (*(volatile unsigned *)0x51000034)
0233 #define rTCNTO3         (*(volatile unsigned *)0x51000038)
0234 #define rTCNTB4         (*(volatile unsigned *)0x5100003C)
0235 #define rTCNTO4         (*(volatile unsigned *)0x51000040)
0236
0237
0238 /* USB DEVICE */
0239 #ifdef __BIG_ENDIAN
0240 #define rFUNC_ADDR_REG     (*(volatile unsigned char *)0x52000143)  //Function address
0241 #define rPWR_REG           (*(volatile unsigned char *)0x52000147)  //Power management
0242 #define rEP_INT_REG        (*(volatile unsigned char *)0x5200014b)  //EP Interrupt pending and clear
0243 #define rUSB_INT_REG       (*(volatile unsigned char *)0x5200015b)  //USB Interrupt pending and clear
0244 #define rEP_INT_EN_REG     (*(volatile unsigned char *)0x5200015f)  //Interrupt enable
0245 #define rUSB_INT_EN_REG    (*(volatile unsigned char *)0x5200016f)
0246 #define rFRAME_NUM1_REG    (*(volatile unsigned char *)0x52000173)  //Frame number lower byte
0247 #define rFRAME_NUM2_REG    (*(volatile unsigned char *)0x52000177)  //Frame number higher byte
0248 #define rINDEX_REG         (*(volatile unsigned char *)0x5200017b)  //Register index
0249 #define rMAXP_REG          (*(volatile unsigned char *)0x52000183)  //Endpoint max packet
0250 #define rEP0_CSR           (*(volatile unsigned char *)0x52000187)  //Endpoint 0 status
0251 #define rIN_CSR1_REG       (*(volatile unsigned char *)0x52000187)  //In endpoint control status
0252 #define rIN_CSR2_REG       (*(volatile unsigned char *)0x5200018b)
0253 #define rOUT_CSR1_REG      (*(volatile unsigned char *)0x52000193)  //Out endpoint control status
0254 #define rOUT_CSR2_REG      (*(volatile unsigned char *)0x52000197)
0255 #define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b)  //Endpoint out write count
0256 #define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f)
0257 #define rEP0_FIFO          (*(volatile unsigned char *)0x520001c3)  //Endpoint 0 FIFO
0258 #define rEP1_FIFO          (*(volatile unsigned char *)0x520001c7)  //Endpoint 1 FIFO
0259 #define rEP2_FIFO          (*(volatile unsigned char *)0x520001cb)  //Endpoint 2 FIFO
0260 #define rEP3_FIFO          (*(volatile unsigned char *)0x520001cf)  //Endpoint 3 FIFO
0261 #define rEP4_FIFO          (*(volatile unsigned char *)0x520001d3)  //Endpoint 4 FIFO
0262 #define rEP1_DMA_CON       (*(volatile unsigned char *)0x52000203)  //EP1 DMA interface control
0263 #define rEP1_DMA_UNIT      (*(volatile unsigned char *)0x52000207)  //EP1 DMA Tx unit counter
0264 #define rEP1_DMA_FIFO      (*(volatile unsigned char *)0x5200020b)  //EP1 DMA Tx FIFO counter
0265 #define rEP1_DMA_TTC_L     (*(volatile unsigned char *)0x5200020f)  //EP1 DMA total Tx counter
0266 #define rEP1_DMA_TTC_M     (*(volatile unsigned char *)0x52000213)
0267 #define rEP1_DMA_TTC_H     (*(volatile unsigned char *)0x52000217)
0268 #define rEP2_DMA_CON       (*(volatile unsigned char *)0x5200021b)  //EP2 DMA interface control
0269 #define rEP2_DMA_UNIT      (*(volatile unsigned char *)0x5200021f)  //EP2 DMA Tx unit counter
0270 #define rEP2_DMA_FIFO      (*(volatile unsigned char *)0x52000223)  //EP2 DMA Tx FIFO counter
0271 #define rEP2_DMA_TTC_L     (*(volatile unsigned char *)0x52000227)  //EP2 DMA total Tx counter
0272 #define rEP2_DMA_TTC_M     (*(volatile unsigned char *)0x5200022b)
0273 #define rEP2_DMA_TTC_H     (*(volatile unsigned char *)0x5200022f)
0274 #define rEP3_DMA_CON       (*(volatile unsigned char *)0x52000243)  //EP3 DMA interface control
0275 #define rEP3_DMA_UNIT      (*(volatile unsigned char *)0x52000247)  //EP3 DMA Tx unit counter
0276 #define rEP3_DMA_FIFO      (*(volatile unsigned char *)0x5200024b)  //EP3 DMA Tx FIFO counter
0277 #define rEP3_DMA_TTC_L     (*(volatile unsigned char *)0x5200024f)  //EP3 DMA total Tx counter
0278 #define rEP3_DMA_TTC_M     (*(volatile unsigned char *)0x52000253)
0279 #define rEP3_DMA_TTC_H     (*(volatile unsigned char *)0x52000257)
0280 #define rEP4_DMA_CON       (*(volatile unsigned char *)0x5200025b)  //EP4 DMA interface control
0281 #define rEP4_DMA_UNIT      (*(volatile unsigned char *)0x5200025f)  //EP4 DMA Tx unit counter
0282 #define rEP4_DMA_FIFO      (*(volatile unsigned char *)0x52000263)  //EP4 DMA Tx FIFO counter
0283 #define rEP4_DMA_TTC_L     (*(volatile unsigned char *)0x52000267)  //EP4 DMA total Tx counter
0284 #define rEP4_DMA_TTC_M     (*(volatile unsigned char *)0x5200026b)
0285 #define rEP4_DMA_TTC_H     (*(volatile unsigned char *)0x5200026f)
0286
0287 #else  // Little Endian
0288 #define rFUNC_ADDR_REG     (*(volatile unsigned char *)0x52000140)  //Function address
0289 #define rPWR_REG           (*(volatile unsigned char *)0x52000144)  //Power management
0290 #define rEP_INT_REG        (*(volatile unsigned char *)0x52000148)  //EP Interrupt pending and clear
0291 #define rUSB_INT_REG       (*(volatile unsigned char *)0x52000158)  //USB Interrupt pending and clear
0292 #define rEP_INT_EN_REG     (*(volatile unsigned char *)0x5200015c)  //Interrupt enable
0293 #define rUSB_INT_EN_REG    (*(volatile unsigned char *)0x5200016c)
0294 #define rFRAME_NUM1_REG    (*(volatile unsigned char *)0x52000170)  //Frame number lower byte
0295 #define rFRAME_NUM2_REG    (*(volatile unsigned char *)0x52000174)  //Frame number higher byte
0296 #define rINDEX_REG         (*(volatile unsigned char *)0x52000178)  //Register index
0297 #define rMAXP_REG          (*(volatile unsigned char *)0x52000180)  //Endpoint max packet
0298 #define rEP0_CSR           (*(volatile unsigned char *)0x52000184)  //Endpoint 0 status
0299 #define rIN_CSR1_REG       (*(volatile unsigned char *)0x52000184)  //In endpoint control status
0300 #define rIN_CSR2_REG       (*(volatile unsigned char *)0x52000188)
0301 #define rOUT_CSR1_REG      (*(volatile unsigned char *)0x52000190)  //Out endpoint control status
0302 #define rOUT_CSR2_REG      (*(volatile unsigned char *)0x52000194)
0303 #define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198)  //Endpoint out write count
0304 #define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c)
0305 #define rEP0_FIFO          (*(volatile unsigned char *)0x520001c0)  //Endpoint 0 FIFO
0306 #define rEP1_FIFO          (*(volatile unsigned char *)0x520001c4)  //Endpoint 1 FIFO
0307 #define rEP2_FIFO          (*(volatile unsigned char *)0x520001c8)  //Endpoint 2 FIFO
0308 #define rEP3_FIFO          (*(volatile unsigned char *)0x520001cc)  //Endpoint 3 FIFO
0309 #define rEP4_FIFO          (*(volatile unsigned char *)0x520001d0)  //Endpoint 4 FIFO
0310 #define rEP1_DMA_CON       (*(volatile unsigned char *)0x52000200)  //EP1 DMA interface control
0311 #define rEP1_DMA_UNIT      (*(volatile unsigned char *)0x52000204)  //EP1 DMA Tx unit counter
0312 #define rEP1_DMA_FIFO      (*(volatile unsigned char *)0x52000208)  //EP1 DMA Tx FIFO counter
0313 #define rEP1_DMA_TTC_L     (*(volatile unsigned char *)0x5200020c)  //EP1 DMA total Tx counter
0314 #define rEP1_DMA_TTC_M     (*(volatile unsigned char *)0x52000210)
0315 #define rEP1_DMA_TTC_H     (*(volatile unsigned char *)0x52000214)
0316 #define rEP2_DMA_CON       (*(volatile unsigned char *)0x52000218)  //EP2 DMA interface control
0317 #define rEP2_DMA_UNIT      (*(volatile unsigned char *)0x5200021c)  //EP2 DMA Tx unit counter
0318 #define rEP2_DMA_FIFO      (*(volatile unsigned char *)0x52000220)  //EP2 DMA Tx FIFO counter
0319 #define rEP2_DMA_TTC_L     (*(volatile unsigned char *)0x52000224)  //EP2 DMA total Tx counter
0320 #define rEP2_DMA_TTC_M     (*(volatile unsigned char *)0x52000228)
0321 #define rEP2_DMA_TTC_H     (*(volatile unsigned char *)0x5200022c)
0322 #define rEP3_DMA_CON       (*(volatile unsigned char *)0x52000240)  //EP3 DMA interface control
0323 #define rEP3_DMA_UNIT      (*(volatile unsigned char *)0x52000244)  //EP3 DMA Tx unit counter
0324 #define rEP3_DMA_FIFO      (*(volatile unsigned char *)0x52000248)  //EP3 DMA Tx FIFO counter
0325 #define rEP3_DMA_TTC_L     (*(volatile unsigned char *)0x5200024c)  //EP3 DMA total Tx counter
0326 #define rEP3_DMA_TTC_M     (*(volatile unsigned char *)0x52000250)
0327 #define rEP3_DMA_TTC_H     (*(volatile unsigned char *)0x52000254)
0328 #define rEP4_DMA_CON       (*(volatile unsigned char *)0x52000258)  //EP4 DMA interface control
0329 #define rEP4_DMA_UNIT      (*(volatile unsigned char *)0x5200025c)  //EP4 DMA Tx unit counter
0330 #define rEP4_DMA_FIFO      (*(volatile unsigned char *)0x52000260)  //EP4 DMA Tx FIFO counter
0331 #define rEP4_DMA_TTC_L     (*(volatile unsigned char *)0x52000264)  //EP4 DMA total Tx counter
0332 #define rEP4_DMA_TTC_M     (*(volatile unsigned char *)0x52000268)
0333 #define rEP4_DMA_TTC_H     (*(volatile unsigned char *)0x5200026c)
0334 #endif   // __BIG_ENDIAN
0335
0336 /* WATCH DOG TIMER */
0337 #define rWTCON          (*(volatile unsigned *)0x53000000)
0338 #define rWTDAT          (*(volatile unsigned *)0x53000004)
0339 #define rWTCNT          (*(volatile unsigned *)0x53000008)
0340
0341
0342 /* IIC */
0343 #define rIICCON         (*(volatile unsigned *)0x54000000)
0344 #define rIICSTAT        (*(volatile unsigned *)0x54000004)
0345 #define rIICADD         (*(volatile unsigned *)0x54000008)
0346 #define rIICDS          (*(volatile unsigned *)0x5400000C)
0347
0348
0349 /* IIS */
0350 #define rIISCON         (*(volatile unsigned *)0x55000000)
0351 #define rIISMOD         (*(volatile unsigned *)0x55000004)
0352 #define rIISPSR         (*(volatile unsigned *)0x55000008)
0353 #define rIISFIFCON      (*(volatile unsigned *)0x5500000C)
0354
0355 #ifdef __BIG_ENDIAN
0356 #define IISFIFO          ((volatile unsigned short *)0x55000012)
0357
0358 #else /* Little Endian */
0359 #define IISFIFO          ((volatile unsigned short *)0x55000010)
0360 #endif
0361
0362
0363 /* I/O PORT */
0364 #define rGPACON    (*(volatile unsigned *)0x56000000)   //Port A control
0365 #define rGPADAT    (*(volatile unsigned *)0x56000004)   //Port A data
0366
0367 #define rGPBCON    (*(volatile unsigned *)0x56000010)   //Port B control
0368 #define rGPBDAT    (*(volatile unsigned *)0x56000014)   //Port B data
0369 #define rGPBUP     (*(volatile unsigned *)0x56000018)   //Pull-up control B
0370
0371 #define rGPCCON    (*(volatile unsigned *)0x56000020)   //Port C control
0372 #define rGPCDAT    (*(volatile unsigned *)0x56000024)   //Port C data
0373 #define rGPCUP     (*(volatile unsigned *)0x56000028)   //Pull-up control C
0374
0375 #define rGPDCON    (*(volatile unsigned *)0x56000030)   //Port D control
0376 #define rGPDDAT    (*(volatile unsigned *)0x56000034)   //Port D data
0377 #define rGPDUP     (*(volatile unsigned *)0x56000038)   //Pull-up control D
0378
0379 #define rGPECON    (*(volatile unsigned *)0x56000040)   //Port E control
0380 #define rGPEDAT    (*(volatile unsigned *)0x56000044)   //Port E data
0381 #define rGPEUP     (*(volatile unsigned *)0x56000048)   //Pull-up control E
0382
0383 #define rGPFCON    (*(volatile unsigned *)0x56000050)   //Port F control
0384 #define rGPFDAT    (*(volatile unsigned *)0x56000054)   //Port F data
0385 #define rGPFUP     (*(volatile unsigned *)0x56000058)   //Pull-up control F
0386
0387 #define rGPGCON    (*(volatile unsigned *)0x56000060)   //Port G control
0388 #define rGPGDAT    (*(volatile unsigned *)0x56000064)   //Port G data
0389 #define rGPGUP     (*(volatile unsigned *)0x56000068)   //Pull-up control G
0390
0391 #define rGPHCON    (*(volatile unsigned *)0x56000070)   //Port H control
0392 #define rGPHDAT    (*(volatile unsigned *)0x56000074)   //Port H data
0393 #define rGPHUP     (*(volatile unsigned *)0x56000078)   //Pull-up control H
0394
0395 #define rMISCCR    (*(volatile unsigned *)0x56000080)   //Miscellaneous control
0396 #define rDCLKCON   (*(volatile unsigned *)0x56000084)   //DCLK0/1 control
0397 #define rEXTINT0   (*(volatile unsigned *)0x56000088)   //External interrupt control register 0
0398 #define rEXTINT1   (*(volatile unsigned *)0x5600008c)   //External interrupt control register 1
0399 #define rEXTINT2   (*(volatile unsigned *)0x56000090)   //External interrupt control register 2
0400 #define rEINTFLT0  (*(volatile unsigned *)0x56000094)   //Reserved
0401 #define rEINTFLT1  (*(volatile unsigned *)0x56000098)   //Reserved
0402 #define rEINTFLT2  (*(volatile unsigned *)0x5600009c)   //External interrupt filter control register 2
0403 #define rEINTFLT3  (*(volatile unsigned *)0x560000a0)   //External interrupt filter control register 3
0404 #define rEINTMASK  (*(volatile unsigned *)0x560000a4)   //External interrupt mask
0405 #define rEINTPEND  (*(volatile unsigned *)0x560000a8)   //External interrupt pending
0406 #define rGSTATUS0  (*(volatile unsigned *)0x560000ac)   //External pin status
0407 #define rGSTATUS1  (*(volatile unsigned *)0x560000b0)   //Chip ID(0x32440000)
0408
0409 /* RTC */
0410 #ifdef __BIG_ENDIAN
0411 #define rRTCCON    (*(volatile unsigned char *)0x57000043)  //RTC control
0412 #define rTICNT     (*(volatile unsigned char *)0x57000047)  //Tick time count
0413 #define rRTCALM    (*(volatile unsigned char *)0x57000053)  //RTC alarm control
0414 #define rALMSEC    (*(volatile unsigned char *)0x57000057)  //Alarm second
0415 #define rALMMIN    (*(volatile unsigned char *)0x5700005b)  //Alarm minute
0416 #define rALMHOUR   (*(volatile unsigned char *)0x5700005f)  //Alarm Hour
0417 #define rALMDATE   (*(volatile unsigned char *)0x57000063)  //Alarm date   //edited by junon
0418 #define rALMMON    (*(volatile unsigned char *)0x57000067)  //Alarm month
0419 #define rALMYEAR   (*(volatile unsigned char *)0x5700006b)  //Alarm year
0420 #define rRTCRST    (*(volatile unsigned char *)0x5700006f)  //RTC round reset
0421 #define rBCDSEC    (*(volatile unsigned char *)0x57000073)  //BCD second
0422 #define rBCDMIN    (*(volatile unsigned char *)0x57000077)  //BCD minute
0423 #define rBCDHOUR   (*(volatile unsigned char *)0x5700007b)  //BCD hour
0424 #define rBCDDATE   (*(volatile unsigned char *)0x5700007f)  //BCD date  //edited by junon
0425 #define rBCDDAY    (*(volatile unsigned char *)0x57000083)  //BCD day   //edited by junon
0426 #define rBCDMON    (*(volatile unsigned char *)0x57000087)  //BCD month
0427 #define rBCDYEAR   (*(volatile unsigned char *)0x5700008b)  //BCD year
0428
0429 #else //Little Endian
0430 #define rRTCCON    (*(volatile unsigned char *)0x57000040)  //RTC control
0431 #define rTICNT     (*(volatile unsigned char *)0x57000044)  //Tick time count
0432 #define rRTCALM    (*(volatile unsigned char *)0x57000050)  //RTC alarm control
0433 #define rALMSEC    (*(volatile unsigned char *)0x57000054)  //Alarm second
0434 #define rALMMIN    (*(volatile unsigned char *)0x57000058)  //Alarm minute
0435 #define rALMHOUR   (*(volatile unsigned char *)0x5700005c)  //Alarm Hour
0436 #define rALMDATE   (*(volatile unsigned char *)0x57000060)  //Alarm date  // edited by junon
0437 #define rALMMON    (*(volatile unsigned char *)0x57000064)  //Alarm month
0438 #define rALMYEAR   (*(volatile unsigned char *)0x57000068)  //Alarm year
0439 #define rRTCRST    (*(volatile unsigned char *)0x5700006c)  //RTC round reset
0440 #define rBCDSEC    (*(volatile unsigned char *)0x57000070)  //BCD second
0441 #define rBCDMIN    (*(volatile unsigned char *)0x57000074)  //BCD minute
0442 #define rBCDHOUR   (*(volatile unsigned char *)0x57000078)  //BCD hour
0443 #define rBCDDATE   (*(volatile unsigned char *)0x5700007c)  //BCD date  //edited by junon
0444 #define rBCDDAY    (*(volatile unsigned char *)0x57000080)  //BCD day   //edited by junon
0445 #define rBCDMON    (*(volatile unsigned char *)0x57000084)  //BCD month
0446 #define rBCDYEAR   (*(volatile unsigned char *)0x57000088)  //BCD year
0447 #endif  //RTC
0448
0449
0450 /* ADC */
0451 #define rADCCON         (*(volatile unsigned *)0x58000000)
0452 #define rADCTSC         (*(volatile unsigned *)0x58000004)
0453 #define rADCDLY         (*(volatile unsigned *)0x58000008)
0454 #define rADCDAT0        (*(volatile unsigned *)0x5800000c)
0455 #define rADCDAT1        (*(volatile unsigned *)0x58000010)
0456
0457
0458 /* SPI */
0459 #define rSPCON0    (*(volatile unsigned *)0x59000000)   //SPI0 control
0460 #define rSPSTA0    (*(volatile unsigned *)0x59000004)   //SPI0 status
0461 #define rSPPIN0    (*(volatile unsigned *)0x59000008)   //SPI0 pin control
0462 #define rSPPRE0    (*(volatile unsigned *)0x5900000c)   //SPI0 baud rate prescaler
0463 #define rSPTDAT0   (*(volatile unsigned *)0x59000010)   //SPI0 Tx data
0464 #define rSPRDAT0   (*(volatile unsigned *)0x59000014)   //SPI0 Rx data
0465
0466 #define rSPCON1    (*(volatile unsigned *)0x59000020)   //SPI1 control
0467 #define rSPSTA1    (*(volatile unsigned *)0x59000024)   //SPI1 status
0468 #define rSPPIN1    (*(volatile unsigned *)0x59000028)   //SPI1 pin control
0469 #define rSPPRE1    (*(volatile unsigned *)0x5900002c)   //SPI1 baud rate prescaler
0470 #define rSPTDAT1   (*(volatile unsigned *)0x59000030)   //SPI1 Tx data
0471 #define rSPRDAT1   (*(volatile unsigned *)0x59000034)   //SPI1 Rx data
0472
0473 /* SD interface */
0474 #define rSDICON     (*(volatile unsigned *)0x5a000000)  //SDI control
0475 #define rSDIPRE     (*(volatile unsigned *)0x5a000004)  //SDI baud rate prescaler
0476 #define rSDICARG    (*(volatile unsigned *)0x5a000008)  //SDI command argument
0477 #define rSDICCON    (*(volatile unsigned *)0x5a00000c)  //SDI command control
0478 #define rSDICSTA    (*(volatile unsigned *)0x5a000010)  //SDI command status
0479 #define rSDIRSP0    (*(volatile unsigned *)0x5a000014)  //SDI response 0
0480 #define rSDIRSP1    (*(volatile unsigned *)0x5a000018)  //SDI response 1
0481 #define rSDIRSP2    (*(volatile unsigned *)0x5a00001c)  //SDI response 2
0482 #define rSDIRSP3    (*(volatile unsigned *)0x5a000020)  //SDI response 3
0483 #define rSDIDTIMER  (*(volatile unsigned *)0x5a000024)  //SDI data/busy timer
0484 #define rSDIBSIZE   (*(volatile unsigned *)0x5a000028)  //SDI block size
0485 #define rSDIDATCON  (*(volatile unsigned *)0x5a00002c)  //SDI data control
0486 #define rSDIDATCNT  (*(volatile unsigned *)0x5a000030)  //SDI data remain counter
0487 #define rSDIDATSTA  (*(volatile unsigned *)0x5a000034)  //SDI data status
0488 #define rSDIFSTA    (*(volatile unsigned *)0x5a000038)  //SDI FIFO status
0489 #define rSDIIMSK    (*(volatile unsigned *)0x5a000040)  //SDI interrupt mask. edited for 2440A
0490
0491 #ifdef __BIG_ENDIAN
0492 #define rSDIDAT    (*(volatile unsigned *)0x5a00003F)   //SDI data
0493 #define SDIDAT     0x5a00003F
0494 #else  // Little Endian
0495 #define rSDIDAT    (*(volatile unsigned *)0x5a00003C)   //SDI data
0496 #define SDIDAT     0x5a00003C
0497 #endif   //SD Interface
0498
0499
0500 #define _ISR_STARTADDRESS rtems_vector_table
0501 /* ISR */
0502 #define pISR_RESET      (*(unsigned *)(_ISR_STARTADDRESS+0x0))
0503 #define pISR_UNDEF      (*(unsigned *)(_ISR_STARTADDRESS+0x4))
0504 #define pISR_SWI        (*(unsigned *)(_ISR_STARTADDRESS+0x8))
0505 #define pISR_PABORT     (*(unsigned *)(_ISR_STARTADDRESS+0xC))
0506 #define pISR_DABORT     (*(unsigned *)(_ISR_STARTADDRESS+0x10))
0507 #define pISR_RESERVED   (*(unsigned *)(_ISR_STARTADDRESS+0x14))
0508 #define pISR_IRQ        (*(unsigned *)(_ISR_STARTADDRESS+0x18))
0509 #define pISR_FIQ        (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
0510
0511 #define pISR_EINT0      (*(unsigned *)(_ISR_STARTADDRESS+0x20))
0512 #define pISR_EINT1      (*(unsigned *)(_ISR_STARTADDRESS+0x24))
0513 #define pISR_EINT2      (*(unsigned *)(_ISR_STARTADDRESS+0x28))
0514 #define pISR_EINT3      (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
0515 #define pISR_EINT4_7    (*(unsigned *)(_ISR_STARTADDRESS+0x30))
0516 #define pISR_EINT8_23   (*(unsigned *)(_ISR_STARTADDRESS+0x34))
0517 #define pISR_BAT_FLT    (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
0518 #define pISR_TICK       (*(unsigned *)(_ISR_STARTADDRESS+0x40))
0519 #define pISR_WDT        (*(unsigned *)(_ISR_STARTADDRESS+0x44))
0520 #define pISR_TIMER0     (*(unsigned *)(_ISR_STARTADDRESS+0x48))
0521 #define pISR_TIMER1     (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
0522 #define pISR_TIMER2     (*(unsigned *)(_ISR_STARTADDRESS+0x50))
0523 #define pISR_TIMER3     (*(unsigned *)(_ISR_STARTADDRESS+0x54))
0524 #define pISR_TIMER4     (*(unsigned *)(_ISR_STARTADDRESS+0x58))
0525 #define pISR_UART2      (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
0526 #define pISR_NOTUSED    (*(unsigned *)(_ISR_STARTADDRESS+0x60))
0527 #define pISR_DMA0       (*(unsigned *)(_ISR_STARTADDRESS+0x64))
0528 #define pISR_DMA1       (*(unsigned *)(_ISR_STARTADDRESS+0x68))
0529 #define pISR_DMA2       (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
0530 #define pISR_DMA3       (*(unsigned *)(_ISR_STARTADDRESS+0x70))
0531 #define pISR_SDI        (*(unsigned *)(_ISR_STARTADDRESS+0x74))
0532 #define pISR_SPI0       (*(unsigned *)(_ISR_STARTADDRESS+0x78))
0533 #define pISR_UART1      (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
0534 #define pISR_USBD       (*(unsigned *)(_ISR_STARTADDRESS+0x84))
0535 #define pISR_USBH       (*(unsigned *)(_ISR_STARTADDRESS+0x88))
0536 #define pISR_IIC        (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
0537 #define pISR_UART0      (*(unsigned *)(_ISR_STARTADDRESS+0x90))
0538 #define pISR_SPI1       (*(unsigned *)(_ISR_STARTADDRESS+0x94))
0539 #define pISR_RTC        (*(unsigned *)(_ISR_STARTADDRESS+0x98))
0540 #define pISR_ADC        (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
0541
0542
0543 /* PENDING BIT */
0544 #define BIT_EINT0       (0x1)
0545 #define BIT_EINT1       (0x1<<1)
0546 #define BIT_EINT2       (0x1<<2)
0547 #define BIT_EINT3       (0x1<<3)
0548 #define BIT_EINT4_7     (0x1<<4)
0549 #define BIT_EINT8_23    (0x1<<5)
0550 #define BIT_BAT_FLT     (0x1<<7)
0551 #define BIT_TICK        (0x1<<8)
0552 #define BIT_WDT         (0x1<<9)
0553 #define BIT_TIMER0      (0x1<<10)
0554 #define BIT_TIMER1      (0x1<<11)
0555 #define BIT_TIMER2      (0x1<<12)
0556 #define BIT_TIMER3      (0x1<<13)
0557 #define BIT_TIMER4      (0x1<<14)
0558 #define BIT_UART2       (0x1<<15)
0559 #define BIT_LCD         (0x1<<16)
0560 #define BIT_DMA0        (0x1<<17)
0561 #define BIT_DMA1        (0x1<<18)
0562 #define BIT_DMA2        (0x1<<19)
0563 #define BIT_DMA3        (0x1<<20)
0564 #define BIT_SDI         (0x1<<21)
0565 #define BIT_SPI0        (0x1<<22)
0566 #define BIT_UART1       (0x1<<23)
0567 #define BIT_USBD        (0x1<<25)
0568 #define BIT_USBH        (0x1<<26)
0569 #define BIT_IIC         (0x1<<27)
0570 #define BIT_UART0       (0x1<<28)
0571 #define BIT_SPI1       (0x1<<29)
0572 #define BIT_RTC         (0x1<<30)
0573 #define BIT_ADC         (0x1<<31)
0574 #define BIT_ALLMSK      (0xFFFFFFFF)
0575
0576 #define ClearPending(bit) {\
0577                  rSRCPND = bit;\
0578                  rINTPND = bit;\
0579                  rINTPND;\
0580                  }
0581 /* Wait until rINTPND is changed for the case that the ISR is very short. */
0582 #ifndef ASM
0583 /* Typedefs */
0584 typedef union {
0585   struct _reg {
0586     unsigned SM_BIT:1;   /* Enters STOP mode. This bit isn't be */
0587                            /*    cleared automatically. */
0588     unsigned Reserved:1;    /* SL_IDLE mode option. This bit isn't cleared */
0589                            /*    automatically. To enter SL_IDLE mode, */
0590                            /* CLKCON register has to be 0xe. */
0591     unsigned IDLE_BIT:1;   /* Enters IDLE mode. This bit isn't be cleared */
0592                            /*    automatically. */
0593     unsigned POWER_OFF:1;
0594     unsigned NAND_flash:1;
0595     unsigned LCDC:1;       /* Controls HCLK into LCDC block */
0596     unsigned USB_host:1;   /* Controls HCLK into USB host block */
0597     unsigned USB_device:1; /* Controls PCLK into USB device block */
0598     unsigned PWMTIMER:1;   /* Controls PCLK into PWMTIMER block */
0599     unsigned SDI:1;        /* Controls PCLK into MMC interface block */
0600     unsigned UART0:1;      /* Controls PCLK into UART0 block */
0601     unsigned UART1:1;      /* Controls PCLK into UART1 block */
0602     unsigned UART2:1;      /* Controls PCLK into UART1 block */
0603     unsigned GPIO:1;       /* Controls PCLK into GPIO block */
0604     unsigned RTC:1;        /* Controls PCLK into RTC control block. Even if */
0605                            /*   this bit is cleared to 0, RTC timer is alive. */
0606     unsigned ADC:1;        /* Controls PCLK into ADC block */
0607     unsigned IIC:1;        /* Controls PCLK into IIC block */
0608     unsigned IIS:1;        /* Controls PCLK into IIS block */
0609     unsigned SPI:1;        /* Controls PCLK into SPI block */
0610   } reg;
0611   unsigned long all;
0612 } CLKCON;
0613
0614 typedef union
0615 {
0616   struct {
0617     unsigned ENVID:1;    /* LCD video output and the logic 1=enable/0=disable. */
0618     unsigned BPPMODE:4;  /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */
0619                          /*   1110 = 16 bpp TFT skipmode */
0620     unsigned PNRMODE:2;  /* TFT: 3 */
0621     unsigned MMODE:1;    /* This bit determines the toggle rate of the VM. */
0622                          /*   0 = Each Frame, 1 = The rate defined by the MVAL */
0623     unsigned CLKVAL:10;  /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */
0624     unsigned LINECNT:10; /* (read only) These bits provide the status of the */
0625                          /*   line counter. Down count from LINEVAL to 0 */
0626   } reg;
0627   unsigned long all;
0628 } LCDCON1;
0629
0630 typedef union {
0631   struct {
0632     unsigned VSPW:6;    /* TFT: Vertical sync pulse width determines the */
0633                         /*   VSYNC pulse's high level width by counting the */
0634                         /*   number of inactive lines. */
0635     unsigned VFPD:8;    /* TFT: Vertical front porch is the number of */
0636                         /*   inactive lines at the end of a frame, before */
0637                         /*   vertical synchronization period. */
0638     unsigned LINEVAL:10;  /* TFT/STN: These bits determine the vertical size */
0639                         /*   of LCD panel. */
0640     unsigned VBPD:8;    /* TFT: Vertical back porch is the number of inactive */
0641                         /*   lines at the start of a frame, after */
0642                         /*   vertical synchronization period. */
0643   } reg;
0644   unsigned long all;
0645 } LCDCON2;
0646
0647 typedef union {
0648   struct {
0649     unsigned HFPD:8;    /* TFT: Horizontal front porch is the number of */
0650                         /*   VCLK periods between the end of active data */
0651                         /*   and the rising edge of HSYNC. */
0652     unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */
0653                         /*   size of LCD panel. 2n bytes. */
0654     unsigned HBPD:7;    /* TFT: Horizontal back porch is the number of VCLK */
0655                         /*   periods between the falling edge of HSYNC and */
0656                         /*   the start of active data. */
0657   } reg;
0658   unsigned long all;
0659 } LCDCON3;
0660
0661 typedef union {
0662   struct {
0663     unsigned HSPW:8;     /* TFT: Horizontal sync pulse width determines the */
0664                          /*   HSYNC pulse's high level width by counting the */
0665                          /*   number of the VCLK. */
0666     unsigned MVAL:8;     /* STN: */
0667   } reg;
0668   unsigned long all;
0669 } LCDCON4;
0670
0671 typedef union {
0672   struct {
0673     unsigned HWSWP:1;     /* STN/TFT: Half-Word swap control bit. */
0674                           /*    0 = Swap Disable 1 = Swap Enable */
0675     unsigned BSWP:1;      /* STN/TFT: Byte swap control bit. */
0676                           /*    0 = Swap Disable 1 = Swap Enable */
0677     unsigned ENLEND:1;    /* TFT: LEND output signal enable/disable. */
0678                           /*    0 = Disable LEND signal. */
0679                           /*    1 = Enable LEND signal */
0680     unsigned PWREN:1;
0681     unsigned INVLEND:1;/* TFT: This bit indicates the LEND signal */
0682                           /*    polarity. 0 = normal 1 = inverted */
0683     unsigned INVPWREN:1;
0684     unsigned INVVDEN:1;   /* TFT: This bit indicates the VDEN signal */
0685                           /*    polarity. */
0686                           /*    0 = normal 1 = inverted */
0687     unsigned INVVD:1;     /* STN/TFT: This bit indicates the VD (video data) */
0688                           /*    pulse polarity. 0 = Normal. */
0689                           /*    1 = VD is inverted. */
0690     unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */
0691                           /*    pulse polarity. 0 = normal 1 = inverted */
0692     unsigned INVVLINE:1;  /* STN/TFT: This bit indicates the VLINE/HSYNC */
0693                           /*    pulse polarity. 0 = normal 1 = inverted */
0694     unsigned INVVCLK:1;   /* STN/TFT: This bit controls the polarity of the */
0695                           /*    VCLK active edge. 0 = The video data is */
0696                           /*    fetched at VCLK falling edge. 1 = The video */
0697                           /*    data is fetched at VCLK rising edge */
0698     unsigned FRM565:1;
0699     unsigned BPP24BL:1;
0700     unsigned HSTATUS:2;   /* TFT: Horizontal Status (Read only) */
0701                           /*    00 = HSYNC */
0702                           /*    01 = BACK Porch. */
0703                           /*    10 = ACTIVE */
0704                           /*    11 = FRONT Porch */
0705     unsigned _VSTATUS:2;   /* TFT: Vertical Status (Read only). */
0706                           /*    00 = VSYNC */
0707                           /*    01 = BACK Porch. */
0708                           /*    10 = ACTIVE */
0709                           /*    11 = FRONT Porch */
0710     unsigned RESERVED:16;
0711   } reg;
0712   unsigned long all;
0713 } LCDCON5;
0714
0715 typedef union {
0716   struct {
0717     unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */
0718                           /*    A[21:1] of the start address of the LCD */
0719                           /*    frame buffer. */
0720     unsigned LCDBANK:9;   /* A[28:22] */
0721   } reg;
0722   unsigned long all;
0723 } LCDSADDR1;
0724
0725 typedef union {
0726   struct {
0727     unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/
0728                           /*    of the end address of the LCD frame buffer. */
0729                           /*    LCDBASEL = ((the fame end address) >>1) + 1 */
0730                           /*    = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */
0731   } reg;
0732   unsigned long all;
0733 } LCDSADDR2;
0734
0735 typedef union {
0736   struct {
0737     unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */
0738                           /*    words) This value defines the width of the */
0739                           /*    view port in the frame */
0740     unsigned OFFSIZE:11;  /* Virtual screen offset size(the number of half */
0741                           /*    words) This value defines the difference */
0742                           /*    between the address of the last half word */
0743                           /*    displayed on the previous LCD line and the */
0744                           /*    address of the first half word to be */
0745                           /*    displayed in the new LCD line. */
0746   } reg;
0747   unsigned long all;
0748 } LCDSADDR3;
0749
0750 /*
0751  *
0752  */
0753
0754 typedef union {
0755   struct {
0756     unsigned IISIFENA:1;  /* IIS interface enable (start) */
0757     unsigned IISPSENA:1;  /* IIS prescaler enable */
0758     unsigned RXCHIDLE:1;  /* Receive channel idle command */
0759     unsigned TXCHIDLE:1;  /* Transmit channel idle command */
0760     unsigned RXDMAENA:1;  /* Receive DMA service request enable */
0761     unsigned TXDMAENA:1;  /* Transmit DMA service request enable */
0762     unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */
0763     unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */
0764     unsigned LRINDEX:1;   /* Left/right channel index (read only) */
0765   } reg;
0766   unsigned long all;
0767 } IISCON;
0768
0769 typedef union {
0770   struct {
0771     unsigned SBCLKFS:2;  /* Serial bit clock frequency select */
0772     unsigned MCLKFS:1;   /* Master clock frequency select */
0773     unsigned SDBITS:1;   /* Serial data bit per channel */
0774     unsigned SIFMT:1;    /* Serial interface format */
0775     unsigned ACTLEVCH:1; /* Active level pf left/right channel */
0776     unsigned TXRXMODE:2; /* Transmit/receive mode select */
0777     unsigned MODE:1;     /* Master/slave mode select */
0778   } reg;
0779   unsigned long all;
0780 } IISMOD;
0781
0782 typedef union {
0783   struct {
0784     unsigned PSB:5;      /* Prescaler control B */
0785     unsigned PSA:5;      /* Prescaler control A */
0786   } reg;
0787   unsigned long all;
0788 } IISPSR;
0789
0790 typedef union {
0791   struct {
0792     unsigned RXFIFOCNT:6;  /* (read only) */
0793     unsigned TXFIFOCNT:6;  /* (read only) */
0794     unsigned RXFIFOENA:1;  /* */
0795     unsigned TXFIFOENA:1;  /* */
0796     unsigned RXFIFOMODE:1; /* */
0797     unsigned TXFIFOMODE:1; /* */
0798   } reg;
0799   unsigned long all;
0800 } IISSFIFCON;
0801
0802 typedef union {
0803   struct {
0804     unsigned FENTRY:16;    /* */
0805   } reg;
0806   unsigned long all;
0807 } IISSFIF;
0808 #endif //ASM
0809
0810 #define LCD_WIDTH 240
0811 #define LCD_HEIGHT 320
0812 #define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT))
0813
0814 #define SMDK2410_KEY_SELECT 512
0815 #define SMDK2410_KEY_START 256
0816 #define SMDK2410_KEY_A 64
0817 #define SMDK2410_KEY_B 32
0818 #define SMDK2410_KEY_L 16
0819 #define SMDK2410_KEY_R 128
0820 #define SMDK2410_KEY_UP 8
0821 #define SMDK2410_KEY_DOWN 2
0822 #define SMDK2410_KEY_LEFT 1
0823 #define SMDK2410_KEY_RIGHT 4
0824
0825 #endif /*S3C2410_H_*/