smdk2410/include/s3c2400.h

0001 /************************************************
0002  * NAME     : s3c2400.h
0003  * Version  : 3.7.2002
0004  *
0005  * Based on 24x.h for the Samsung Development Board
0006  ************************************************/
0007
0008 #ifndef S3C2400_H_
0009 #define S3C2400_H_
0010
0011 /* to be used in assembly code */
0012 #define rINTOFFSET_ADDR 0x14400014
0013 /* Memory control */
0014 #define rBWSCON         (*(volatile unsigned *)0x14000000)
0015 #define rBANKCON0       (*(volatile unsigned *)0x14000004)
0016 #define rBANKCON1       (*(volatile unsigned *)0x14000008)
0017 #define rBANKCON2       (*(volatile unsigned *)0x1400000C)
0018 #define rBANKCON3       (*(volatile unsigned *)0x14000010)
0019 #define rBANKCON4       (*(volatile unsigned *)0x14000014)
0020 #define rBANKCON5       (*(volatile unsigned *)0x14000018)
0021 #define rBANKCON6       (*(volatile unsigned *)0x1400001C)
0022 #define rBANKCON7       (*(volatile unsigned *)0x14000020)
0023 #define rREFRESH        (*(volatile unsigned *)0x14000024)
0024 #define rBANKSIZE       (*(volatile unsigned *)0x14000028)
0025 #define rMRSRB6         (*(volatile unsigned *)0x1400002C)
0026 #define rMRSRB7         (*(volatile unsigned *)0x14000030)
0027
0028
0029 /* INTERRUPT */
0030 #define rSRCPND         (*(volatile unsigned *)0x14400000)
0031 #define rINTMOD         (*(volatile unsigned *)0x14400004)
0032 #define rINTMSK         (*(volatile unsigned *)0x14400008)
0033 #define rPRIORITY       (*(volatile unsigned *)0x1440000C)
0034 #define rINTPND         (*(volatile unsigned *)0x14400010)
0035 #define rINTOFFSET      (*(volatile unsigned *)0x14400014)
0036
0037
0038 /* DMA */
0039 #define rDISRC0         (*(volatile unsigned *)0x14600000)
0040 #define rDIDST0         (*(volatile unsigned *)0x14600004)
0041 #define rDCON0          (*(volatile unsigned *)0x14600008)
0042 #define rDSTAT0         (*(volatile unsigned *)0x1460000C)
0043 #define rDCSRC0         (*(volatile unsigned *)0x14600010)
0044 #define rDCDST0         (*(volatile unsigned *)0x14600014)
0045 #define rDMASKTRIG0     (*(volatile unsigned *)0x14600018)
0046 #define rDISRC1         (*(volatile unsigned *)0x14600020)
0047 #define rDIDST1         (*(volatile unsigned *)0x14600024)
0048 #define rDCON1          (*(volatile unsigned *)0x14600028)
0049 #define rDSTAT1         (*(volatile unsigned *)0x1460002C)
0050 #define rDCSRC1         (*(volatile unsigned *)0x14600030)
0051 #define rDCDST1         (*(volatile unsigned *)0x14600034)
0052 #define rDMASKTRIG1     (*(volatile unsigned *)0x14600038)
0053 #define rDISRC2         (*(volatile unsigned *)0x14600040)
0054 #define rDIDST2         (*(volatile unsigned *)0x14600044)
0055 #define rDCON2          (*(volatile unsigned *)0x14600048)
0056 #define rDSTAT2         (*(volatile unsigned *)0x1460004C)
0057 #define rDCSRC2         (*(volatile unsigned *)0x14600050)
0058 #define rDCDST2         (*(volatile unsigned *)0x14600054)
0059 #define rDMASKTRIG2     (*(volatile unsigned *)0x14600058)
0060 #define rDISRC3         (*(volatile unsigned *)0x14600060)
0061 #define rDIDST3         (*(volatile unsigned *)0x14600064)
0062 #define rDCON3          (*(volatile unsigned *)0x14600068)
0063 #define rDSTAT3         (*(volatile unsigned *)0x1460006C)
0064 #define rDCSRC3         (*(volatile unsigned *)0x14600070)
0065 #define rDCDST3         (*(volatile unsigned *)0x14600074)
0066 #define rDMASKTRIG3     (*(volatile unsigned *)0x14600078)
0067
0068
0069 /* CLOCK & POWER MANAGEMENT */
0070 #define rLOCKTIME       (*(volatile unsigned *)0x14800000)
0071 #define rMPLLCON        (*(volatile unsigned *)0x14800004)
0072 #define rUPLLCON        (*(volatile unsigned *)0x14800008)
0073 #define rCLKCON         (*(volatile unsigned *)0x1480000C)
0074 #define rCLKSLOW        (*(volatile unsigned *)0x14800010)
0075 #define rCLKDIVN        (*(volatile unsigned *)0x14800014)
0076
0077
0078 /* LCD CONTROLLER */
0079 #define rLCDCON1        (*(volatile unsigned *)0x14A00000)
0080 #define rLCDCON2        (*(volatile unsigned *)0x14A00004)
0081 #define rLCDCON3        (*(volatile unsigned *)0x14A00008)
0082 #define rLCDCON4        (*(volatile unsigned *)0x14A0000C)
0083 #define rLCDCON5        (*(volatile unsigned *)0x14A00010)
0084 #define rLCDSADDR1      (*(volatile unsigned *)0x14A00014)
0085 #define rLCDSADDR2      (*(volatile unsigned *)0x14A00018)
0086 #define rLCDSADDR3      (*(volatile unsigned *)0x14A0001C)
0087 #define rREDLUT         (*(volatile unsigned *)0x14A00020)
0088 #define rGREENLUT       (*(volatile unsigned *)0x14A00024)
0089 #define rBLUELUT        (*(volatile unsigned *)0x14A00028)
0090 #define rDP1_2          (*(volatile unsigned *)0x14A0002C)
0091 #define rDP4_7          (*(volatile unsigned *)0x14A00030)
0092 #define rDP3_5          (*(volatile unsigned *)0x14A00034)
0093 #define rDP2_3          (*(volatile unsigned *)0x14A00038)
0094 #define rDP5_7          (*(volatile unsigned *)0x14A0003c)
0095 #define rDP3_4          (*(volatile unsigned *)0x14A00040)
0096 #define rDP4_5          (*(volatile unsigned *)0x14A00044)
0097 #define rDP6_7          (*(volatile unsigned *)0x14A00048)
0098 #define rDITHMODE       (*(volatile unsigned *)0x14A0004C)
0099 #define rTPAL           (*(volatile unsigned *)0x14A00050)
0100 #define GP32_PALETTE    (*(volatile unsigned *)0x14A00400)      /* SJS */
0101
0102
0103 /* UART */
0104 #define rULCON0         (*(volatile unsigned char *)0x15000000)
0105 #define rUCON0          (*(volatile unsigned short *)0x15000004)
0106 #define rUFCON0         (*(volatile unsigned char *)0x15000008)
0107 #define rUMCON0         (*(volatile unsigned char *)0x1500000C)
0108 #define rUTRSTAT0       (*(volatile unsigned char *)0x15000010)
0109 #define rUERSTAT0       (*(volatile unsigned char *)0x15000014)
0110 #define rUFSTAT0        (*(volatile unsigned short *)0x15000018)
0111 #define rUMSTAT0        (*(volatile unsigned char *)0x1500001C)
0112 #define rUBRDIV0        (*(volatile unsigned short *)0x15000028)
0113
0114 #define rULCON1         (*(volatile unsigned char *)0x15004000)
0115 #define rUCON1          (*(volatile unsigned short *)0x15004004)
0116 #define rUFCON1         (*(volatile unsigned char *)0x15004008)
0117 #define rUMCON1         (*(volatile unsigned char *)0x1500400C)
0118 #define rUTRSTAT1       (*(volatile unsigned char *)0x15004010)
0119 #define rUERSTAT1       (*(volatile unsigned char *)0x15004014)
0120 #define rUFSTAT1        (*(volatile unsigned short *)0x15004018)
0121 #define rUMSTAT1        (*(volatile unsigned char *)0x1500401C)
0122 #define rUBRDIV1        (*(volatile unsigned short *)0x15004028)
0123
0124 #ifdef __BIG_ENDIAN
0125 #define rUTXH0          (*(volatile unsigned char *)0x15000023)
0126 #define rURXH0          (*(volatile unsigned char *)0x15000027)
0127 #define rUTXH1          (*(volatile unsigned char *)0x15004023)
0128 #define rURXH1          (*(volatile unsigned char *)0x15004027)
0129
0130 #define WrUTXH0(ch)     (*(volatile unsigned char *)0x15000023)=(unsigned char)(ch)
0131 #define RdURXH0()       (*(volatile unsigned char *)0x15000027)
0132 #define WrUTXH1(ch)     (*(volatile unsigned char *)0x15004023)=(unsigned char)(ch)
0133 #define RdURXH1()       (*(volatile unsigned char *)0x15004027)
0134
0135 #define UTXH0           (0x15000020+3)  /* byte_access address by DMA */
0136 #define URXH0           (0x15000024+3)
0137 #define UTXH1           (0x15004020+3)
0138 #define URXH1           (0x15004024+3)
0139
0140 #else /* Little Endian */
0141 #define rUTXH0          (*(volatile unsigned char *)0x15000020)
0142 #define rURXH0          (*(volatile unsigned char *)0x15000024)
0143 #define rUTXH1          (*(volatile unsigned char *)0x15004020)
0144 #define rURXH1          (*(volatile unsigned char *)0x15004024)
0145
0146 #define WrUTXH0(ch)     (*(volatile unsigned char *)0x15000020)=(unsigned char)(ch)
0147 #define RdURXH0()       (*(volatile unsigned char *)0x15000024)
0148 #define WrUTXH1(ch)     (*(volatile unsigned char *)0x15004020)=(unsigned char)(ch)
0149 #define RdURXH1()       (*(volatile unsigned char *)0x15004024)
0150
0151 #define UTXH0           (0x15000020)    /* byte_access address by DMA */
0152 #define URXH0           (0x15000024)
0153 #define UTXH1           (0x15004020)
0154 #define URXH1           (0x15004024)
0155 #endif
0156
0157
0158 /* PWM TIMER */
0159 #define rTCFG0          (*(volatile unsigned *)0x15100000)
0160 #define rTCFG1          (*(volatile unsigned *)0x15100004)
0161 #define rTCON           (*(volatile unsigned *)0x15100008)
0162 #define rTCNTB0         (*(volatile unsigned *)0x1510000C)
0163 #define rTCMPB0         (*(volatile unsigned *)0x15100010)
0164 #define rTCNTO0         (*(volatile unsigned *)0x15100014)
0165 #define rTCNTB1         (*(volatile unsigned *)0x15100018)
0166 #define rTCMPB1         (*(volatile unsigned *)0x1510001C)
0167 #define rTCNTO1         (*(volatile unsigned *)0x15100020)
0168 #define rTCNTB2         (*(volatile unsigned *)0x15100024)
0169 #define rTCMPB2         (*(volatile unsigned *)0x15100028)
0170 #define rTCNTO2         (*(volatile unsigned *)0x1510002C)
0171 #define rTCNTB3         (*(volatile unsigned *)0x15100030)
0172 #define rTCMPB3         (*(volatile unsigned *)0x15100034)
0173 #define rTCNTO3         (*(volatile unsigned *)0x15100038)
0174 #define rTCNTB4         (*(volatile unsigned *)0x1510003C)
0175 #define rTCNTO4         (*(volatile unsigned *)0x15100040)
0176
0177
0178 /* USB DEVICE */
0179 #define rFUNC_ADDR_REG  (*(volatile unsigned *)0x15200140)
0180 #define rPWR_REG        (*(volatile unsigned *)0x15200144)
0181 #define rINT_REG        (*(volatile unsigned *)0x15200148)
0182 #define rINT_MASK_REG   (*(volatile unsigned *)0x1520014C)
0183 #define rFRAME_NUM_REG  (*(volatile unsigned *)0x15200150)
0184 #define rRESUME_CON_REG (*(volatile unsigned *)0x15200154)
0185 #define rEP0_CSR        (*(volatile unsigned *)0x15200160)
0186 #define rEP0_MAXP       (*(volatile unsigned *)0x15200164)
0187 #define rEP0_OUT_CNT    (*(volatile unsigned *)0x15200168)
0188 #define rEP0_FIFO       (*(volatile unsigned *)0x1520016C)
0189 #define rEP1_IN_CSR     (*(volatile unsigned *)0x15200180)
0190 #define rEP1_IN_MAXP    (*(volatile unsigned *)0x15200184)
0191 #define rEP1_FIFO       (*(volatile unsigned *)0x15200188)
0192 #define rEP2_IN_CSR     (*(volatile unsigned *)0x15200190)
0193 #define rEP2_IN_MAXP    (*(volatile unsigned *)0x15200194)
0194 #define rEP2_FIFO       (*(volatile unsigned *)0x15200198)
0195 #define rEP3_OUT_CSR    (*(volatile unsigned *)0x152001A0)
0196 #define rEP3_OUT_MAXP   (*(volatile unsigned *)0x152001A4)
0197 #define rEP3_OUT_CNT    (*(volatile unsigned *)0x152001A8)
0198 #define rEP3_FIFO       (*(volatile unsigned *)0x152001AC)
0199 #define rEP4_OUT_CSR    (*(volatile unsigned *)0x152001B0)
0200 #define rEP4_OUT_MAXP   (*(volatile unsigned *)0x152001B4)
0201 #define rEP4_OUT_CNT    (*(volatile unsigned *)0x152001B8)
0202 #define rEP4_FIFO       (*(volatile unsigned *)0x152001BC)
0203 #define rDMA_CON        (*(volatile unsigned *)0x152001C0)
0204 #define rDMA_UNIT       (*(volatile unsigned *)0x152001C4)
0205 #define rDMA_FIFO       (*(volatile unsigned *)0x152001C8)
0206 #define rDMA_TX         (*(volatile unsigned *)0x152001CC)
0207 #define rTEST_MODE      (*(volatile unsigned *)0x152001F4)
0208 #define rIN_CON_REG     (*(volatile unsigned *)0x152001F8)
0209
0210
0211 /* WATCH DOG TIMER */
0212 #define rWTCON          (*(volatile unsigned *)0x15300000)
0213 #define rWTDAT          (*(volatile unsigned *)0x15300004)
0214 #define rWTCNT          (*(volatile unsigned *)0x15300008)
0215
0216
0217 /* IIC */
0218 #define rIICCON         (*(volatile unsigned *)0x15400000)
0219 #define rIICSTAT        (*(volatile unsigned *)0x15400004)
0220 #define rIICADD         (*(volatile unsigned *)0x15400008)
0221 #define rIICDS          (*(volatile unsigned *)0x1540000C)
0222
0223
0224 /* IIS */
0225 #define rIISCON         (*(volatile unsigned *)0x15508000)
0226 #define rIISMOD         (*(volatile unsigned *)0x15508004)
0227 #define rIISPSR         (*(volatile unsigned *)0x15508008)
0228 #define rIISFIFCON      (*(volatile unsigned *)0x1550800C)
0229
0230 #ifdef __BIG_ENDIAN
0231 #define IISFIF          ((volatile unsigned short *)0x15508012)
0232
0233 #else /* Little Endian */
0234 #define IISFIF          ((volatile unsigned short *)0x15508010)
0235 #endif
0236
0237
0238 /* I/O PORT */
0239 #define rPACON          (*(volatile unsigned *)0x15600000)
0240 #define rPADAT          (*(volatile unsigned *)0x15600004)
0241
0242 #define rPBCON          (*(volatile unsigned *)0x15600008)
0243 #define rPBDAT          (*(volatile unsigned *)0x1560000C)
0244 #define rPBUP           (*(volatile unsigned *)0x15600010)
0245
0246 #define rPCCON          (*(volatile unsigned *)0x15600014)
0247 #define rPCDAT          (*(volatile unsigned *)0x15600018)
0248 #define rPCUP           (*(volatile unsigned *)0x1560001C)
0249
0250 #define rPDCON          (*(volatile unsigned *)0x15600020)
0251 #define rPDDAT          (*(volatile unsigned *)0x15600024)
0252 #define rPDUP           (*(volatile unsigned *)0x15600028)
0253
0254 #define rPECON          (*(volatile unsigned *)0x1560002C)
0255 #define rPEDAT          (*(volatile unsigned *)0x15600030)
0256 #define rPEUP           (*(volatile unsigned *)0x15600034)
0257
0258 #define rPFCON          (*(volatile unsigned *)0x15600038)
0259 #define rPFDAT          (*(volatile unsigned *)0x1560003C)
0260 #define rPFUP           (*(volatile unsigned *)0x15600040)
0261
0262 #define rPGCON          (*(volatile unsigned *)0x15600044)
0263 #define rPGDAT          (*(volatile unsigned *)0x15600048)
0264 #define rPGUP           (*(volatile unsigned *)0x1560004C)
0265
0266 #define rOPENCR         (*(volatile unsigned *)0x15600050)
0267 #define rMISCCR         (*(volatile unsigned *)0x15600054)
0268 #define rEXTINT         (*(volatile unsigned *)0x15600058)
0269
0270
0271 /* RTC */
0272 #ifdef __BIG_ENDIAN
0273 #define rRTCCON         (*(volatile unsigned char *)0x15700043)
0274 #define rRTCALM         (*(volatile unsigned char *)0x15700053)
0275 #define rALMSEC         (*(volatile unsigned char *)0x15700057)
0276 #define rALMMIN         (*(volatile unsigned char *)0x1570005B)
0277 #define rALMHOUR        (*(volatile unsigned char *)0x1570005F)
0278 #define rALMDAY         (*(volatile unsigned char *)0x15700063)
0279 #define rALMMON         (*(volatile unsigned char *)0x15700067)
0280 #define rALMYEAR        (*(volatile unsigned char *)0x1570006B)
0281 #define rRTCRST         (*(volatile unsigned char *)0x1570006F)
0282 #define rBCDSEC         (*(volatile unsigned char *)0x15700073)
0283 #define rBCDMIN         (*(volatile unsigned char *)0x15700077)
0284 #define rBCDHOUR        (*(volatile unsigned char *)0x1570007B)
0285 #define rBCDDAY         (*(volatile unsigned char *)0x1570007F)
0286 #define rBCDDATE        (*(volatile unsigned char *)0x15700083)
0287 #define rBCDMON         (*(volatile unsigned char *)0x15700087)
0288 #define rBCDYEAR        (*(volatile unsigned char *)0x1570008B)
0289 #define rTICINT         (*(volatile unsigned char *)0x15700047)
0290
0291 #else /* Little Endian */
0292 #define rRTCCON         (*(volatile unsigned char *)0x15700040)
0293 #define rRTCALM         (*(volatile unsigned char *)0x15700050)
0294 #define rALMSEC         (*(volatile unsigned char *)0x15700054)
0295 #define rALMMIN         (*(volatile unsigned char *)0x15700058)
0296 #define rALMHOUR        (*(volatile unsigned char *)0x1570005C)
0297 #define rALMDAY         (*(volatile unsigned char *)0x15700060)
0298 #define rALMMON         (*(volatile unsigned char *)0x15700064)
0299 #define rALMYEAR        (*(volatile unsigned char *)0x15700068)
0300 #define rRTCRST         (*(volatile unsigned char *)0x1570006C)
0301 #define rBCDSEC         (*(volatile unsigned char *)0x15700070)
0302 #define rBCDMIN         (*(volatile unsigned char *)0x15700074)
0303 #define rBCDHOUR        (*(volatile unsigned char *)0x15700078)
0304 #define rBCDDAY         (*(volatile unsigned char *)0x1570007C)
0305 #define rBCDDATE        (*(volatile unsigned char *)0x15700080)
0306 #define rBCDMON         (*(volatile unsigned char *)0x15700084)
0307 #define rBCDYEAR        (*(volatile unsigned char *)0x15700088)
0308 #define rTICINT         (*(volatile unsigned char *)0x15700044)
0309 #endif
0310
0311
0312 /* ADC */
0313 #define rADCCON         (*(volatile unsigned *)0x15800000)
0314 #define rADCDAT         (*(volatile unsigned *)0x15800004)
0315
0316
0317 /* SPI */
0318 #define rSPCON          (*(volatile unsigned *)0x15900000)
0319 #define rSPSTA          (*(volatile unsigned *)0x15900004)
0320 #define rSPPIN          (*(volatile unsigned *)0x15900008)
0321 #define rSPPRE          (*(volatile unsigned *)0x1590000C)
0322 #define rSPTDAT         (*(volatile unsigned *)0x15900010)
0323 #define rSPRDAT         (*(volatile unsigned *)0x15900014)
0324
0325
0326 /* MMC INTERFACE */
0327 #define rMMCON          (*(volatile unsigned *)0x15a00000)
0328 #define rMMCRR          (*(volatile unsigned *)0x15a00004)
0329 #define rMMFCON         (*(volatile unsigned *)0x15a00008)
0330 #define rMMSTA          (*(volatile unsigned *)0x15a0000C)
0331 #define rMMFSTA         (*(volatile unsigned *)0x15a00010)
0332 #define rMMPRE          (*(volatile unsigned *)0x15a00014)
0333 #define rMMLEN          (*(volatile unsigned *)0x15a00018)
0334 #define rMMCR7          (*(volatile unsigned *)0x15a0001C)
0335 #define rMMRSP0         (*(volatile unsigned *)0x15a00020)
0336 #define rMMRSP1         (*(volatile unsigned *)0x15a00024)
0337 #define rMMRSP2         (*(volatile unsigned *)0x15a00028)
0338 #define rMMRSP3         (*(volatile unsigned *)0x15a0002C)
0339 #define rMMCMD0         (*(volatile unsigned *)0x15a00030)
0340 #define rMMCMD1         (*(volatile unsigned *)0x15a00034)
0341 #define rMMCR16         (*(volatile unsigned *)0x15a00038)
0342 #define rMMDAT          (*(volatile unsigned *)0x15a0003C)
0343
0344
0345 #define _ISR_STARTADDRESS rtems_vector_table
0346 /* ISR */
0347 #define pISR_RESET      (*(unsigned *)(_ISR_STARTADDRESS+0x0))
0348 #define pISR_UNDEF      (*(unsigned *)(_ISR_STARTADDRESS+0x4))
0349 #define pISR_SWI        (*(unsigned *)(_ISR_STARTADDRESS+0x8))
0350 #define pISR_PABORT     (*(unsigned *)(_ISR_STARTADDRESS+0xC))
0351 #define pISR_DABORT     (*(unsigned *)(_ISR_STARTADDRESS+0x10))
0352 #define pISR_RESERVED   (*(unsigned *)(_ISR_STARTADDRESS+0x14))
0353 #define pISR_IRQ        (*(unsigned *)(_ISR_STARTADDRESS+0x18))
0354 #define pISR_FIQ        (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
0355
0356 #define pISR_EINT0      (*(unsigned *)(_ISR_STARTADDRESS+0x20))
0357 #define pISR_EINT1      (*(unsigned *)(_ISR_STARTADDRESS+0x24))
0358 #define pISR_EINT2      (*(unsigned *)(_ISR_STARTADDRESS+0x28))
0359 #define pISR_EINT3      (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
0360 #define pISR_EINT4      (*(unsigned *)(_ISR_STARTADDRESS+0x30))
0361 #define pISR_EINT5      (*(unsigned *)(_ISR_STARTADDRESS+0x34))
0362 #define pISR_EINT6      (*(unsigned *)(_ISR_STARTADDRESS+0x38))
0363 #define pISR_EINT7      (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
0364 #define pISR_TICK       (*(unsigned *)(_ISR_STARTADDRESS+0x40))
0365 #define pISR_WDT        (*(unsigned *)(_ISR_STARTADDRESS+0x44))
0366 #define pISR_TIMER0     (*(unsigned *)(_ISR_STARTADDRESS+0x48))
0367 #define pISR_TIMER1     (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
0368 #define pISR_TIMER2     (*(unsigned *)(_ISR_STARTADDRESS+0x50))
0369 #define pISR_TIMER3     (*(unsigned *)(_ISR_STARTADDRESS+0x54))
0370 #define pISR_TIMER4     (*(unsigned *)(_ISR_STARTADDRESS+0x58))
0371 #define pISR_UERR01     (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
0372 #define pISR_NOTUSED    (*(unsigned *)(_ISR_STARTADDRESS+0x60))
0373 #define pISR_DMA0       (*(unsigned *)(_ISR_STARTADDRESS+0x64))
0374 #define pISR_DMA1       (*(unsigned *)(_ISR_STARTADDRESS+0x68))
0375 #define pISR_DMA2       (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
0376 #define pISR_DMA3       (*(unsigned *)(_ISR_STARTADDRESS+0x70))
0377 #define pISR_MMC        (*(unsigned *)(_ISR_STARTADDRESS+0x74))
0378 #define pISR_SPI        (*(unsigned *)(_ISR_STARTADDRESS+0x78))
0379 #define pISR_URXD0      (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
0380 #define pISR_URXD1      (*(unsigned *)(_ISR_STARTADDRESS+0x80))
0381 #define pISR_USBD       (*(unsigned *)(_ISR_STARTADDRESS+0x84))
0382 #define pISR_USBH       (*(unsigned *)(_ISR_STARTADDRESS+0x88))
0383 #define pISR_IIC        (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
0384 #define pISR_UTXD0      (*(unsigned *)(_ISR_STARTADDRESS+0x90))
0385 #define pISR_UTXD1      (*(unsigned *)(_ISR_STARTADDRESS+0x94))
0386 #define pISR_RTC        (*(unsigned *)(_ISR_STARTADDRESS+0x98))
0387 #define pISR_ADC        (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
0388
0389
0390 /* PENDING BIT */
0391 #define BIT_EINT0       (0x1)
0392 #define BIT_EINT1       (0x1<<1)
0393 #define BIT_EINT2       (0x1<<2)
0394 #define BIT_EINT3       (0x1<<3)
0395 #define BIT_EINT4       (0x1<<4)
0396 #define BIT_EINT5       (0x1<<5)
0397 #define BIT_EINT6       (0x1<<6)
0398 #define BIT_EINT7       (0x1<<7)
0399 #define BIT_TICK        (0x1<<8)
0400 #define BIT_WDT         (0x1<<9)
0401 #define BIT_TIMER0      (0x1<<10)
0402 #define BIT_TIMER1      (0x1<<11)
0403 #define BIT_TIMER2      (0x1<<12)
0404 #define BIT_TIMER3      (0x1<<13)
0405 #define BIT_TIMER4      (0x1<<14)
0406 #define BIT_UERR01      (0x1<<15)
0407 #define BIT_NOTUSED     (0x1<<16)
0408 #define BIT_DMA0        (0x1<<17)
0409 #define BIT_DMA1        (0x1<<18)
0410 #define BIT_DMA2        (0x1<<19)
0411 #define BIT_DMA3        (0x1<<20)
0412 #define BIT_MMC         (0x1<<21)
0413 #define BIT_SPI         (0x1<<22)
0414 #define BIT_URXD0       (0x1<<23)
0415 #define BIT_URXD1       (0x1<<24)
0416 #define BIT_USBD        (0x1<<25)
0417 #define BIT_USBH        (0x1<<26)
0418 #define BIT_IIC         (0x1<<27)
0419 #define BIT_UTXD0       (0x1<<28)
0420 #define BIT_UTXD1       (0x1<<29)
0421 #define BIT_RTC         (0x1<<30)
0422 #define BIT_ADC         (0x1<<31)
0423 #define BIT_ALLMSK      (0xFFFFFFFF)
0424
0425 #define ClearPending(bit) {\
0426                  rSRCPND = bit;\
0427                  rINTPND = bit;\
0428                  rINTPND;\
0429                  }
0430 /* Wait until rINTPND is changed for the case that the ISR is very short. */
0431
0432 #ifndef ASM
0433 /* Typedefs */
0434 typedef union {
0435   struct _reg {
0436     unsigned STOP_BIT:1;   /* Enters STOP mode. This bit isn't be */
0437                            /*    cleared automatically. */
0438     unsigned SL_IDLE:1;    /* SL_IDLE mode option. This bit isn't cleared */
0439                            /*    automatically. To enter SL_IDLE mode, */
0440                            /* CLKCON register has to be 0xe. */
0441     unsigned IDLE_BIT:1;   /* Enters IDLE mode. This bit isn't be cleared */
0442                            /*    automatically. */
0443     unsigned LCDC:1;       /* Controls HCLK into LCDC block */
0444     unsigned USB_host:1;   /* Controls HCLK into USB host block */
0445     unsigned USB_device:1; /* Controls PCLK into USB device block */
0446     unsigned PWMTIMER:1;   /* Controls PCLK into PWMTIMER block */
0447     unsigned MMC:1;        /* Controls PCLK into MMC interface block */
0448     unsigned UART0:1;      /* Controls PCLK into UART0 block */
0449     unsigned UART1:1;      /* Controls PCLK into UART1 block */
0450     unsigned GPIO:1;       /* Controls PCLK into GPIO block */
0451     unsigned RTC:1;        /* Controls PCLK into RTC control block. Even if */
0452                            /*   this bit is cleared to 0, RTC timer is alive. */
0453     unsigned ADC:1;        /* Controls PCLK into ADC block */
0454     unsigned IIC:1;        /* Controls PCLK into IIC block */
0455     unsigned IIS:1;        /* Controls PCLK into IIS block */
0456     unsigned SPI:1;        /* Controls PCLK into SPI block */
0457   } reg;
0458   unsigned long all;
0459 } CLKCON;
0460
0461 typedef union
0462 {
0463   struct {
0464     unsigned ENVID:1;    /* LCD video output and the logic 1=enable/0=disable. */
0465     unsigned BPPMODE:4;  /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */
0466                          /*   1110 = 16 bpp TFT skipmode */
0467     unsigned PNRMODE:2;  /* TFT: 3 */
0468     unsigned MMODE:1;    /* This bit determines the toggle rate of the VM. */
0469                          /*   0 = Each Frame, 1 = The rate defined by the MVAL */
0470     unsigned CLKVAL:10;  /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */
0471     unsigned LINECNT:10; /* (read only) These bits provide the status of the */
0472                          /*   line counter. Down count from LINEVAL to 0 */
0473   } reg;
0474   unsigned long all;
0475 } LCDCON1;
0476
0477 typedef union {
0478   struct {
0479     unsigned VSPW:6;    /* TFT: Vertical sync pulse width determines the */
0480                         /*   VSYNC pulse's high level width by counting the */
0481                         /*   number of inactive lines. */
0482     unsigned VFPD:8;    /* TFT: Vertical front porch is the number of */
0483                         /*   inactive lines at the end of a frame, before */
0484                         /*   vertical synchronization period. */
0485     unsigned LINEVAL:10;  /* TFT/STN: These bits determine the vertical size */
0486                         /*   of LCD panel. */
0487     unsigned VBPD:8;    /* TFT: Vertical back porch is the number of inactive */
0488                         /*   lines at the start of a frame, after */
0489                         /*   vertical synchronization period. */
0490   } reg;
0491   unsigned long all;
0492 } LCDCON2;
0493
0494 typedef union {
0495   struct {
0496     unsigned HFPD:8;    /* TFT: Horizontal front porch is the number of */
0497                         /*   VCLK periods between the end of active data */
0498                         /*   and the rising edge of HSYNC. */
0499     unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */
0500                         /*   size of LCD panel. 2n bytes. */
0501     unsigned HBPD:7;    /* TFT: Horizontal back porch is the number of VCLK */
0502                         /*   periods between the falling edge of HSYNC and */
0503                         /*   the start of active data. */
0504   } reg;
0505   unsigned long all;
0506 } LCDCON3;
0507
0508 typedef union {
0509   struct {
0510     unsigned HSPW:8;     /* TFT: Horizontal sync pulse width determines the */
0511                          /*   HSYNC pulse's high level width by counting the */
0512                          /*   number of the VCLK. */
0513     unsigned MVAL:8;     /* STN: */
0514     unsigned ADDVAL:8;   /* TFT: Palette Index offset value */
0515     unsigned PALADDEN:1; /* TFT: Palette Index offset enable. */
0516                          /*   0 = Disable 1 = Enable */
0517   } reg;
0518   unsigned long all;
0519 } LCDCON4;
0520
0521 typedef union {
0522   struct {
0523     unsigned HWSWP:1;     /* STN/TFT: Half-Word swap control bit. */
0524                           /*    0 = Swap Disable 1 = Swap Enable */
0525     unsigned BSWP:1;      /* STN/TFT: Byte swap control bit. */
0526                           /*    0 = Swap Disable 1 = Swap Enable */
0527     unsigned ENLEND:1;    /* TFT: LEND output signal enable/disable. */
0528                           /*    0 = Disable LEND signal. */
0529                           /*    1 = Enable LEND signal */
0530     unsigned RESERVED1:1;
0531     unsigned INVENDLINE:1;/* TFT: This bit indicates the LEND signal */
0532                           /*    polarity. 0 = normal 1 = inverted */
0533     unsigned RESERVED2:1;
0534     unsigned INVVDEN:1;   /* TFT: This bit indicates the VDEN signal */
0535                           /*    polarity. */
0536                           /*    0 = normal 1 = inverted */
0537     unsigned INVVD:1;     /* STN/TFT: This bit indicates the VD (video data) */
0538                           /*    pulse polarity. 0 = Normal. */
0539                           /*    1 = VD is inverted. */
0540     unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */
0541                           /*    pulse polarity. 0 = normal 1 = inverted */
0542     unsigned INVVLINE:1;  /* STN/TFT: This bit indicates the VLINE/HSYNC */
0543                           /*    pulse polarity. 0 = normal 1 = inverted */
0544     unsigned INVVCLK:1;   /* STN/TFT: This bit controls the polarity of the */
0545                           /*    VCLK active edge. 0 = The video data is */
0546                           /*    fetched at VCLK falling edge. 1 = The video */
0547                           /*    data is fetched at VCLK rising edge */
0548     unsigned RESERVED3:2;
0549     unsigned SELFREF:1;   /* STN: */
0550     unsigned SLOWCLKSYNC:1; /* STN: */
0551     unsigned RESERVED4:2; /* must be 0 */
0552     unsigned HSTATUS:2;   /* TFT: Horizontal Status (Read only) */
0553                           /*    00 = HSYNC */
0554                           /*    01 = BACK Porch. */
0555                           /*    10 = ACTIVE */
0556                           /*    11 = FRONT Porch */
0557     unsigned _VSTATUS:2;   /* TFT: Vertical Status (Read only). */
0558                           /*    00 = VSYNC */
0559                           /*    01 = BACK Porch. */
0560                           /*    10 = ACTIVE */
0561                           /*    11 = FRONT Porch */
0562   } reg;
0563   unsigned long all;
0564 } LCDCON5;
0565
0566 typedef union {
0567   struct {
0568     unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */
0569                           /*    A[21:1] of the start address of the LCD */
0570                           /*    frame buffer. */
0571     unsigned LCDBANK:7;   /* A[28:22] */
0572   } reg;
0573   unsigned long all;
0574 } LCDSADDR1;
0575
0576 typedef union {
0577   struct {
0578     unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/
0579                           /*    of the end address of the LCD frame buffer. */
0580                           /*    LCDBASEL = ((the fame end address) >>1) + 1 */
0581                           /*    = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */
0582   } reg;
0583   unsigned long all;
0584 } LCDSADDR2;
0585
0586 typedef union {
0587   struct {
0588     unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */
0589                           /*    words) This value defines the width of the */
0590                           /*    view port in the frame */
0591     unsigned OFFSIZE:11;  /* Virtual screen offset size(the number of half */
0592                           /*    words) This value defines the difference */
0593                           /*    between the address of the last half word */
0594                           /*    displayed on the previous LCD line and the */
0595                           /*    address of the first half word to be */
0596                           /*    displayed in the new LCD line. */
0597   } reg;
0598   unsigned long all;
0599 } LCDSADDR3;
0600
0601 /*
0602  *
0603  */
0604
0605 typedef union {
0606   struct {
0607     unsigned IISIFENA:1;  /* IIS interface enable (start) */
0608     unsigned IISPSENA:1;  /* IIS prescaler enable */
0609     unsigned RXCHIDLE:1;  /* Receive channel idle command */
0610     unsigned TXCHIDLE:1;  /* Transmit channel idle command */
0611     unsigned RXDMAENA:1;  /* Receive DMA service request enable */
0612     unsigned TXDMAENA:1;  /* Transmit DMA service request enable */
0613     unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */
0614     unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */
0615     unsigned LRINDEX:1;   /* Left/right channel index (read only) */
0616   } reg;
0617   unsigned long all;
0618 } IISCON;
0619
0620 typedef union {
0621   struct {
0622     unsigned SBCLKFS:2;  /* Serial bit clock frequency select */
0623     unsigned MCLKFS:1;   /* Master clock frequency select */
0624     unsigned SDBITS:1;   /* Serial data bit per channel */
0625     unsigned SIFMT:1;    /* Serial interface format */
0626     unsigned ACTLEVCH:1; /* Active level pf left/right channel */
0627     unsigned TXRXMODE:2; /* Transmit/receive mode select */
0628     unsigned MODE:1;     /* Master/slave mode select */
0629   } reg;
0630   unsigned long all;
0631 } IISMOD;
0632
0633 typedef union {
0634   struct {
0635     unsigned PSB:5;      /* Prescaler control B */
0636     unsigned PSA:5;      /* Prescaler control A */
0637   } reg;
0638   unsigned long all;
0639 } IISPSR;
0640
0641 typedef union {
0642   struct {
0643     unsigned RXFIFOCNT:4;  /* (read only) */
0644     unsigned TXFIFOCNT:4;  /* (read only) */
0645     /*signed RXFIFOENA:1;  /* */
0646     unsigned TXFIFOENA:1;  /* */
0647     unsigned RXFIFOMODE:1; /* */
0648     unsigned TXFIFOMODE:1; /* */
0649   } reg;
0650   unsigned long all;
0651 } IISSFIFCON;
0652
0653 typedef union {
0654   struct {
0655     unsigned FENTRY:16;    /* */
0656   } reg;
0657   unsigned long all;
0658 } IISSFIF;
0659 #endif //ASM
0660
0661 #define LCD_WIDTH 240
0662 #define LCD_HEIGHT 320
0663 #define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT))
0664
0665 #define GP32_KEY_SELECT 512
0666 #define GP32_KEY_START 256
0667 #define GP32_KEY_A 64
0668 #define GP32_KEY_B 32
0669 #define GP32_KEY_L 16
0670 #define GP32_KEY_R 128
0671 #define GP32_KEY_UP 8
0672 #define GP32_KEY_DOWN 2
0673 #define GP32_KEY_LEFT 1
0674 #define GP32_KEY_RIGHT 4
0675
0676 #endif /*S3C2400_H_*/