include/bsp/irq.h

0001 /* irq.h
0002  *
0003  *  Copyright (c) 2010 embedded brains GmbH & Co. KG
0004  *
0005  *  CopyRight (C) 2000 Canon Research France SA.
0006  *  Emmanuel Raguet,  mailto:raguet@crf.canon.fr
0007  *
0008  *  Common file, merged from s3c2400/irq/irq.h and s3c2410/irq/irq.h
0009  */
0010
0011 #ifndef _IRQ_H_
0012 #define _IRQ_H_
0013
0014 #include <rtems.h>
0015 #include <rtems/irq.h>
0016 #include <rtems/irq-extension.h>
0017
0018 #include <s3c24xx.h>
0019
0020 #ifdef CPU_S3C2400
0021   /* possible interrupt sources */
0022 #define BSP_EINT0             0
0023 #define BSP_EINT1             1
0024 #define BSP_EINT2             2
0025 #define BSP_EINT3             3
0026 #define BSP_EINT4             4
0027 #define BSP_EINT5             5
0028 #define BSP_EINT6             6
0029 #define BSP_EINT7             7
0030 #define BSP_INT_TICK          8
0031 #define BSP_INT_WDT           9
0032 #define BSP_INT_TIMER0       10
0033 #define BSP_INT_TIMER1       11
0034 #define BSP_INT_TIMER2       12
0035 #define BSP_INT_TIMER3       13
0036 #define BSP_INT_TIMER4       14
0037 #define BSP_INT_UERR01       15
0038 #define _res0                16
0039 #define BSP_INT_DMA0         17
0040 #define BSP_INT_DMA1         18
0041 #define BSP_INT_DMA2         19
0042 #define BSP_INT_DMA3         20
0043 #define BSP_INT_MMC          21
0044 #define BSP_INT_SPI          22
0045 #define BSP_INT_URXD0        23
0046 #define BSP_INT_URXD1        24
0047 #define BSP_INT_USBD         25
0048 #define BSP_INT_USBH         26
0049 #define BSP_INT_IIC          27
0050 #define BSP_INT_UTXD0        28
0051 #define BSP_INT_UTXD1        29
0052 #define BSP_INT_RTC          30
0053 #define BSP_INT_ADC          31
0054 #define BSP_MAX_INT          32
0055
0056 #elif defined CPU_S3C2410
0057   /* possible interrupt sources */
0058 #define BSP_EINT0             0
0059 #define BSP_EINT1             1
0060 #define BSP_EINT2             2
0061 #define BSP_EINT3             3
0062 #define BSP_EINT4_7           4
0063 #define BSP_EINT8_23          5
0064 #define BSP_nBATT_FLT         7
0065 #define BSP_INT_TICK          8
0066 #define BSP_INT_WDT           9
0067 #define BSP_INT_TIMER0       10
0068 #define BSP_INT_TIMER1       11
0069 #define BSP_INT_TIMER2       12
0070 #define BSP_INT_TIMER3       13
0071 #define BSP_INT_TIMER4       14
0072 #define BSP_INT_UART2        15
0073 #define BSP_INT_LCD          16
0074 #define BSP_INT_DMA0         17
0075 #define BSP_INT_DMA1         18
0076 #define BSP_INT_DMA2         19
0077 #define BSP_INT_DMA3         20
0078 #define BSP_INT_SDI          21
0079 #define BSP_INT_SPI0         22
0080 #define BSP_INT_UART1        23
0081 #define BSP_INT_USBD         25
0082 #define BSP_INT_USBH         26
0083 #define BSP_INT_IIC          27
0084 #define BSP_INT_UART0        28
0085 #define BSP_INT_SPI1         29
0086 #define BSP_INT_RTC          30
0087 #define BSP_INT_ADC          31
0088 #define BSP_MAX_INT          32
0089 #else
0090 #error "Undefined Samsung CPU model"
0091 #endif
0092
0093 #define BSP_INTERRUPT_VECTOR_COUNT BSP_MAX_INT
0094
0095 #endif /* _IRQ_H_ */
0096 /* end of include file */