shared/start/arm-a9mpcore-smp.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMShared
0007  *
0008  * @brief This source file contains the SMP support some Arm devices.
0009  */
0010
0011 /*
0012  * Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <rtems/score/smpimpl.h>
0037
0038 #include <libcpu/arm-cp15.h>
0039
0040 #include <bsp/irq.h>
0041
0042 static void bsp_inter_processor_interrupt(void *arg)
0043 {
0044   _SMP_Inter_processor_interrupt_handler(_Per_CPU_Get());
0045 }
0046
0047 uint32_t _CPU_SMP_Initialize(void)
0048 {
0049   return arm_gic_irq_processor_count();
0050 }
0051
0052 static rtems_interrupt_entry arm_a9mpcore_ipi_entry =
0053   RTEMS_INTERRUPT_ENTRY_INITIALIZER(
0054     bsp_inter_processor_interrupt,
0055     NULL,
0056     "IPI"
0057   );
0058
0059 void _CPU_SMP_Finalize_initialization(uint32_t cpu_count)
0060 {
0061   rtems_status_code sc;
0062
0063   sc = rtems_interrupt_entry_install(
0064     ARM_GIC_IRQ_SGI_0,
0065     RTEMS_INTERRUPT_UNIQUE,
0066     &arm_a9mpcore_ipi_entry
0067   );
0068   _Assert_Unused_variable_equals(sc, RTEMS_SUCCESSFUL);
0069
0070 #if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED)
0071   /*
0072    * When all secondary processors are ready to start multitasking, enable the
0073    * unified L2 cache.
0074    */
0075   _SMP_Wait_for_ready_to_start_multitasking();
0076   rtems_cache_enable_data();
0077 #endif
0078 }
0079
0080 void _CPU_SMP_Prepare_start_multitasking( void )
0081 {
0082   /* Do nothing */
0083 }
0084
0085 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index )
0086 {
0087   arm_gic_trigger_sgi(
0088     ARM_GIC_IRQ_SGI_0,
0089     1U << target_processor_index
0090   );
0091 }