shared/irq/irq-armv7m.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (C) 2020 embedded brains GmbH & Co. KG
0005  * Copyright (C) 2011, 2012 Sebastian Huber
0006  *
0007  * Redistribution and use in source and binary forms, with or without
0008  * modification, are permitted provided that the following conditions
0009  * are met:
0010  * 1. Redistributions of source code must retain the above copyright
0011  *    notice, this list of conditions and the following disclaimer.
0012  * 2. Redistributions in binary form must reproduce the above copyright
0013  *    notice, this list of conditions and the following disclaimer in the
0014  *    documentation and/or other materials provided with the distribution.
0015  *
0016  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0019  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0020  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0021  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0022  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0023  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0024  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0025  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0026  * POSSIBILITY OF SUCH DAMAGE.
0027  */
0028
0029 #include <bsp/irq-generic.h>
0030 #include <bsp.h>
0031 #include <bsp/irq.h>
0032 #include <bsp/linker-symbols.h>
0033 #include <bsp/armv7m-irq.h>
0034
0035 #include <rtems/score/armv7m.h>
0036
0037 #include <string.h>
0038
0039 #ifdef ARM_MULTILIB_ARCH_V7M
0040
0041 rtems_status_code bsp_interrupt_get_attributes(
0042   rtems_vector_number         vector,
0043   rtems_interrupt_attributes *attributes
0044 )
0045 {
0046   attributes->maximum_priority = 255;
0047   attributes->can_get_priority = true;
0048   attributes->can_set_priority = true;
0049   return RTEMS_SUCCESSFUL;
0050 }
0051
0052 rtems_status_code bsp_interrupt_is_pending(
0053   rtems_vector_number vector,
0054   bool               *pending
0055 )
0056 {
0057   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0058   bsp_interrupt_assert(pending != NULL);
0059   *pending = false;
0060   return RTEMS_UNSATISFIED;
0061 }
0062
0063 rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
0064 {
0065   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0066   return RTEMS_UNSATISFIED;
0067 }
0068
0069 rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
0070 {
0071   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0072   return RTEMS_UNSATISFIED;
0073 }
0074
0075 rtems_status_code bsp_interrupt_vector_is_enabled(
0076   rtems_vector_number vector,
0077   bool               *enabled
0078 )
0079 {
0080   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0081   bsp_interrupt_assert(enabled != NULL);
0082   *enabled = false;
0083   return RTEMS_UNSATISFIED;
0084 }
0085
0086 rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
0087 {
0088   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0089   _ARMV7M_NVIC_Set_enable((int) vector);
0090   return RTEMS_SUCCESSFUL;
0091 }
0092
0093 rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
0094 {
0095   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0096   _ARMV7M_NVIC_Clear_enable((int) vector);
0097   return RTEMS_SUCCESSFUL;
0098 }
0099
0100 rtems_status_code bsp_interrupt_set_priority(
0101   rtems_vector_number vector,
0102   uint32_t priority
0103 )
0104 {
0105   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0106
0107   if (priority > 255) {
0108     return RTEMS_INVALID_PRIORITY;
0109   }
0110
0111   _ARMV7M_NVIC_Set_priority((int) vector, (int) priority);
0112   return RTEMS_SUCCESSFUL;
0113 }
0114
0115 rtems_status_code bsp_interrupt_get_priority(
0116   rtems_vector_number vector,
0117   uint32_t *priority
0118 )
0119 {
0120   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0121   bsp_interrupt_assert(priority != NULL);
0122
0123   *priority = (uint32_t) _ARMV7M_NVIC_Get_priority((int) vector);
0124   return RTEMS_SUCCESSFUL;
0125 }
0126
0127 void bsp_interrupt_facility_initialize(void)
0128 {
0129   ARMV7M_Exception_handler *vector_table;
0130   int                       i;
0131
0132   vector_table = (ARMV7M_Exception_handler *) bsp_vector_table_begin;
0133
0134   if (&bsp_vector_table_begin[0] != &bsp_start_vector_table_begin[0]) {
0135     memcpy(
0136       vector_table,
0137       bsp_start_vector_table_begin,
0138       (size_t) bsp_vector_table_size
0139     );
0140   }
0141
0142   _ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR | ARMV7M_SCB_ICSR_PENDSTCLR;
0143
0144   for (i = 0; i < BSP_INTERRUPT_VECTOR_COUNT; ++i) {
0145     _ARMV7M_NVIC_Clear_enable(i);
0146     _ARMV7M_NVIC_Clear_pending(i);
0147     _ARMV7M_NVIC_Set_priority(i, BSP_ARMV7M_IRQ_PRIORITY_DEFAULT);
0148   }
0149
0150   _ARMV7M_SCB->vtor = vector_table;
0151 }
0152
0153 #endif /* ARM_MULTILIB_ARCH_V7M */