shared/clock/arm-generic-timer-aarch32.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMShared
0007  *
0008  * @brief ARM-specific clock driver functions.
0009  */
0010
0011 /*
0012  * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
0013  * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #include <libcpu/arm-cp15.h>
0038 #include <dev/clock/arm-generic-timer.h>
0039
0040 uint64_t arm_gt_clock_get_compare_value(void)
0041 {
0042 #ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
0043   return arm_cp15_get_counter_pl1_virtual_compare_value();
0044 #else
0045   return arm_cp15_get_counter_pl1_physical_compare_value();
0046 #endif
0047 }
0048
0049 void arm_gt_clock_set_compare_value(uint64_t cval)
0050 {
0051 #ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
0052   arm_cp15_set_counter_pl1_virtual_compare_value(cval);
0053 #else
0054   arm_cp15_set_counter_pl1_physical_compare_value(cval);
0055 #endif
0056 }
0057
0058 uint64_t arm_gt_clock_get_count(void)
0059 {
0060 #ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
0061   return arm_cp15_get_counter_virtual_count();
0062 #else
0063   return arm_cp15_get_counter_physical_count();
0064 #endif
0065 }
0066
0067 void arm_gt_clock_set_control(uint32_t ctl)
0068 {
0069 #ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
0070   arm_cp15_set_counter_pl1_virtual_timer_control(ctl);
0071 #else
0072   arm_cp15_set_counter_pl1_physical_timer_control(ctl);
0073 #endif
0074 }