shared/cache/cache-v7m.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (c) 2016 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <rtems.h>
0029 #include <chip.h>
0030
0031 #define CPU_DATA_CACHE_ALIGNMENT 32
0032
0033 #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
0034
0035 #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
0036
0037 static inline void _CPU_cache_flush_data_range(
0038   const void *d_addr,
0039   size_t n_bytes
0040 )
0041 {
0042   SCB_CleanInvalidateDCache_by_Addr(
0043     RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr),
0044     n_bytes
0045   );
0046 }
0047
0048 static inline void _CPU_cache_invalidate_data_range(
0049   const void *d_addr,
0050   size_t n_bytes
0051 )
0052 {
0053   SCB_InvalidateDCache_by_Addr(
0054     RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr),
0055     n_bytes
0056   );
0057 }
0058
0059 static inline void _CPU_cache_freeze_data(void)
0060 {
0061   /* TODO */
0062 }
0063
0064 static inline void _CPU_cache_unfreeze_data(void)
0065 {
0066   /* TODO */
0067 }
0068
0069 static inline void _CPU_cache_invalidate_instruction_range(
0070   const void *i_addr,
0071   size_t n_bytes
0072 )
0073 {
0074   rtems_interrupt_level level;
0075
0076   rtems_interrupt_disable(level);
0077   SCB_InvalidateICache();
0078   rtems_interrupt_enable(level);
0079 }
0080
0081 static inline void _CPU_cache_freeze_instruction(void)
0082 {
0083   /* TODO */
0084 }
0085
0086 static inline void _CPU_cache_unfreeze_instruction(void)
0087 {
0088   /* TODO */
0089 }
0090
0091 static inline void _CPU_cache_flush_entire_data(void)
0092 {
0093   rtems_interrupt_level level;
0094
0095   rtems_interrupt_disable(level);
0096   SCB_CleanDCache();
0097   rtems_interrupt_enable(level);
0098 }
0099
0100 static inline void _CPU_cache_invalidate_entire_data(void)
0101 {
0102   rtems_interrupt_level level;
0103
0104   rtems_interrupt_disable(level);
0105   SCB_InvalidateDCache();
0106   rtems_interrupt_enable(level);
0107 }
0108
0109 static inline void _CPU_cache_enable_data(void)
0110 {
0111   rtems_interrupt_level level;
0112
0113   rtems_interrupt_disable(level);
0114   SCB_EnableDCache();
0115   rtems_interrupt_enable(level);
0116 }
0117
0118 static inline void _CPU_cache_disable_data(void)
0119 {
0120   rtems_interrupt_level level;
0121
0122   rtems_interrupt_disable(level);
0123   SCB_DisableDCache();
0124   rtems_interrupt_enable(level);
0125 }
0126
0127 static inline void _CPU_cache_invalidate_entire_instruction(void)
0128 {
0129   rtems_interrupt_level level;
0130
0131   rtems_interrupt_disable(level);
0132   SCB_InvalidateICache();
0133   rtems_interrupt_enable(level);
0134 }
0135
0136 static inline void _CPU_cache_enable_instruction(void)
0137 {
0138   rtems_interrupt_level level;
0139
0140   rtems_interrupt_disable(level);
0141   SCB_EnableICache();
0142   rtems_interrupt_enable(level);
0143 }
0144
0145 static inline void _CPU_cache_disable_instruction(void)
0146 {
0147   rtems_interrupt_level level;
0148
0149   rtems_interrupt_disable(level);
0150   SCB_DisableICache();
0151   rtems_interrupt_enable(level);
0152 }
0153
0154 #include "../../shared/cache/cacheimpl.h"