shared/cache/cache-v7ar-disable-data.S

0001 /*
0002  * SPDX-License-Identifier: BSD-2-Clause
0003  *
0004  * Copyright (C) 2018 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <rtems/asm.h>
0029
0030 #include <dev/cache/arm-data-cache-loop-set-way.h>
0031
0032 #if __ARM_ARCH >= 7 && (__ARM_ARCH_PROFILE == 'A' || __ARM_ARCH_PROFILE == 'R')
0033     .globl  rtems_cache_disable_data
0034
0035     .syntax unified
0036     .section    .text
0037     .arm
0038
0039     /*
0040      * This function disables the data cache on an ARMv7-AR compatible
0041      * processor.
0042      */
0043 FUNCTION_ENTRY(rtems_cache_disable_data)
0044     /* Disable interrupts */
0045     mrs r0, CPSR
0046     orr r1, r0, #0x80
0047     msr CPSR_fc, r1
0048
0049     stmdb   sp!, {r4 - r11, lr}
0050     dmb
0051
0052     /* Disable data cache in SCTLR */
0053     mrc p15, 0, r1, c1, c0, 0
0054     bic r1, r1, #0x4
0055     mcr p15, 0, r1, c1, c0, 0
0056     isb
0057
0058     /*
0059      * Clean and invalidate the sets and ways of all data or unified cache
0060      * levels using DCCISW (Data Cache line Clean and Invalidate by
0061      * Set/Way).
0062      */
0063     ARM_DATA_CACHE_LOOP_SET_WAY c14
0064
0065     /* Restore interrupts */
0066     msr CPSR_fc, r0
0067
0068     ldmia   sp!, {r4 - r11, pc}
0069 #endif