rtl22xx/start/start.S

0001 /*
0002  * Philips LPC22XX/LPC21xx Startup code
0003  *
0004  * Copyright (c) 2007 Ray Xu<rayx.cn@gmail.com>
0005  * Change from CSB337's code by Jay Monkman <jtm@lopingdog.com>
0006  *  The license and distribution terms for this file may be
0007  *  found in the file LICENSE in this distribution or at
0008  *  http://www.rtems.org/license/LICENSE.
0009 */
0010
0011 #include <rtems/asm.h>
0012 #include <rtems/score/cpu.h>
0013
0014 .text
0015 .code   32
0016 .globl  _start
0017 _start:
0018         /*
0019          * Since I don't plan to return to the bootloader,
0020          * I don't have to save the registers.
0021          */
0022
0023         /* Set end of interrupt stack area */
0024         ldr     r7, =_ISR_Stack_area_end
0025
0026         /* Enter FIQ mode and set up the FIQ stack pointer */
0027         mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
0028         msr     cpsr, r0
0029         ldr     r1, =bsp_stack_fiq_size
0030         mov     sp, r7
0031         sub     r7, r7, r1
0032
0033         /* Enter ABT mode and set up the ABT stack pointer */
0034         mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
0035         msr     cpsr, r0
0036         ldr     r1, =bsp_stack_abt_size
0037         mov     sp, r7
0038         sub     r7, r7, r1
0039
0040         /* Enter UND mode and set up the UND stack pointer */
0041         mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
0042         msr     cpsr, r0
0043         ldr     r1, =bsp_stack_und_size
0044         mov     sp, r7
0045         sub     r7, r7, r1
0046
0047         /* Enter IRQ mode and set up the IRQ stack pointer */
0048         mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
0049         msr     cpsr, r0
0050         mov     sp, r7
0051
0052         /*
0053          * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
0054          * (interrupts are disabled).
0055          */
0056         mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
0057         msr     cpsr, r0
0058         mov     sp, r7
0059
0060         /* Stay in SVC mode */
0061
0062         /*
0063          * Initialize the exception vectors. This includes the
0064          * exceptions vectors (0x00000000-0x0000001c), and the
0065          * pointers to the exception handlers (0x00000020-0x0000003c).
0066          */
0067         mov     r0, #0
0068         adr     r1, vector_block
0069         ldmia   r1!, {r2-r9}
0070         stmia   r0!, {r2-r9}
0071
0072         ldmia   r1!, {r2-r9}
0073         stmia   r0!, {r2-r9}
0074
0075
0076         /* zero the bss */
0077         ldr     r1, =bsp_section_bss_end
0078         ldr     r0, =bsp_section_bss_begin
0079
0080 _bss_init:
0081         mov     r2, #0
0082         cmp     r0, r1
0083         strlot  r2, [r0], #4
0084         blo     _bss_init        /* loop while r0 < r1 */
0085
0086
0087         /* Now we are prepared to start the BSP's C code */
0088         mov     r0, #0
0089 #ifdef __thumb__
0090     ldr r3, =boot_card
0091         bx      r3
0092 #else
0093         bl      boot_card
0094
0095
0096         /*
0097          * Theoretically, we could return to what started us up,
0098          * but we'd have to have saved the registers and stacks.
0099          * Instead, we'll just reset.
0100          */
0101         bl      bsp_reset
0102 #endif
0103     .code   32
0104
0105         /* We shouldn't get here. If we do, hang */
0106 _hang:  b       _hang
0107
0108
0109 /*******************************************************
0110  standard exception vectors table
0111  *** Must be located at address 0
0112 ********************************************************/
0113
0114 vector_block:
0115         ldr    pc, handler_addr_reset
0116         ldr    pc, handler_addr_undef
0117         ldr    pc, handler_addr_swi
0118         ldr    pc, handler_addr_prefetch
0119         ldr    pc, handler_addr_abort
0120         nop
0121         ldr    pc, handler_addr_irq
0122         ldr    pc, handler_addr_fiq
0123
0124 handler_addr_reset:
0125         .word  _start
0126
0127 handler_addr_undef:
0128         .word  _ARMV4_Exception_undef_default
0129
0130 handler_addr_swi:
0131         .word  _ARMV4_Exception_swi_default
0132
0133 handler_addr_prefetch:
0134         .word  _ARMV4_Exception_pref_abort_default
0135
0136 handler_addr_abort:
0137         .word  _ARMV4_Exception_data_abort_default
0138
0139 handler_addr_reserved:
0140         .word  0
0141
0142 handler_addr_irq:
0143         .word  _ARMV4_Exception_interrupt
0144
0145 handler_addr_fiq:
0146         .word  _ARMV4_Exception_fiq_default