rtl22xx/irq/irq.c

0001 /*
0002  * Philps LPC22XX Interrupt handler
0003  *
0004  * Copyright (c) 2010 embedded brains GmbH & Co. KG
0005  *
0006  * Copyright (c)  2006 by Ray<rayx.cn@gmail.com>  to support LPC ARM
0007  *  The license and distribution terms for this file may be
0008  *  found in the file LICENSE in this distribution or at
0009  *  http://www.rtems.org/license/LICENSE.
0010  */
0011
0012 #include <rtems/score/armv4.h>
0013
0014 #include <bsp.h>
0015 #include <bsp/irq.h>
0016 #include <bsp/irq-generic.h>
0017
0018 #include <lpc22xx.h>
0019
0020 void bsp_interrupt_dispatch(void)
0021 {
0022   rtems_vector_number vector = 31 - __builtin_clz(VICIRQStatus);
0023
0024   bsp_interrupt_handler_dispatch(vector);
0025
0026   VICVectAddr = 0;
0027 }
0028
0029 rtems_status_code bsp_interrupt_get_attributes(
0030   rtems_vector_number         vector,
0031   rtems_interrupt_attributes *attributes
0032 )
0033 {
0034   return RTEMS_SUCCESSFUL;
0035 }
0036
0037 rtems_status_code bsp_interrupt_is_pending(
0038   rtems_vector_number vector,
0039   bool               *pending
0040 )
0041 {
0042   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0043   bsp_interrupt_assert(pending != NULL);
0044   *pending = false;
0045   return RTEMS_UNSATISFIED;
0046 }
0047
0048 rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
0049 {
0050   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0051   return RTEMS_UNSATISFIED;
0052 }
0053
0054 rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
0055 {
0056   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0057   return RTEMS_UNSATISFIED;
0058 }
0059
0060 rtems_status_code bsp_interrupt_vector_is_enabled(
0061   rtems_vector_number vector,
0062   bool               *enabled
0063 )
0064 {
0065   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0066   bsp_interrupt_assert(enabled != NULL);
0067   *enabled = false;
0068   return RTEMS_UNSATISFIED;
0069 }
0070
0071 rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
0072 {
0073   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0074   VICIntEnable |= 1 << vector;
0075   return RTEMS_SUCCESSFUL;
0076 }
0077
0078 rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
0079 {
0080   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0081   VICIntEnClr = 1 << vector;
0082   return RTEMS_SUCCESSFUL;
0083 }
0084
0085 rtems_status_code bsp_interrupt_set_priority(
0086   rtems_vector_number vector,
0087   uint32_t priority
0088 )
0089 {
0090   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0091   return RTEMS_UNSATISFIED;
0092 }
0093
0094 rtems_status_code bsp_interrupt_get_priority(
0095   rtems_vector_number vector,
0096   uint32_t *priority
0097 )
0098 {
0099   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0100   bsp_interrupt_assert(priority != NULL);
0101   return RTEMS_UNSATISFIED;
0102 }
0103
0104 void bsp_interrupt_facility_initialize(void)
0105 {
0106   volatile uint32_t *ctrl = (volatile uint32_t *) VICVectCntlBase;
0107   size_t i = 0;
0108
0109   /* Disable all interrupts */
0110   VICIntEnClr = 0xffffffff;
0111
0112   /* Use IRQ category */
0113   VICIntSelect = 0;
0114
0115   /* Enable access in USER mode */
0116   VICProtection = 0;
0117
0118   for (i = 0; i < 16; ++i) {
0119     /* Disable vector mode */
0120     ctrl [i] = 0;
0121
0122     /* Acknowledge interrupts for all priorities */
0123     VICVectAddr = 0;
0124   }
0125
0126   /* Acknowledge interrupts for all priorities */
0127   VICVectAddr = 0;
0128
0129   /* Install the IRQ exception handler */
0130   _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
0131 }