rtl22xx/console/lpc22xx_uart.h

0001 /**
0002  * @file
0003  * @ingroup rtl22xx_uart
0004  * @brief UART support.
0005  */
0006
0007 #ifndef LPC22XX_UART_H
0008 #define LPC22XX_UART_H
0009
0010 /**
0011  * @defgroup rtl22xx_uart UART Support
0012  * @ingroup RTEMSBSPsARMRTL22XX
0013  * @brief UART (Universal Asynchronous Reciever/Transmitter) Support
0014  * @{
0015  */
0016
0017 #define FIFODEEP    16
0018
0019 #define BD115200    115200
0020 #define BD38400     38400
0021 #define BD9600      9600
0022
0023 /** @brief PINSEL0 Value for UART0 */
0024 #define U0_PINSEL       (0x00000005)
0025 /** @brief PINSEL0 Mask for UART0 */
0026 #define U0_PINMASK      (0x0000000F)
0027 /** @brief PINSEL0 Value for UART1 */
0028 #define U1_PINSEL       (0x00050000)
0029 /** @brief PINSEL0 Mask for UART1 */
0030 #define U1_PINMASK      (0x000F0000)
0031
0032 /**
0033  * @name Uart line control register bit descriptions
0034  * @{
0035  */
0036
0037 #define LCR_WORDLENTH_BIT         0
0038 #define LCR_STOPBITSEL_BIT        2
0039 #define LCR_PARITYENBALE_BIT      3
0040 #define LCR_PARITYSEL_BIT         4
0041 #define LCR_BREAKCONTROL_BIT      6
0042 #define LCR_DLAB_BIT              7
0043
0044 /** @} */
0045
0046 /**
0047  * @name Line Control Register bit definitions
0048  * @{
0049  */
0050
0051 /** @brief 5-bit character length */
0052 #define ULCR_CHAR_5         (0 << 0)
0053 /** @brief 6-bit character length */
0054 #define ULCR_CHAR_6         (1 << 0)
0055 /** @brief 7-bit character length */
0056 #define ULCR_CHAR_7         (2 << 0)
0057 /** @brief 8-bit character length */
0058 #define ULCR_CHAR_8         (3 << 0)
0059 /** @brief no stop bits */
0060 #define ULCR_STOP_0         (0 << 2)
0061 /** @brief 1 stop bit */
0062 #define ULCR_STOP_1         (1 << 2)
0063 /** @brief No Parity */
0064 #define ULCR_PAR_NO         (0 << 3)
0065 /** @brief Odd Parity */
0066 #define ULCR_PAR_ODD        (1 << 3)
0067 /** @brief Even Parity */
0068 #define ULCR_PAR_EVEN       (3 << 3)
0069 /** @brief MARK "1" Parity */
0070 #define ULCR_PAR_MARK       (5 << 3)
0071 /** @brief SPACE "0" Paruty */
0072 #define ULCR_PAR_SPACE      (7 << 3)
0073 /** @brief Output BREAK line condition */
0074 #define ULCR_BREAK_ENABLE   (1 << 6)
0075 /** @brief Enable Divisor Latch Access */
0076 #define ULCR_DLAB_ENABLE    (1 << 7)
0077
0078 /** @} */
0079
0080 /**
0081  * @name Modem Control Register bit definitions
0082  * @{
0083  */
0084
0085 /** @brief Data Terminal Ready */
0086 #define UMCR_DTR            (1 << 0)
0087 /** @brief Request To Send */
0088 #define UMCR_RTS            (1 << 1)
0089 /** @brief Loopback */
0090 #define UMCR_LB             (1 << 4)
0091
0092 /** @} */
0093
0094 /**
0095  * @name  Line Status Register bit definitions
0096  * @{
0097  */
0098
0099 /** @brief Receive Data Ready */
0100 #define ULSR_RDR            (1 << 0)
0101 /** @brief Overrun Error */
0102 #define ULSR_OE             (1 << 1)
0103 /** @brief Parity Error */
0104 #define ULSR_PE             (1 << 2)
0105 /** @brief Framing Error */
0106 #define ULSR_FE             (1 << 3)
0107 /** @brief Break Interrupt */
0108 #define ULSR_BI             (1 << 4)
0109 /** @brief Transmit Holding Register Empty */
0110 #define ULSR_THRE           (1 << 5)
0111 /** @brief Transmitter Empty */
0112 #define ULSR_TEMT           (1 << 6)
0113 /** @brief Error in Receive FIFO */
0114 #define ULSR_RXFE           (1 << 7)
0115 #define ULSR_ERR_MASK       0x1E
0116
0117 /** @} */
0118
0119 /**
0120  * @name Modem Status Register bit definitions
0121  * @{
0122  */
0123
0124 /** @brief Delta Clear To Send */
0125 #define UMSR_DCTS           (1 << 0)
0126 /** @brief Delta Data Set Ready */
0127 #define UMSR_DDSR           (1 << 1)
0128 /** @brief Trailing Edge Ring Indicator */
0129 #define UMSR_TERI           (1 << 2)
0130 /** @brief Delta Data Carrier Detect */
0131 #define UMSR_DDCD           (1 << 3)
0132 /** @brief Clear To Send */
0133 #define UMSR_CTS            (1 << 4)
0134 /** @brief Data Set Ready */
0135 #define UMSR_DSR            (1 << 5)
0136 /** @brief Ring Indicator */
0137 #define UMSR_RI             (1 << 6)
0138 /** @brief Data Carrier Detect */
0139 #define UMSR_DCD            (1 << 7)
0140
0141 /** @} */
0142
0143 /**
0144  * @name Uart Interrupt Identification
0145  * @{
0146  */
0147
0148 #define IIR_RSL                   0x3
0149 #define IIR_RDA                   0x2
0150 #define IIR_CTI                   0x6
0151 #define IIR_THRE                  0x1
0152
0153 /** @} */
0154
0155 /**
0156  * @name  Uart Interrupt Enable Type
0157  * @{
0158  */
0159
0160 #define IER_RBR                   0x1
0161 #define IER_THRE                  0x2
0162 #define IER_RLS                   0x4
0163
0164 /** @} */
0165
0166 /**
0167  * @name Uart Receiver Errors
0168  * @{
0169  */
0170
0171 #define RC_FIFO_OVERRUN_ERR       0x1
0172 #define RC_OVERRUN_ERR            0x2
0173 #define RC_PARITY_ERR             0x4
0174 #define RC_FRAMING_ERR            0x8
0175 #define RC_BREAK_IND              0x10
0176
0177 /** @} */
0178
0179 typedef enum {
0180   UART0 = 0,
0181   UART1
0182 } LPC_UartChanel_t;
0183
0184 /** @} */
0185
0186 #endif
0187