File indexing completed on 2025-05-11 08:23:04
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028 #define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION
0029
0030 #include <bsp.h>
0031 #include <bsp/start.h>
0032 #include <bsp/arm-cp15-start.h>
0033 #include <bsp/arm-a9mpcore-start.h>
0034
0035 #ifdef RTEMS_SMP
0036 #include <rtems/score/smpimpl.h>
0037 #endif
0038
0039 BSP_START_DATA_SECTION static const arm_cp15_start_section_config
0040 rvpbxa9_mmu_config_table[] = {
0041 ARMV7_CP15_START_DEFAULT_SECTIONS,
0042 {
0043 .begin = 0x10000000U,
0044 .end = 0x10020000U,
0045 .flags = ARMV7_MMU_DEVICE
0046 }, {
0047 .begin = 0x1f000000U,
0048 .end = 0x20000000U,
0049 .flags = ARMV7_MMU_DEVICE
0050 }, {
0051 .begin = 0x4e000000U,
0052 .end = 0x4f000000U,
0053 .flags = ARMV7_MMU_DEVICE
0054 }
0055 };
0056
0057 BSP_START_TEXT_SECTION static void setup_mmu_and_cache(void)
0058 {
0059 uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
0060 ARM_CP15_CTRL_A,
0061 ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
0062 );
0063
0064 arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
0065 ctrl,
0066 (uint32_t *) bsp_translation_table_base,
0067 ARM_MMU_DEFAULT_CLIENT_DOMAIN,
0068 &rvpbxa9_mmu_config_table[0],
0069 RTEMS_ARRAY_SIZE(rvpbxa9_mmu_config_table)
0070 );
0071 }
0072
0073 BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
0074 {
0075 #ifdef RTEMS_SMP
0076 uint32_t cpu_index_self = _SMP_Get_current_processor();
0077
0078
0079
0080
0081
0082
0083 if (cpu_index_self != 0 && !_SMP_Should_start_processor(cpu_index_self)) {
0084 while (true) {
0085 _ARM_Wait_for_event();
0086 }
0087 }
0088 #endif
0089
0090 arm_a9mpcore_start_hook_0();
0091 }
0092
0093 BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
0094 {
0095 arm_a9mpcore_start_hook_1();
0096 bsp_start_copy_sections();
0097 setup_mmu_and_cache();
0098 bsp_start_clear_bss();
0099 }