include/bsp/raspberrypi.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup raspberrypi_reg
0005  *
0006  * @brief Register definitions.
0007  */
0008
0009 /*
0010  *  Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com>
0011  *  Copyright (c) 2013 Alan Cudmore.
0012  *  Copyright (c) 2015 Yang Qiao
0013  *
0014  *  The license and distribution terms for this file may be
0015  *  found in the file LICENSE in this distribution or at
0016  *
0017  *  http://www.rtems.org/license/LICENSE
0018  *
0019  */
0020
0021 #ifndef LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H
0022 #define LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H
0023
0024 #include <bspopts.h>
0025 #include <stdint.h>
0026 #include <bsp/utility.h>
0027
0028 /**
0029  * @defgroup raspberrypi_reg Register Definitions
0030  *
0031  * @ingroup RTEMSBSPsARMRaspberryPi
0032  *
0033  * @brief Register Definitions
0034  *
0035  * @{
0036  */
0037
0038 /**
0039  * @name Register Macros
0040  *
0041  * @{
0042  */
0043
0044 #define BCM2835_REG(x)           (*(volatile uint32_t *)(x))
0045 #define BCM2835_BIT(n)           (1 << (n))
0046
0047 /** @} */
0048
0049 /**
0050  * @name Peripheral Base Register Address
0051  *
0052  * @{
0053  */
0054
0055 #if (BSP_IS_RPI2 == 1)
0056   #define RPI_PERIPHERAL_BASE    0x3F000000
0057   #define BASE_OFFSET            0X3F000000
0058 #else
0059   #define RPI_PERIPHERAL_BASE    0x20000000
0060   #define BASE_OFFSET            0X5E000000
0061 #endif
0062
0063 #define RPI_PERIPHERAL_SIZE      0x01000000
0064
0065 /**
0066  * @name Bus to Physical address translation
0067  *       Macro.
0068  * @{
0069  */
0070
0071 #define BUS_TO_PHY(x)            ((x) - BASE_OFFSET)
0072
0073 /** @} */
0074
0075 /**
0076  * @name Internal ARM Timer Registers
0077  *
0078  * @{
0079  */
0080
0081 #define BCM2835_CLOCK_FREQ       250000000
0082
0083 #define BCM2835_TIMER_BASE       (RPI_PERIPHERAL_BASE + 0xB400)
0084
0085 #define BCM2835_TIMER_LOD        (BCM2835_TIMER_BASE + 0x00)
0086 #define BCM2835_TIMER_VAL        (BCM2835_TIMER_BASE + 0x04)
0087 #define BCM2835_TIMER_CTL        (BCM2835_TIMER_BASE + 0x08)
0088 #define BCM2835_TIMER_CLI        (BCM2835_TIMER_BASE + 0x0C)
0089 #define BCM2835_TIMER_RIS        (BCM2835_TIMER_BASE + 0x10)
0090 #define BCM2835_TIMER_MIS        (BCM2835_TIMER_BASE + 0x14)
0091 #define BCM2835_TIMER_RLD        (BCM2835_TIMER_BASE + 0x18)
0092 #define BCM2835_TIMER_DIV        (BCM2835_TIMER_BASE + 0x1C)
0093 #define BCM2835_TIMER_CNT        (BCM2835_TIMER_BASE + 0x20)
0094
0095 #define BCM2835_TIMER_PRESCALE    0xF9
0096
0097 /** @} */
0098
0099 /**
0100  * @name Power Management and Watchdog  Registers
0101  *
0102  * @{
0103  */
0104
0105 #define BCM2835_PM_PASSWD_MAGIC  0x5a000000
0106
0107 #define BCM2835_PM_BASE          (RPI_PERIPHERAL_BASE + 0x100000)
0108
0109 #define BCM2835_PM_GNRIC         (BCM2835_PM_BASE + 0x00)
0110 #define BCM2835_PM_GNRIC_POWUP   0x00000001
0111 #define BCM2835_PM_GNRIC_POWOK   0x00000002
0112 #define BCM2835_PM_GNRIC_ISPOW   0x00000004
0113 #define BCM2835_PM_GNRIC_MEMREP  0x00000008
0114 #define BCM2835_PM_GNRIC_MRDONE  0x00000010
0115 #define BCM2835_PM_GNRIC_ISFUNC  0x00000020
0116 #define BCM2835_PM_GNRIC_RSTN    0x00000fc0
0117 #define BCM2835_PM_GNRIC_ENAB    0x00001000
0118 #define BCM2835_PM_GNRIC_CFG     0x007f0000
0119
0120 #define BCM2835_PM_AUDIO         (BCM2835_PM_BASE + 0x04)
0121 #define BCM2835_PM_AUDIO_APSM    0x000fffff
0122 #define BCM2835_PM_AUDIO_CTRLEN  0x00100000
0123 #define BCM2835_PM_AUDIO_RSTN    0x00200000
0124
0125 #define BCM2835_PM_STATUS        (BCM2835_PM_BASE + 0x18)
0126
0127 #define BCM2835_PM_RSTC          (BCM2835_PM_BASE + 0x1c)
0128 #define BCM2835_PM_RSTC_DRCFG    0x00000003
0129 #define BCM2835_PM_RSTC_WRCFG    0x00000030
0130 #define BCM2835_PM_RSTC_WRCFG_FULL   0x00000020
0131 #define BCM2835_PM_RSTC_SRCFG    0x00000300
0132 #define BCM2835_PM_RSTC_QRCFG    0x00003000
0133 #define BCM2835_PM_RSTC_FRCFG    0x00030000
0134 #define BCM2835_PM_RSTC_HRCFG    0x00300000
0135
0136 #define BCM2835_PM_RSTS          (BCM2835_PM_BASE + 0x20)
0137 #define BCM2835_PM_RSTS_HADDRQ   0x00000001
0138 #define BCM2835_PM_RSTS_HADDRF   0x00000002
0139 #define BCM2835_PM_RSTS_HADDRH   0x00000004
0140 #define BCM2835_PM_RSTS_HADWRQ   0x00000010
0141 #define BCM2835_PM_RSTS_HADWRF   0x00000020
0142 #define BCM2835_PM_RSTS_HADWRH   0x00000040
0143 #define BCM2835_PM_RSTS_HADSRQ   0x00000100
0144 #define BCM2835_PM_RSTS_HADSRF   0x00000200
0145 #define BCM2835_PM_RSTS_HADSRH   0x00000400
0146 #define BCM2835_PM_RSTS_HADPOR   0x00001000
0147
0148 #define BCM2835_PM_WDOG          (BCM2835_PM_BASE + 0x24)
0149
0150 /** @} */
0151
0152 /**
0153  * @name GPIO Registers
0154  *
0155  * @{
0156  */
0157
0158 #define BCM2835_GPIO_REGS_BASE   (RPI_PERIPHERAL_BASE + 0x200000)
0159
0160 #define BCM2835_GPIO_GPFSEL1     (BCM2835_GPIO_REGS_BASE + 0x04)
0161 #define BCM2835_GPIO_GPSET0      (BCM2835_GPIO_REGS_BASE + 0x1C)
0162 #define BCM2835_GPIO_GPCLR0      (BCM2835_GPIO_REGS_BASE + 0x28)
0163 #define BCM2835_GPIO_GPLEV0      (BCM2835_GPIO_REGS_BASE + 0x34)
0164 #define BCM2835_GPIO_GPEDS0      (BCM2835_GPIO_REGS_BASE + 0x40)
0165 #define BCM2835_GPIO_GPREN0      (BCM2835_GPIO_REGS_BASE + 0x4C)
0166 #define BCM2835_GPIO_GPFEN0      (BCM2835_GPIO_REGS_BASE + 0x58)
0167 #define BCM2835_GPIO_GPHEN0      (BCM2835_GPIO_REGS_BASE + 0x64)
0168 #define BCM2835_GPIO_GPLEN0      (BCM2835_GPIO_REGS_BASE + 0x70)
0169 #define BCM2835_GPIO_GPAREN0     (BCM2835_GPIO_REGS_BASE + 0x7C)
0170 #define BCM2835_GPIO_GPAFEN0     (BCM2835_GPIO_REGS_BASE + 0x88)
0171 #define BCM2835_GPIO_GPPUD       (BCM2835_GPIO_REGS_BASE + 0x94)
0172 #define BCM2835_GPIO_GPPUDCLK0   (BCM2835_GPIO_REGS_BASE + 0x98)
0173
0174 /** @} */
0175
0176 /**
0177  * @name AUX Registers
0178  *
0179  * @{
0180  */
0181
0182 #define BCM2835_AUX_BASE         (RPI_PERIPHERAL_BASE + 0x215000)
0183
0184 #define AUX_ENABLES              (BCM2835_AUX_BASE + 0x04)
0185 #define AUX_MU_IO_REG            (BCM2835_AUX_BASE + 0x40)
0186 #define AUX_MU_IER_REG           (BCM2835_AUX_BASE + 0x44)
0187 #define AUX_MU_IIR_REG           (BCM2835_AUX_BASE + 0x48)
0188 #define AUX_MU_LCR_REG           (BCM2835_AUX_BASE + 0x4C)
0189 #define AUX_MU_MCR_REG           (BCM2835_AUX_BASE + 0x50)
0190 #define AUX_MU_LSR_REG           (BCM2835_AUX_BASE + 0x54)
0191 #define AUX_MU_MSR_REG           (BCM2835_AUX_BASE + 0x58)
0192 #define AUX_MU_SCRATCH           (BCM2835_AUX_BASE + 0x5C)
0193 #define AUX_MU_CNTL_REG          (BCM2835_AUX_BASE + 0x60)
0194 #define AUX_MU_STAT_REG          (BCM2835_AUX_BASE + 0x64)
0195 #define AUX_MU_BAUD_REG          (BCM2835_AUX_BASE + 0x68)
0196
0197 /** @} */
0198
0199 /** @} */
0200
0201 /**
0202  * @name I2C (BSC) Registers
0203  *
0204  * @{
0205  */
0206
0207 #define BCM2835_I2C_BASE           (RPI_PERIPHERAL_BASE + 0x804000)
0208
0209 #define BCM2835_I2C_C              (BCM2835_I2C_BASE + 0x00)
0210 #define BCM2835_I2C_S              (BCM2835_I2C_BASE + 0x04)
0211 #define BCM2835_I2C_DLEN           (BCM2835_I2C_BASE + 0x08)
0212 #define BCM2835_I2C_A              (BCM2835_I2C_BASE + 0x0C)
0213 #define BCM2835_I2C_FIFO           (BCM2835_I2C_BASE + 0x10)
0214 #define BCM2835_I2C_DIV            (BCM2835_I2C_BASE + 0x14)
0215 #define BCM2835_I2C_DEL            (BCM2835_I2C_BASE + 0x18)
0216 #define BCM2835_I2C_CLKT           (BCM2835_I2C_BASE + 0x1C)
0217
0218 /** @} */
0219
0220 /**
0221  * @name SPI Registers
0222  *
0223  * @{
0224  */
0225
0226 #define BCM2835_SPI_BASE           (RPI_PERIPHERAL_BASE + 0x204000)
0227
0228 #define BCM2835_SPI_CS             (BCM2835_SPI_BASE + 0x00)
0229 #define BCM2835_SPI_FIFO           (BCM2835_SPI_BASE + 0x04)
0230 #define BCM2835_SPI_CLK            (BCM2835_SPI_BASE + 0x08)
0231 #define BCM2835_SPI_DLEN           (BCM2835_SPI_BASE + 0x0C)
0232 #define BCM2835_SPI_LTOH           (BCM2835_SPI_BASE + 0x10)
0233 #define BCM2835_SPI_DC             (BCM2835_SPI_BASE + 0x14)
0234
0235 /** @} */
0236
0237 /**
0238  * @name I2C/SPI slave BSC Registers
0239  *
0240  * @{
0241  */
0242
0243 #define BCM2835_I2C_SPI_BASE       (RPI_PERIPHERAL_BASE + 0x214000)
0244
0245 #define BCM2835_I2C_SPI_DR         (BCM2835_I2C_SPI_BASE + 0x00)
0246 #define BCM2835_I2C_SPI_RSR        (BCM2835_I2C_SPI_BASE + 0x04)
0247 #define BCM2835_I2C_SPI_SLV        (BCM2835_I2C_SPI_BASE + 0x08)
0248 #define BCM2835_I2C_SPI_CR         (BCM2835_I2C_SPI_BASE + 0x0C)
0249 #define BCM2835_I2C_SPI_FR         (BCM2835_I2C_SPI_BASE + 0x10)
0250 #define BCM2835_I2C_SPI_IFLS       (BCM2835_I2C_SPI_BASE + 0x14)
0251 #define BCM2835_I2C_SPI_IMSC       (BCM2835_I2C_SPI_BASE + 0x18)
0252 #define BCM2835_I2C_SPI_RIS        (BCM2835_I2C_SPI_BASE + 0x1C)
0253 #define BCM2835_I2C_SPI_MIS        (BCM2835_I2C_SPI_BASE + 0x20)
0254 #define BCM2835_I2C_SPI_ICR        (BCM2835_I2C_SPI_BASE + 0x24)
0255 #define BCM2835_I2C_SPI_DMACR      (BCM2835_I2C_SPI_BASE + 0x28)
0256 #define BCM2835_I2C_SPI_TDR        (BCM2835_I2C_SPI_BASE + 0x2C)
0257 #define BCM2835_I2C_SPI_GPUSTAT    (BCM2835_I2C_SPI_BASE + 0x30)
0258 #define BCM2835_I2C_SPI_HCTRL      (BCM2835_I2C_SPI_BASE + 0x34)
0259
0260 /** @} */
0261
0262 /**
0263  * @name IRQ Registers
0264  *
0265  * @{
0266  */
0267
0268 #define BCM2835_BASE_INTC         (RPI_PERIPHERAL_BASE + 0xB200)
0269
0270 #define BCM2835_IRQ_BASIC         (BCM2835_BASE_INTC + 0x00)
0271 #define BCM2835_IRQ_PENDING1      (BCM2835_BASE_INTC + 0x04)
0272 #define BCM2835_IRQ_PENDING2      (BCM2835_BASE_INTC + 0x08)
0273 #define BCM2835_IRQ_FIQ_CTRL      (BCM2835_BASE_INTC + 0x0C)
0274 #define BCM2835_IRQ_ENABLE1       (BCM2835_BASE_INTC + 0x10)
0275 #define BCM2835_IRQ_ENABLE2       (BCM2835_BASE_INTC + 0x14)
0276 #define BCM2835_IRQ_ENABLE_BASIC  (BCM2835_BASE_INTC + 0x18)
0277 #define BCM2835_IRQ_DISABLE1      (BCM2835_BASE_INTC + 0x1C)
0278 #define BCM2835_IRQ_DISABLE2      (BCM2835_BASE_INTC + 0x20)
0279 #define BCM2835_IRQ_DISABLE_BASIC (BCM2835_BASE_INTC + 0x24)
0280
0281 /** @} */
0282
0283 /**
0284  * @name GPU Timer Registers
0285  *
0286  * @{
0287  */
0288
0289 /**
0290  * NOTE: The GPU uses Compare registers 0 and 2 for
0291  *       it's own RTOS. 1 and 3 are available for use in
0292  *       RTEMS.
0293  */
0294 #define BCM2835_GPU_TIMER_BASE    (RPI_PERIPHERAL_BASE + 0x3000)
0295
0296 #define BCM2835_GPU_TIMER_CS      (BCM2835_GPU_TIMER_BASE + 0x00)
0297 #define BCM2835_GPU_TIMER_CS_M0   0x00000001
0298 #define BCM2835_GPU_TIMER_CS_M1   0x00000002
0299 #define BCM2835_GPU_TIMER_CS_M2   0x00000004
0300 #define BCM2835_GPU_TIMER_CS_M3   0x00000008
0301 #define BCM2835_GPU_TIMER_CLO     (BCM2835_GPU_TIMER_BASE + 0x04)
0302 #define BCM2835_GPU_TIMER_CHI     (BCM2835_GPU_TIMER_BASE + 0x08)
0303 #define BCM2835_GPU_TIMER_C0      (BCM2835_GPU_TIMER_BASE + 0x0C)
0304 #define BCM2835_GPU_TIMER_C1      (BCM2835_GPU_TIMER_BASE + 0x10)
0305 #define BCM2835_GPU_TIMER_C2      (BCM2835_GPU_TIMER_BASE + 0x14)
0306 #define BCM2835_GPU_TIMER_C3      (BCM2835_GPU_TIMER_BASE + 0x18)
0307
0308 /** @} */
0309
0310 /**
0311  * @name EMMC Registers
0312  *
0313  * @{
0314  */
0315
0316 /**
0317  * NOTE: Since the SD controller follows the SDHCI standard,
0318  *       the rtems-libbsd tree already provides the remaining registers.
0319  */
0320
0321 #define BCM2835_EMMC_BASE              (RPI_PERIPHERAL_BASE + 0x300000)
0322
0323 /** @} */
0324
0325 /**
0326 * @name Mailbox Registers
0327 *
0328 * @{
0329 */
0330
0331 #define BCM2835_MBOX_BASE   (RPI_PERIPHERAL_BASE+0xB880)
0332
0333 #define BCM2835_MBOX_PEEK   (BCM2835_MBOX_BASE+0x10)
0334 #define BCM2835_MBOX_READ   (BCM2835_MBOX_BASE+0x00)
0335 #define BCM2835_MBOX_WRITE  (BCM2835_MBOX_BASE+0x20)
0336 #define BCM2835_MBOX_STATUS (BCM2835_MBOX_BASE+0x18)
0337 #define BCM2835_MBOX_SENDER (BCM2835_MBOX_BASE+0x14)
0338 #define BCM2835_MBOX_CONFIG (BCM2835_MBOX_BASE+0x1C)
0339
0340 #define BCM2835_MBOX_FULL   0x80000000
0341 #define BCM2835_MBOX_EMPTY  0x40000000
0342
0343 /** @} */
0344
0345 /**
0346 * @name Mailbox Channels
0347 *
0348 * @{
0349 */
0350
0351 /* Power Manager channel */
0352 #define BCM2835_MBOX_CHANNEL_PM         0
0353 /* Framebuffer channel */
0354 #define BCM2835_MBOX_CHANNEL_FB         1
0355  /* Virtual UART channel */
0356 #define BCM2835_MBOX_CHANNEL_VUART      2
0357  /* VCHIQ channel */
0358 #define BCM2835_MBOX_CHANNEL_VCHIQ      3
0359  /* LEDs channel */
0360 #define BCM2835_MBOX_CHANNEL_LED        4
0361  /* Button channel */
0362 #define BCM2835_MBOX_CHANNEL_BUTTON     5
0363  /* Touch screen channel */
0364 #define BCM2835_MBOX_CHANNEL_TOUCHS     6
0365 /* Property tags (ARM <-> VC) channel */
0366 #define BCM2835_MBOX_CHANNEL_PROP_AVC   8
0367  /* Property tags (VC <-> ARM) channel */
0368 #define BCM2835_MBOX_CHANNEL_PROP_VCA   9
0369
0370 /** @} */
0371
0372 /**
0373 * @name USB Registers
0374 *
0375 * @{
0376 */
0377
0378 #define BCM2835_USB_BASE    (RPI_PERIPHERAL_BASE + 0x980000) /* DTC_OTG USB controller */
0379
0380 /** @} */
0381
0382 /**
0383  * @name Raspberry Pi 2 CPU Cores Local Peripherals
0384  *
0385  * @{
0386  */
0387
0388 #define BCM2836_CORE_LOCAL_PERIPH_BASE    0x40000000
0389 #define BCM2836_CORE_LOCAL_PERIPH_SIZE    0x00040000
0390
0391 /** @} */
0392
0393 /**
0394  * @name Raspberry Pi 2 Mailbox Register Defines
0395  *
0396  * @{
0397  */
0398
0399 #define BCM2836_MAILBOX_0_WRITE_SET_BASE  0x40000080
0400 #define BCM2836_MAILBOX_1_WRITE_SET_BASE  0x40000084
0401 #define BCM2836_MAILBOX_2_WRITE_SET_BASE  0x40000088
0402 #define BCM2836_MAILBOX_3_WRITE_SET_BASE  0x4000008C
0403 #define BCM2836_MAILBOX_0_READ_CLEAR_BASE 0x400000C0
0404 #define BCM2836_MAILBOX_1_READ_CLEAR_BASE 0x400000C4
0405 #define BCM2836_MAILBOX_2_READ_CLEAR_BASE 0x400000C8
0406 #define BCM2836_MAILBOX_3_READ_CLEAR_BASE 0x400000CC
0407
0408 /** @} */
0409
0410 /**
0411  * @name Raspberry Pi 2 Core Timer
0412  *
0413  * @{
0414  */
0415
0416 #define BCM2836_CORE_TIMER_CTRL           0x40000000
0417
0418 #define BCM2836_CORE_TIMER_CTRL_APB_CLK   0x00000100
0419 #define BCM2836_CORE_TIMER_CTRL_INC_2     0x00000200
0420
0421 #define BCM2836_CORE_TIMER_PRESCALER      0x40000008
0422
0423 #define BCM2836_CORE_TIMER_LS32           0x4000001C
0424 #define BCM2836_CORE_TIMER_MS32           0x40000020
0425
0426 /** @} */
0427
0428 /**
0429  * @name Raspberry Pi 2 Local Timer
0430  *
0431  * @{
0432  */
0433
0434 #define BCM2836_LOCAL_TIMER_CTRL          0x40000034
0435
0436 #define BCM2836_LOCAL_TIMER_CTRL_IRQ_FLAG 0x80000000
0437 #define BCM2836_LOCAL_TIMER_CTRL_IRQ_EN   0x20000000
0438 #define BCM2836_LOCAL_TIMER_CTRL_TIMER_EN 0x10000000
0439 #define BCM2836_LOCAL_TIMER_RELOAD        0x0FFFFFFF
0440
0441 #define BCM2836_LOCAL_TIMER_IRQ_RELOAD    0x40000038
0442
0443 #define BCM2836_LOCAL_TIMER_IRQ_CLEAR     0x80000000
0444 #define BCM2836_LOCAL_TIMER_RELOAD_NOW    0x40000000
0445
0446 #define BCM2836_LOCAL_TIMER_IRQ_ROUTING   0x40000024
0447 #define BCM2836_LOCAL_TIMER_ROU_CORE0_IRQ       0x00
0448 #define BCM2836_LOCAL_TIMER_ROU_CORE1_IRQ       0x01
0449 #define BCM2836_LOCAL_TIMER_ROU_CORE2_IRQ       0x02
0450 #define BCM2836_LOCAL_TIMER_ROU_CORE3_IRQ       0x03
0451 #define BCM2836_LOCAL_TIMER_ROU_CORE0_FIQ       0x04
0452 #define BCM2836_LOCAL_TIMER_ROU_CORE1_FIQ       0x05
0453 #define BCM2836_LOCAL_TIMER_ROU_CORE2_FIQ       0x06
0454 #define BCM2836_LOCAL_TIMER_ROU_CORE3_FIQ       0x07
0455
0456 /** @} */
0457
0458 /**
0459  * @name Raspberry Pi 2 IRQ Routing
0460  *
0461  * @{
0462  */
0463
0464 #define BCM2836_GPU_IRQ_ROUTING           0x4000000C
0465
0466 #define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE0 0x00000000
0467 #define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE1 0x00000001
0468 #define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE2 0x00000002
0469 #define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE4 0x00000003
0470
0471 #define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE0 0x00000000
0472 #define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE1 0x00000004
0473 #define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE2 0x00000008
0474 #define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C
0475
0476 #define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C
0477
0478
0479 /** @} */
0480
0481 /**
0482  * @name Raspberry Pi 2 Interrupt Register Defines
0483  *
0484  * @{
0485  */
0486
0487 /* Timers interrupt control registers */
0488 #define BCM2836_CORE0_TIMER_IRQ_CTRL_BASE 0x40000040
0489 #define BCM2836_CORE1_TIMER_IRQ_CTRL_BASE 0x40000044
0490 #define BCM2836_CORE2_TIMER_IRQ_CTRL_BASE 0x40000048
0491 #define BCM2836_CORE3_TIMER_IRQ_CTRL_BASE 0x4000004C
0492
0493 #define BCM2836_CORE_TIMER_IRQ_CTRL(cpuidx) \
0494   (BCM2836_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx))
0495
0496 /*
0497  * Where to route timer interrupt to, IRQ/FIQ
0498  * Setting both the IRQ and FIQ bit gives an FIQ
0499  */
0500 #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_IRQ  0x01
0501 #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_IRQ  0x02
0502 #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_IRQ  0x04
0503 #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_IRQ  0x08
0504 #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_FIQ  0x10
0505 #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_FIQ  0x20
0506 #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_FIQ  0x40
0507 #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_FIQ  0x80
0508
0509 /* CPU mailbox registers */
0510 #define BCM2836_MAILBOX_IRQ_CTRL_BASE     0x40000050
0511 #define BCM2836_MAILBOX_IRQ_CTRL(cpuidx) \
0512   (BCM2836_MAILBOX_IRQ_CTRL_BASE + 0x4 * (cpuidx))
0513 /*
0514  * Where to route mailbox interrupt to, IRQ/FIQ
0515  * Setting both the IRQ and FIQ bit gives an FIQ
0516  */
0517 #define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_IRQ      0x01
0518 #define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_IRQ      0x02
0519 #define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_IRQ      0x04
0520 #define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_IRQ      0x08
0521 #define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_FIQ      0x10
0522 #define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_FIQ      0x20
0523 #define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_FIQ      0x40
0524 #define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_FIQ      0x80
0525
0526 #define BCM2836_IRQ_SOURCE_REG_BASE       0x40000060
0527 #define BCM2836_IRQ_SOURCE_REG(cpuidx) \
0528   (BCM2836_IRQ_SOURCE_REG_BASE + 0x4 * (cpuidx))
0529
0530 #define BCM2836_FIQ_SOURCE_REG_BASE       0x40000070
0531 #define BCM2836_FIQ_SOURCE_REG(cpuidx) \
0532   (BCM2836_FIQ_SOURCE_REG_BASE + 0x4 * (cpuidx))
0533
0534 #define BCM2836_IRQ_SOURCE_TIMER0         0x00000001
0535 #define BCM2836_IRQ_SOURCE_TIMER1         0x00000002
0536 #define BCM2836_IRQ_SOURCE_TIMER2         0x00000004
0537 #define BCM2836_IRQ_SOURCE_TIMER3         0x00000008
0538 #define BCM2836_IRQ_SOURCE_MBOX0          0x00000010
0539 #define BCM2836_IRQ_SOURCE_MBOX1          0x00000020
0540 #define BCM2836_IRQ_SOURCE_MBOX2          0x00000040
0541 #define BCM2836_IRQ_SOURCE_MBOX3          0x00000080
0542 #define BCM2836_IRQ_SOURCE_GPU            0x00000100
0543 #define BCM2836_IRQ_SOURCE_PMU            0x00000200
0544 #define BCM2836_IRQ_SOURCE_LOCAL_TIMER    0x00000800
0545
0546 /** @} */
0547
0548 #endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */