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File indexing completed on 2025-05-11 08:23:04

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002 
0003 /* @file
0004  *
0005  * @ingroup RTEMSBSPsARMLPC32XX
0006  *
0007  * @brief Implementations of interrupt mechanisms for Time Test 27
0008  */
0009 
0010 /*
0011  * Copyright (c) 2010 embedded brains GmbH & Co. KG
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0023  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0025  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0026  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0027  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0028  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0029  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0030  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0031  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0032  * POSSIBILITY OF SUCH DAMAGE.
0033  */
0034 
0035 #ifndef _RTEMS_TMTEST27
0036 #error "This is an RTEMS internal file you must not include directly."
0037 #endif
0038 
0039 #ifndef __tm27_h
0040 #define __tm27_h
0041 
0042 #include <rtems.h>
0043 
0044 #include <bsp/lpc32xx.h>
0045 #include <bsp/irq.h>
0046 #include <bsp/irq-generic.h>
0047 
0048 #define MUST_WAIT_FOR_INTERRUPT 1
0049 
0050 #define LPC32XX_TM27_TIMER (&lpc32xx.timer_2)
0051 
0052 #define LPC32XX_TM27_IRQ LPC32XX_IRQ_TIMER_2
0053 
0054 static inline void Install_tm27_vector( rtems_interrupt_handler handler )
0055 {
0056   static rtems_interrupt_entry entry;
0057   volatile lpc_timer *timer = LPC32XX_TM27_TIMER;
0058 
0059   LPC32XX_TIMCLK_CTRL1 |= 1U << 4;
0060 
0061   timer->tcr = LPC_TIMER_TCR_RST;
0062   timer->ctcr = 0x0;
0063   timer->pr = 0x0;
0064   timer->ir = 0xff;
0065   timer->mcr = LPC_TIMER_MCR_MR0_INTR | LPC_TIMER_MCR_MR0_STOP |
0066     LPC_TIMER_MCR_MR0_RST;
0067   timer->ccr = 0x0;
0068   timer->emr = 0x0;
0069   timer->mr0 = 0x1;
0070 
0071   rtems_interrupt_entry_initialize(
0072     &entry,
0073     handler,
0074     NULL,
0075     "tm27"
0076   );
0077   (void) rtems_interrupt_entry_install(
0078     LPC32XX_TM27_IRQ,
0079     RTEMS_INTERRUPT_SHARED,
0080     &entry
0081   );
0082 }
0083 
0084 static inline void Cause_tm27_intr(void)
0085 {
0086   volatile lpc_timer *timer = LPC32XX_TM27_TIMER;
0087 
0088   timer->tcr = LPC_TIMER_TCR_EN;
0089 }
0090 
0091 static inline void Clear_tm27_intr(void)
0092 {
0093   volatile lpc_timer *timer = LPC32XX_TM27_TIMER;
0094 
0095   timer->ir = LPC_TIMER_IR_MR0;
0096   (void) rtems_interrupt_set_priority(
0097     LPC32XX_TM27_IRQ,
0098     LPC32XX_IRQ_PRIORITY_LOWEST
0099   );
0100 }
0101 
0102 static inline void Lower_tm27_intr(void)
0103 {
0104   bsp_interrupt_vector_enable(LPC32XX_TM27_IRQ);
0105   (void) rtems_interrupt_set_priority(
0106     LPC32XX_TM27_IRQ,
0107     LPC32XX_IRQ_PRIORITY_HIGHEST
0108   );
0109 }
0110 
0111 #endif /* __tm27_h */