include/bsp/mmu.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup lpc32xx_mmu
0007  *
0008  * @brief MMU support API.
0009  */
0010
0011 /*
0012  * Copyright (C) 2009, 2011 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_ARM_LPC32XX_MMU_H
0037 #define LIBBSP_ARM_LPC32XX_MMU_H
0038
0039 #include <libcpu/arm-cp15.h>
0040
0041 #ifdef __cplusplus
0042 extern "C" {
0043 #endif /* __cplusplus */
0044
0045 /**
0046  * @defgroup lpc32xx_mmu MMU Support
0047  *
0048  * @ingroup RTEMSBSPsARMLPC32XX
0049  *
0050  * @brief MMU support.
0051  *
0052  * @{
0053  */
0054
0055 #define LPC32XX_MMU_CLIENT_DOMAIN 15U
0056
0057 #define LPC32XX_MMU_READ_ONLY \
0058   ((LPC32XX_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \
0059     | ARM_MMU_SECT_DEFAULT)
0060
0061 #define LPC32XX_MMU_READ_ONLY_CACHED \
0062   (LPC32XX_MMU_READ_ONLY | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
0063
0064 #define LPC32XX_MMU_READ_WRITE \
0065   ((LPC32XX_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \
0066     | ARM_MMU_SECT_AP_0 \
0067     | ARM_MMU_SECT_DEFAULT)
0068
0069 #define LPC32XX_MMU_READ_WRITE_CACHED \
0070   (LPC32XX_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
0071
0072 /**
0073  * @brief Sets the @a section_flags for the address range [@a begin, @a end).
0074  *
0075  * @return Previous section flags of the first modified entry.
0076  */
0077 uint32_t lpc32xx_set_translation_table_entries(
0078   const void *begin,
0079   const void *end,
0080   uint32_t section_flags
0081 );
0082
0083 /** @} */
0084
0085 #ifdef __cplusplus
0086 }
0087 #endif /* __cplusplus */
0088
0089 #endif /* LIBBSP_ARM_LPC32XX_MMU_H */