include/bsp/lpc32xx.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup lpc32xx_reg
0005  *
0006  * @brief Register base addresses.
0007  */
0008
0009 /*
0010  * Copyright (C) 2009, 2010 embedded brains GmbH & Co. KG
0011  *
0012  * The license and distribution terms for this file may be
0013  * found in the file LICENSE in this distribution or at
0014  * http:
0015  */
0016
0017 #ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H
0018 #define LIBBSP_ARM_LPC32XX_LPC32XX_H
0019
0020 #include <stdint.h>
0021
0022 #include <bsp/utility.h>
0023 #include <bsp/lpc-timer.h>
0024 #include <bsp/lpc-dma.h>
0025 #include <bsp/lpc-i2s.h>
0026 #include <bsp/lpc-emc.h>
0027
0028 /**
0029  * @defgroup lpc32xx_reg Register Definitions
0030  *
0031  * @ingroup RTEMSBSPsARMLPC32XX
0032  *
0033  * @brief Register definitions.
0034  *
0035  * @{
0036  */
0037
0038 /**
0039  * @name Register Base Addresses
0040  *
0041  * @{
0042  */
0043
0044 #define LPC32XX_BASE_ADC 0x40048000
0045 #define LPC32XX_BASE_SYSCON 0x40004000
0046 #define LPC32XX_BASE_DEBUG_CTRL 0x40040000
0047 #define LPC32XX_BASE_DMA 0x31000000
0048 #define LPC32XX_BASE_EMC 0x31080000
0049 #define LPC32XX_BASE_EMC_CS_0 0xe0000000
0050 #define LPC32XX_BASE_EMC_CS_1 0xe1000000
0051 #define LPC32XX_BASE_EMC_CS_2 0xe2000000
0052 #define LPC32XX_BASE_EMC_CS_3 0xe3000000
0053 #define LPC32XX_BASE_EMC_DYCS_0 0x80000000
0054 #define LPC32XX_BASE_EMC_DYCS_1 0xa0000000
0055 #define LPC32XX_BASE_ETB_CFG 0x310c0000
0056 #define LPC32XX_BASE_ETB_DATA 0x310e0000
0057 #define LPC32XX_BASE_ETHERNET 0x31060000
0058 #define LPC32XX_BASE_GPIO 0x40028000
0059 #define LPC32XX_BASE_I2C_1 0x400a0000
0060 #define LPC32XX_BASE_I2C_2 0x400a8000
0061 #define LPC32XX_BASE_I2S_0 0x20094000
0062 #define LPC32XX_BASE_I2S_1 0x2009c000
0063 #define LPC32XX_BASE_IRAM 0x08000000
0064 #define LPC32XX_BASE_IROM 0x0c000000
0065 #define LPC32XX_BASE_KEYSCAN 0x40050000
0066 #define LPC32XX_BASE_LCD 0x31040000
0067 #define LPC32XX_BASE_MCPWM 0x400e8000
0068 #define LPC32XX_BASE_MIC 0x40008000
0069 #define LPC32XX_BASE_NAND_MLC 0x200a8000
0070 #define LPC32XX_BASE_NAND_SLC 0x20020000
0071 #define LPC32XX_BASE_PWM_1 0x4005c000
0072 #define LPC32XX_BASE_PWM_2 0x4005c004
0073 #define LPC32XX_BASE_PWM_3 0x4002c000
0074 #define LPC32XX_BASE_PWM_4 0x40030000
0075 #define LPC32XX_BASE_RTC 0x40024000
0076 #define LPC32XX_BASE_RTC_RAM 0x40024080
0077 #define LPC32XX_BASE_SDCARD 0x20098000
0078 #define LPC32XX_BASE_SIC_1 0x4000c000
0079 #define LPC32XX_BASE_SIC_2 0x40010000
0080 #define LPC32XX_BASE_SPI_1 0x20088000
0081 #define LPC32XX_BASE_SPI_2 0x20090000
0082 #define LPC32XX_BASE_SSP_0 0x20084000
0083 #define LPC32XX_BASE_SSP_1 0x2008c000
0084 #define LPC32XX_BASE_TIMER_0 0x40044000
0085 #define LPC32XX_BASE_TIMER_1 0x4004c000
0086 #define LPC32XX_BASE_TIMER_2 0x40058000
0087 #define LPC32XX_BASE_TIMER_3 0x40060000
0088 #define LPC32XX_BASE_TIMER_5 0x4002c000
0089 #define LPC32XX_BASE_TIMER_6 0x40030000
0090 #define LPC32XX_BASE_TIMER_HS 0x40038000
0091 #define LPC32XX_BASE_TIMER_MS 0x40034000
0092 #define LPC32XX_BASE_UART_1 0x40014000
0093 #define LPC32XX_BASE_UART_2 0x40018000
0094 #define LPC32XX_BASE_UART_3 0x40080000
0095 #define LPC32XX_BASE_UART_4 0x40088000
0096 #define LPC32XX_BASE_UART_5 0x40090000
0097 #define LPC32XX_BASE_UART_6 0x40098000
0098 #define LPC32XX_BASE_UART_7 0x4001c000
0099 #define LPC32XX_BASE_USB 0x31020000
0100 #define LPC32XX_BASE_USB_OTG_I2C 0x31020300
0101 #define LPC32XX_BASE_WDT 0x4003c000
0102
0103 /** @} */
0104
0105 /**
0106  * @name Miscanellanous Registers
0107  *
0108  * @{
0109  */
0110
0111 #define LPC32XX_U3CLK (*(volatile uint32_t *) 0x400040d0)
0112 #define LPC32XX_U4CLK (*(volatile uint32_t *) 0x400040d4)
0113 #define LPC32XX_U5CLK (*(volatile uint32_t *) 0x400040d8)
0114 #define LPC32XX_U6CLK (*(volatile uint32_t *) 0x400040dc)
0115 #define LPC32XX_IRDACLK (*(volatile uint32_t *) 0x400040e0)
0116 #define LPC32XX_UART_CTRL (*(volatile uint32_t *) 0x40054000)
0117 #define LPC32XX_UART_CLKMODE (*(volatile uint32_t *) 0x40054004)
0118 #define LPC32XX_UART_LOOP (*(volatile uint32_t *) 0x40054008)
0119 #define LPC32XX_SW_INT (*(volatile uint32_t *) 0x400040a8)
0120 #define LPC32XX_MAC_CLK_CTRL (*(volatile uint32_t *) 0x40004090)
0121 #define LPC32XX_USB_DIV (*(volatile uint32_t *) 0x4000401c)
0122 #define LPC32XX_OTG_CLK_CTRL (*(volatile uint32_t *) 0x31020ff4)
0123 #define LPC32XX_OTG_CLK_STAT (*(volatile uint32_t *) 0x31020ff8)
0124 #define LPC32XX_OTG_STAT_CTRL (*(volatile uint32_t *) 0x31020110)
0125 #define LPC32XX_I2C_RX (*(volatile uint32_t *) 0x31020300)
0126 #define LPC32XX_I2C_TX (*(volatile uint32_t *) 0x31020300)
0127 #define LPC32XX_I2C_STS (*(volatile uint32_t *) 0x31020304)
0128 #define LPC32XX_I2C_CTL (*(volatile uint32_t *) 0x31020308)
0129 #define LPC32XX_I2C_CLKHI (*(volatile uint32_t *) 0x3102030c)
0130 #define LPC32XX_I2C_CLKLO (*(volatile uint32_t *) 0x31020310)
0131 #define LPC32XX_PWR_CTRL (*(volatile uint32_t *) 0x40004044)
0132 #define LPC32XX_OSC_CTRL (*(volatile uint32_t *) 0x4000404c)
0133 #define LPC32XX_SYSCLK_CTRL (*(volatile uint32_t *) 0x40004050)
0134 #define LPC32XX_PLL397_CTRL (*(volatile uint32_t *) 0x40004048)
0135 #define LPC32XX_HCLKPLL_CTRL (*(volatile uint32_t *) 0x40004058)
0136 #define LPC32XX_HCLKDIV_CTRL (*(volatile uint32_t *) 0x40004040)
0137 #define LPC32XX_TEST_CLK (*(volatile uint32_t *) 0x400040a4)
0138 #define LPC32XX_AUTOCLK_CTRL (*(volatile uint32_t *) 0x400040ec)
0139 #define LPC32XX_START_ER_PIN (*(volatile uint32_t *) 0x40004030)
0140 #define LPC32XX_START_ER_INT (*(volatile uint32_t *) 0x40004020)
0141 #define LPC32XX_P0_INTR_ER (*(volatile uint32_t *) 0x40004018)
0142 #define LPC32XX_START_SR_PIN (*(volatile uint32_t *) 0x40004038)
0143 #define LPC32XX_START_SR_INT (*(volatile uint32_t *) 0x40004028)
0144 #define LPC32XX_START_RSR_PIN (*(volatile uint32_t *) 0x40004034)
0145 #define LPC32XX_START_RSR_INT (*(volatile uint32_t *) 0x40004024)
0146 #define LPC32XX_START_APR_PIN (*(volatile uint32_t *) 0x4000403c)
0147 #define LPC32XX_START_APR_INT (*(volatile uint32_t *) 0x4000402c)
0148 #define LPC32XX_USB_CTRL (*(volatile uint32_t *) 0x40004064)
0149 #define LPC32XX_USBDIV_CTRL (*(volatile uint32_t *) 0x4000401c)
0150 #define LPC32XX_MS_CTRL (*(volatile uint32_t *) 0x40004080)
0151 #define LPC32XX_DMACLK_CTRL (*(volatile uint32_t *) 0x400040e8)
0152 #define LPC32XX_FLASHCLK_CTRL (*(volatile uint32_t *) 0x400040c8)
0153 #define LPC32XX_MACCLK_CTRL (*(volatile uint32_t *) 0x40004090)
0154 #define LPC32XX_LCDCLK_CTRL (*(volatile uint32_t *) 0x40004054)
0155 #define LPC32XX_I2S_CTRL (*(volatile uint32_t *) 0x4000407c)
0156 #define LPC32XX_SSP_CTRL (*(volatile uint32_t *) 0x40004078)
0157 #define LPC32XX_SPI_CTRL (*(volatile uint32_t *) 0x400040c4)
0158 #define LPC32XX_I2CCLK_CTRL (*(volatile uint32_t *) 0x400040ac)
0159 #define LPC32XX_TIMCLK_CTRL1 (*(volatile uint32_t *) 0x400040c0)
0160 #define LPC32XX_TIMCLK_CTRL (*(volatile uint32_t *) 0x400040bc)
0161 #define LPC32XX_ADCLK_CTRL (*(volatile uint32_t *) 0x400040b4)
0162 #define LPC32XX_ADCLK_CTRL1 (*(volatile uint32_t *) 0x40004060)
0163 #define LPC32XX_KEYCLK_CTRL (*(volatile uint32_t *) 0x400040b0)
0164 #define LPC32XX_PWMCLK_CTRL (*(volatile uint32_t *) 0x400040b8)
0165 #define LPC32XX_UARTCLK_CTRL (*(volatile uint32_t *) 0x400040e4)
0166 #define LPC32XX_POS0_IRAM_CTRL (*(volatile uint32_t *) 0x40004110)
0167 #define LPC32XX_POS1_IRAM_CTRL (*(volatile uint32_t *) 0x40004114)
0168 #define LPC32XX_SDRAMCLK_CTRL (*(volatile uint32_t *) 0x40004068)
0169
0170 /** @} */
0171
0172 /**
0173  * @name Power Control Register (PWR_CTRL)
0174  *
0175  * @{
0176  */
0177
0178 #define PWR_STOP BSP_BIT32(0)
0179 #define PWR_HIGHCORE_ALWAYS BSP_BIT32(1)
0180 #define PWR_NORMAL_RUN_MODE BSP_BIT32(2)
0181 #define PWR_SYSCLKEN_ALWAYS BSP_BIT32(3)
0182 #define PWR_SYSCLKEN_HIGH BSP_BIT32(4)
0183 #define PWR_HIGHCORE_HIGH BSP_BIT32(5)
0184 #define PWR_SDRAM_AUTO_REFRESH BSP_BIT32(7)
0185 #define PWR_UPDATE_EMCSREFREQ BSP_BIT32(8)
0186 #define PWR_EMCSREFREQ BSP_BIT32(9)
0187 #define PWR_HCLK_USES_PERIPH_CLK BSP_BIT32(10)
0188
0189 /** @} */
0190
0191 /**
0192  * @name HCLK PLL Control Register (HCLKPLL_CTRL)
0193  *
0194  * @{
0195  */
0196
0197 #define HCLK_PLL_LOCK BSP_BIT32(0)
0198 #define HCLK_PLL_M(val) BSP_FLD32(val, 1, 8)
0199 #define HCLK_PLL_M_GET(reg) BSP_FLD32GET(reg, 1, 8)
0200 #define HCLK_PLL_N(val) BSP_FLD32(val, 9, 10)
0201 #define HCLK_PLL_N_GET(reg) BSP_FLD32GET(reg, 9, 10)
0202 #define HCLK_PLL_P(val) BSP_FLD32(val, 11, 12)
0203 #define HCLK_PLL_P_GET(reg) BSP_FLD32GET(reg, 11, 12)
0204 #define HCLK_PLL_FBD_FCLKOUT BSP_BIT32(13)
0205 #define HCLK_PLL_DIRECT BSP_BIT32(14)
0206 #define HCLK_PLL_BYPASS BSP_BIT32(15)
0207 #define HCLK_PLL_POWER BSP_BIT32(16)
0208
0209 /** @} */
0210
0211 /**
0212  * @name HCLK Divider Control Register (HCLKDIV_CTRL)
0213  *
0214  * @{
0215  */
0216
0217 #define HCLK_DIV_HCLK(val) BSP_FLD32(val, 0, 1)
0218 #define HCLK_DIV_HCLK_GET(reg) BSP_FLD32GET(reg, 0, 1)
0219 #define HCLK_DIV_PERIPH_CLK(val) BSP_FLD32(val, 2, 6)
0220 #define HCLK_DIV_PERIPH_CLK_GET(reg) BSP_FLD32GET(reg, 2, 6)
0221 #define HCLK_DIV_DDRAM_CLK(val) BSP_FLD32(val, 7, 8)
0222 #define HCLK_DIV_DDRAM_CLK_GET(reg) BSP_FLD32GET(reg, 7, 8)
0223
0224 /** @} */
0225
0226 /**
0227  * @name Timer Clock Control Register (TIMCLK_CTRL)
0228  *
0229  * @{
0230  */
0231
0232 #define TIMCLK_CTRL_WDT BSP_BIT32(0)
0233 #define TIMCLK_CTRL_HST BSP_BIT32(1)
0234
0235 /** @} */
0236
0237 #define LPC32XX_FILL(a, b, s) uint8_t reserved_ ## b [b - a - sizeof(s)]
0238 #define LPC32XX_RESERVE(a, b) uint8_t reserved_ ## b [b - a]
0239
0240 typedef struct {
0241 } lpc32xx_nand_slc;
0242
0243 typedef struct {
0244 } lpc32xx_ssp;
0245
0246 typedef struct {
0247 } lpc32xx_spi;
0248
0249 typedef struct {
0250 } lpc32xx_sd_card;
0251
0252 typedef struct {
0253 } lpc32xx_usb;
0254
0255 typedef struct {
0256 } lpc32xx_lcd;
0257
0258 typedef struct {
0259 } lpc32xx_etb;
0260
0261 typedef struct {
0262 } lpc32xx_syscon;
0263
0264 typedef struct {
0265 } lpc32xx_uart_ctrl;
0266
0267 typedef struct {
0268 } lpc32xx_uart;
0269
0270 typedef struct {
0271 } lpc32xx_ms_timer;
0272
0273 typedef struct {
0274 } lpc32xx_hs_timer;
0275
0276 /**
0277  * @name Watchdog Timer Interrupt Status Register (WDTIM_INT)
0278  *
0279  * @{
0280  */
0281
0282 #define WDTTIM_INT_MATCH_INT BSP_BIT32(0)
0283
0284 /** @} */
0285
0286 /**
0287  * @name Watchdog Timer Control Register (WDTIM_CTRL)
0288  *
0289  * @{
0290  */
0291
0292 #define WDTTIM_CTRL_COUNT_ENAB BSP_BIT32(0)
0293 #define WDTTIM_CTRL_RESET_COUNT BSP_BIT32(1)
0294 #define WDTTIM_CTRL_PAUSE_EN BSP_BIT32(2)
0295
0296 /** @} */
0297
0298 /**
0299  * @name Watchdog Timer Match Control Register (WDTIM_MCTRL)
0300  *
0301  * @{
0302  */
0303
0304 #define WDTTIM_MCTRL_MR0_INT BSP_BIT32(0)
0305 #define WDTTIM_MCTRL_RESET_COUNT0 BSP_BIT32(1)
0306 #define WDTTIM_MCTRL_STOP_COUNT0 BSP_BIT32(2)
0307 #define WDTTIM_MCTRL_M_RES1 BSP_BIT32(3)
0308 #define WDTTIM_MCTRL_M_RES2 BSP_BIT32(4)
0309 #define WDTTIM_MCTRL_RESFRC1 BSP_BIT32(5)
0310 #define WDTTIM_MCTRL_RESFRC2 BSP_BIT32(6)
0311
0312 /** @} */
0313
0314 /**
0315  * @name Watchdog Timer External Match Control Register (WDTIM_EMR)
0316  *
0317  * @{
0318  */
0319
0320 #define WDTTIM_EMR_EXT_MATCH0 BSP_BIT32(0)
0321 #define WDTTIM_EMR_MATCH_CTRL(val) BSP_FLD32(val, 4, 5)
0322 #define WDTTIM_EMR_MATCH_CTRL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5)
0323
0324 /** @} */
0325
0326 /**
0327  * @name Watchdog Timer Reset Source Register (WDTIM_RES)
0328  *
0329  * @{
0330  */
0331
0332 #define WDTTIM_RES_WDT BSP_BIT32(0)
0333
0334 /** @} */
0335
0336 typedef struct {
0337   uint32_t intr;
0338   uint32_t ctrl;
0339   uint32_t counter;
0340   uint32_t mctrl;
0341   uint32_t match0;
0342   uint32_t emr;
0343   uint32_t pulse;
0344   uint32_t res;
0345 } lpc32xx_wdt;
0346
0347 typedef struct {
0348 } lpc32xx_debug;
0349
0350 typedef struct {
0351 } lpc32xx_adc;
0352
0353 typedef struct {
0354 } lpc32xx_keyscan;
0355
0356 typedef struct {
0357 } lpc32xx_pwm;
0358
0359 typedef struct {
0360 } lpc32xx_mcpwm;
0361
0362 typedef struct {
0363   uint32_t mac1;
0364   uint32_t mac2;
0365   uint32_t ipgt;
0366   uint32_t ipgr;
0367   uint32_t clrt;
0368   uint32_t maxf;
0369   uint32_t supp;
0370   uint32_t test;
0371   uint32_t mcfg;
0372   uint32_t mcmd;
0373   uint32_t madr;
0374   uint32_t mwtd;
0375   uint32_t mrdd;
0376   uint32_t mind;
0377   uint32_t reserved_0 [2];
0378   uint32_t sa0;
0379   uint32_t sa1;
0380   uint32_t sa2;
0381   uint32_t reserved_1 [45];
0382   uint32_t command;
0383   uint32_t status;
0384   uint32_t rxdescriptor;
0385   uint32_t rxstatus;
0386   uint32_t rxdescriptornum;
0387   uint32_t rxproduceindex;
0388   uint32_t rxconsumeindex;
0389   uint32_t txdescriptor;
0390   uint32_t txstatus;
0391   uint32_t txdescriptornum;
0392   uint32_t txproduceindex;
0393   uint32_t txconsumeindex;
0394   uint32_t reserved_2 [10];
0395   uint32_t tsv0;
0396   uint32_t tsv1;
0397   uint32_t rsv;
0398   uint32_t reserved_3 [3];
0399   uint32_t flowcontrolcnt;
0400   uint32_t flowcontrolsts;
0401   uint32_t reserved_4 [34];
0402   uint32_t rxfilterctrl;
0403   uint32_t rxfilterwolsts;
0404   uint32_t rxfilterwolclr;
0405   uint32_t reserved_5 [1];
0406   uint32_t hashfilterl;
0407   uint32_t hashfilterh;
0408   uint32_t reserved_6 [882];
0409   uint32_t intstatus;
0410   uint32_t intenable;
0411   uint32_t intclear;
0412   uint32_t intset;
0413   uint32_t reserved_7 [1];
0414   uint32_t powerdown;
0415 } lpc32xx_eth;
0416
0417 typedef struct {
0418   uint32_t er;
0419   uint32_t rsr;
0420   uint32_t sr;
0421   uint32_t apr;
0422   uint32_t atr;
0423   uint32_t itr;
0424 } lpc32xx_irq;
0425
0426 typedef struct {
0427   uint32_t p3_inp_state;
0428   uint32_t p3_outp_set;
0429   uint32_t p3_outp_clr;
0430   uint32_t p3_outp_state;
0431   uint32_t p2_dir_set;
0432   uint32_t p2_dir_clr;
0433   uint32_t p2_dir_state;
0434   uint32_t p2_inp_state;
0435   uint32_t p2_outp_set;
0436   uint32_t p2_outp_clr;
0437   uint32_t p2_mux_set;
0438   uint32_t p2_mux_clr;
0439   uint32_t p2_mux_state;
0440   LPC32XX_RESERVE(0x034, 0x040);
0441   uint32_t p0_inp_state;
0442   uint32_t p0_outp_set;
0443   uint32_t p0_outp_clr;
0444   uint32_t p0_outp_state;
0445   uint32_t p0_dir_set;
0446   uint32_t p0_dir_clr;
0447   uint32_t p0_dir_state;
0448   LPC32XX_RESERVE(0x05c, 0x060);
0449   uint32_t p1_inp_state;
0450   uint32_t p1_outp_set;
0451   uint32_t p1_outp_clr;
0452   uint32_t p1_outp_state;
0453   uint32_t p1_dir_set;
0454   uint32_t p1_dir_clr;
0455   uint32_t p1_dir_state;
0456   LPC32XX_RESERVE(0x07c, 0x110);
0457   uint32_t p3_mux_set;
0458   uint32_t p3_mux_clr;
0459   uint32_t p3_mux_state;
0460   LPC32XX_RESERVE(0x11c, 0x120);
0461   uint32_t p0_mux_set;
0462   uint32_t p0_mux_clr;
0463   uint32_t p0_mux_state;
0464   LPC32XX_RESERVE(0x12c, 0x130);
0465   uint32_t p1_mux_set;
0466   uint32_t p1_mux_clr;
0467   uint32_t p1_mux_state;
0468 } lpc32xx_gpio;
0469
0470 typedef struct {
0471   uint32_t rx_or_tx;
0472   uint32_t stat;
0473   uint32_t ctrl;
0474   uint32_t clk_hi;
0475   uint32_t clk_lo;
0476   uint32_t adr;
0477   uint32_t rxfl;
0478   uint32_t txfl;
0479   uint32_t rxb;
0480   uint32_t txb;
0481   uint32_t s_tx;
0482   uint32_t s_txfl;
0483 } lpc32xx_i2c;
0484
0485 typedef struct {
0486   uint32_t ucount;
0487   uint32_t dcount;
0488   uint32_t match0;
0489   uint32_t match1;
0490   uint32_t ctrl;
0491   uint32_t intstat;
0492   uint32_t key;
0493   uint32_t sram [32];
0494 } lpc32xx_rtc;
0495
0496 typedef struct {
0497   uint32_t control;
0498   uint32_t status;
0499   uint32_t timeout;
0500   uint32_t reserved_0 [5];
0501 } lpc32xx_emc_ahb;
0502
0503 typedef struct {
0504   union {
0505     uint32_t w32;
0506     uint16_t w16;
0507     uint8_t w8;
0508   } buff;
0509   uint32_t reserved_0 [8191];
0510   union {
0511     uint32_t w32;
0512     uint16_t w16;
0513     uint8_t w8;
0514   } data;
0515   uint32_t reserved_1 [8191];
0516   uint32_t cmd;
0517   uint32_t addr;
0518   uint32_t ecc_enc;
0519   uint32_t ecc_dec;
0520   uint32_t ecc_auto_enc;
0521   uint32_t ecc_auto_dec;
0522   uint32_t rpr;
0523   uint32_t wpr;
0524   uint32_t rubp;
0525   uint32_t robp;
0526   uint32_t sw_wp_add_low;
0527   uint32_t sw_wp_add_hig;
0528   uint32_t icr;
0529   uint32_t time;
0530   uint32_t irq_mr;
0531   uint32_t irq_sr;
0532   uint32_t reserved_2;
0533   uint32_t lock_pr;
0534   uint32_t isr;
0535   uint32_t ceh;
0536 } lpc32xx_nand_mlc;
0537
0538 typedef struct {
0539   lpc32xx_nand_slc nand_slc;
0540   LPC32XX_FILL(0x20020000, 0x20084000, lpc32xx_nand_slc);
0541   lpc32xx_ssp ssp_0;
0542   LPC32XX_FILL(0x20084000, 0x20088000, lpc32xx_ssp);
0543   lpc32xx_spi spi_1;
0544   LPC32XX_FILL(0x20088000, 0x2008c000, lpc32xx_spi);
0545   lpc32xx_ssp ssp_1;
0546   LPC32XX_FILL(0x2008c000, 0x20090000, lpc32xx_ssp);
0547   lpc32xx_spi spi_2;
0548   LPC32XX_FILL(0x20090000, 0x20094000, lpc32xx_spi);
0549   lpc_i2s i2s_0;
0550   LPC32XX_FILL(0x20094000, 0x20098000, lpc_i2s);
0551   lpc32xx_sd_card sd_card;
0552   LPC32XX_FILL(0x20098000, 0x2009c000, lpc32xx_sd_card);
0553   lpc_i2s i2s_1;
0554   LPC32XX_FILL(0x2009c000, 0x200a8000, lpc_i2s);
0555   lpc32xx_nand_mlc nand_mlc;
0556   LPC32XX_FILL(0x200a8000, 0x31000000, lpc32xx_nand_mlc);
0557   lpc_dma dma;
0558   LPC32XX_FILL(0x31000000, 0x31020000, lpc_dma);
0559   lpc32xx_usb usb;
0560   LPC32XX_FILL(0x31020000, 0x31040000, lpc32xx_usb);
0561   lpc32xx_lcd lcd;
0562   LPC32XX_FILL(0x31040000, 0x31060000, lpc32xx_lcd);
0563   lpc32xx_eth eth;
0564   LPC32XX_FILL(0x31060000, 0x31080000, lpc32xx_eth);
0565   lpc_emc emc;
0566   LPC32XX_FILL(0x31080000, 0x31080400, lpc_emc);
0567   lpc32xx_emc_ahb emc_ahb [5];
0568   LPC32XX_FILL(0x31080400, 0x310c0000, lpc32xx_emc_ahb [5]);
0569   lpc32xx_etb etb;
0570   LPC32XX_FILL(0x310c0000, 0x40004000, lpc32xx_etb);
0571   lpc32xx_syscon syscon;
0572   LPC32XX_FILL(0x40004000, 0x40008000, lpc32xx_syscon);
0573   lpc32xx_irq mic;
0574   LPC32XX_FILL(0x40008000, 0x4000c000, lpc32xx_irq);
0575   lpc32xx_irq sic_1;
0576   LPC32XX_FILL(0x4000c000, 0x40010000, lpc32xx_irq);
0577   lpc32xx_irq sic_2;
0578   LPC32XX_FILL(0x40010000, 0x40014000, lpc32xx_irq);
0579   lpc32xx_uart uart_1;
0580   LPC32XX_FILL(0x40014000, 0x40018000, lpc32xx_uart);
0581   lpc32xx_uart uart_2;
0582   LPC32XX_FILL(0x40018000, 0x4001c000, lpc32xx_uart);
0583   lpc32xx_uart uart_7;
0584   LPC32XX_FILL(0x4001c000, 0x40024000, lpc32xx_uart);
0585   lpc32xx_rtc rtc;
0586   LPC32XX_FILL(0x40024000, 0x40028000, lpc32xx_rtc);
0587   lpc32xx_gpio gpio;
0588   LPC32XX_FILL(0x40028000, 0x4002c000, lpc32xx_gpio);
0589   lpc_timer timer_4;
0590   LPC32XX_FILL(0x4002c000, 0x40030000, lpc_timer);
0591   lpc_timer timer_5;
0592   LPC32XX_FILL(0x40030000, 0x40034000, lpc_timer);
0593   lpc32xx_ms_timer ms_timer;
0594   LPC32XX_FILL(0x40034000, 0x40038000, lpc32xx_ms_timer);
0595   lpc32xx_hs_timer hs_timer;
0596   LPC32XX_FILL(0x40038000, 0x4003c000, lpc32xx_hs_timer);
0597   lpc32xx_wdt wdt;
0598   LPC32XX_FILL(0x4003c000, 0x40040000, lpc32xx_wdt);
0599   lpc32xx_debug debug;
0600   LPC32XX_FILL(0x40040000, 0x40044000, lpc32xx_debug);
0601   lpc_timer timer_0;
0602   LPC32XX_FILL(0x40044000, 0x40048000, lpc_timer);
0603   lpc32xx_adc adc;
0604   LPC32XX_FILL(0x40048000, 0x4004c000, lpc32xx_adc);
0605   lpc_timer timer_1;
0606   LPC32XX_FILL(0x4004c000, 0x40050000, lpc_timer);
0607   lpc32xx_keyscan keyscan;
0608   LPC32XX_FILL(0x40050000, 0x40054000, lpc32xx_keyscan);
0609   lpc32xx_uart_ctrl uart_ctrl;
0610   LPC32XX_FILL(0x40054000, 0x40058000, lpc32xx_uart_ctrl);
0611   lpc_timer timer_2;
0612   LPC32XX_FILL(0x40058000, 0x4005c000, lpc_timer);
0613   lpc32xx_pwm pwm_1_and_pwm_2;
0614   LPC32XX_FILL(0x4005c000, 0x40060000, lpc32xx_pwm);
0615   lpc_timer timer3;
0616   LPC32XX_FILL(0x40060000, 0x40080000, lpc_timer);
0617   lpc32xx_uart uart_3;
0618   LPC32XX_FILL(0x40080000, 0x40088000, lpc32xx_uart);
0619   lpc32xx_uart uart_4;
0620   LPC32XX_FILL(0x40088000, 0x40090000, lpc32xx_uart);
0621   lpc32xx_uart uart_5;
0622   LPC32XX_FILL(0x40090000, 0x40098000, lpc32xx_uart);
0623   lpc32xx_uart uart_6;
0624   LPC32XX_FILL(0x40098000, 0x400a0000, lpc32xx_uart);
0625   lpc32xx_i2c i2c_1;
0626   LPC32XX_FILL(0x400a0000, 0x400a8000, lpc32xx_i2c);
0627   lpc32xx_i2c i2c_2;
0628   LPC32XX_FILL(0x400a8000, 0x400e8000, lpc32xx_i2c);
0629   lpc32xx_mcpwm mcpwm;
0630 } lpc32xx_registers;
0631
0632 extern volatile lpc32xx_registers lpc32xx;
0633
0634 /** @} */
0635
0636 #endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */